1package xiangshan.backend.issue 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 7import utility.{GTimer, GatedValidRegNext, HasCircularQueuePtrHelper, SelectOne, XSPerfAccumulate, XSPerfHistogram} 8import xiangshan._ 9import xiangshan.backend.Bundles._ 10import xiangshan.backend.issue.EntryBundles._ 11import xiangshan.backend.decode.{ImmUnion, Imm_LUI_LOAD} 12import xiangshan.backend.datapath.DataConfig._ 13import xiangshan.backend.datapath.DataSource 14import xiangshan.backend.fu.{FuConfig, FuType} 15import xiangshan.mem.{LqPtr, MemWaitUpdateReq, SqPtr} 16import xiangshan.backend.rob.RobPtr 17import xiangshan.backend.datapath.NewPipelineConnect 18import xiangshan.backend.fu.vector.Bundles.VSew 19 20class IssueQueue(params: IssueBlockParams)(implicit p: Parameters) extends LazyModule with HasXSParameter { 21 override def shouldBeInlined: Boolean = false 22 23 implicit val iqParams: IssueBlockParams = params 24 lazy val module: IssueQueueImp = iqParams.schdType match { 25 case IntScheduler() => new IssueQueueIntImp(this) 26 case FpScheduler() => new IssueQueueFpImp(this) 27 case VfScheduler() => new IssueQueueVfImp(this) 28 case MemScheduler() => 29 if (iqParams.StdCnt == 0 && !iqParams.isVecMemIQ) new IssueQueueMemAddrImp(this) 30 else if (iqParams.isVecMemIQ) new IssueQueueVecMemImp(this) 31 else new IssueQueueIntImp(this) 32 case _ => null 33 } 34} 35 36class IssueQueueStatusBundle(numEnq: Int, numEntries: Int) extends Bundle { 37 val empty = Output(Bool()) 38 val full = Output(Bool()) 39 val validCnt = Output(UInt(log2Ceil(numEntries + 1).W)) 40 val leftVec = Output(Vec(numEnq + 1, Bool())) 41} 42 43class IssueQueueDeqRespBundle(implicit p:Parameters, params: IssueBlockParams) extends EntryDeqRespBundle 44 45class IssueQueueIO()(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 46 // Inputs 47 val flush = Flipped(ValidIO(new Redirect)) 48 val enq = Vec(params.numEnq, Flipped(DecoupledIO(new DynInst))) 49 50 val og0Resp = Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle))) 51 val og1Resp = Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle))) 52 val og2Resp = Option.when(params.needOg2Resp)(Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle)))) 53 val finalIssueResp = Option.when(params.LdExuCnt > 0 || params.VlduCnt > 0)(Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle)))) 54 val memAddrIssueResp = Option.when(params.LdExuCnt > 0)(Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle)))) 55 val vecLoadIssueResp = Option.when(params.VlduCnt > 0)(Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle)))) 56 val wbBusyTableRead = Input(params.genWbFuBusyTableReadBundle) 57 val wbBusyTableWrite = Output(params.genWbFuBusyTableWriteBundle) 58 val wakeupFromWB: MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = Flipped(params.genWBWakeUpSinkValidBundle) 59 val wakeupFromIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(params.genIQWakeUpSinkValidBundle) 60 val vlFromIntIsZero = Input(Bool()) 61 val vlFromIntIsVlmax = Input(Bool()) 62 val vlFromVfIsZero = Input(Bool()) 63 val vlFromVfIsVlmax = Input(Bool()) 64 val og0Cancel = Input(ExuVec()) 65 val og1Cancel = Input(ExuVec()) 66 val ldCancel = Vec(backendParams.LduCnt + backendParams.HyuCnt, Flipped(new LoadCancelIO)) 67 val replaceRCIdx = Option.when(params.needWriteRegCache)(Vec(params.numDeq, Input(UInt(RegCacheIdxWidth.W)))) 68 69 // Outputs 70 val wakeupToIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = params.genIQWakeUpSourceValidBundle 71 val status = Output(new IssueQueueStatusBundle(params.numEnq, params.numEntries)) 72 val validCntDeqVec = Output(Vec(params.numDeq,UInt(params.numEntries.U.getWidth.W))) 73 // val statusNext = Output(new IssueQueueStatusBundle(params.numEnq)) 74 75 val deqDelay: MixedVec[DecoupledIO[IssueQueueIssueBundle]] = params.genIssueDecoupledBundle// = deq.cloneType 76 def allWakeUp = wakeupFromWB ++ wakeupFromIQ 77} 78 79class IssueQueueImp(override val wrapper: IssueQueue)(implicit p: Parameters, val params: IssueBlockParams) 80 extends LazyModuleImp(wrapper) 81 with HasXSParameter { 82 83 override def desiredName: String = s"${params.getIQName}" 84 85 println(s"[IssueQueueImp] ${params.getIQName} wakeupFromWB(${io.wakeupFromWB.size}), " + 86 s"wakeup exu in(${params.wakeUpInExuSources.size}): ${params.wakeUpInExuSources.map(_.name).mkString("{",",","}")}, " + 87 s"wakeup exu out(${params.wakeUpOutExuSources.size}): ${params.wakeUpOutExuSources.map(_.name).mkString("{",",","}")}, " + 88 s"numEntries: ${params.numEntries}, numRegSrc: ${params.numRegSrc}, " + 89 s"numEnq: ${params.numEnq}, numSimp: ${params.numSimp}, numComp: ${params.numComp}, numDeq: ${params.numDeq}, " + 90 s"isAllSimp: ${params.isAllSimp}, isAllComp: ${params.isAllComp}") 91 92 require(params.numExu <= 2, "IssueQueue has not supported more than 2 deq ports") 93 require(params.numEnq <= 2, "IssueQueue has not supported more than 2 enq ports") 94 require(params.numSimp == 0 || params.numSimp >= params.numEnq, "numSimp should be 0 or at least not less than numEnq") 95 require(params.numComp == 0 || params.numComp >= params.numEnq, "numComp should be 0 or at least not less than numEnq") 96 97 val deqFuCfgs : Seq[Seq[FuConfig]] = params.exuBlockParams.map(_.fuConfigs) 98 val allDeqFuCfgs : Seq[FuConfig] = params.exuBlockParams.flatMap(_.fuConfigs) 99 val fuCfgsCnt : Map[FuConfig, Int] = allDeqFuCfgs.groupBy(x => x).map { case (cfg, cfgSeq) => (cfg, cfgSeq.length) } 100 val commonFuCfgs : Seq[FuConfig] = fuCfgsCnt.filter(_._2 > 1).keys.toSeq 101 val wakeupFuLatencyMaps : Seq[Map[FuType.OHType, Int]] = params.exuBlockParams.map(x => x.wakeUpFuLatencyMap) 102 103 println(s"[IssueQueueImp] ${params.getIQName} fuLatencyMaps: ${wakeupFuLatencyMaps}") 104 println(s"[IssueQueueImp] ${params.getIQName} commonFuCfgs: ${commonFuCfgs.map(_.name)}") 105 lazy val io = IO(new IssueQueueIO()) 106 107 // Modules 108 val entries = Module(new Entries) 109 val fuBusyTableWrite = params.exuBlockParams.map { case x => Option.when(x.latencyValMax > 0)(Module(new FuBusyTableWrite(x.fuLatencyMap))) } 110 val fuBusyTableRead = params.exuBlockParams.map { case x => Option.when(x.latencyValMax > 0)(Module(new FuBusyTableRead(x.fuLatencyMap))) } 111 val intWbBusyTableWrite = params.exuBlockParams.map { case x => Option.when(x.intLatencyCertain)(Module(new FuBusyTableWrite(x.intFuLatencyMap))) } 112 val intWbBusyTableRead = params.exuBlockParams.map { case x => Option.when(x.intLatencyCertain)(Module(new FuBusyTableRead(x.intFuLatencyMap))) } 113 val fpWbBusyTableWrite = params.exuBlockParams.map { case x => Option.when(x.fpLatencyCertain)(Module(new FuBusyTableWrite(x.fpFuLatencyMap))) } 114 val fpWbBusyTableRead = params.exuBlockParams.map { case x => Option.when(x.fpLatencyCertain)(Module(new FuBusyTableRead(x.fpFuLatencyMap))) } 115 val vfWbBusyTableWrite = params.exuBlockParams.map { case x => Option.when(x.vfLatencyCertain)(Module(new FuBusyTableWrite(x.vfFuLatencyMap))) } 116 val vfWbBusyTableRead = params.exuBlockParams.map { case x => Option.when(x.vfLatencyCertain)(Module(new FuBusyTableRead(x.vfFuLatencyMap))) } 117 val v0WbBusyTableWrite = params.exuBlockParams.map { case x => Option.when(x.v0LatencyCertain)(Module(new FuBusyTableWrite(x.v0FuLatencyMap))) } 118 val v0WbBusyTableRead = params.exuBlockParams.map { case x => Option.when(x.v0LatencyCertain)(Module(new FuBusyTableRead(x.v0FuLatencyMap))) } 119 val vlWbBusyTableWrite = params.exuBlockParams.map { case x => Option.when(x.vlLatencyCertain)(Module(new FuBusyTableWrite(x.vlFuLatencyMap))) } 120 val vlWbBusyTableRead = params.exuBlockParams.map { case x => Option.when(x.vlLatencyCertain)(Module(new FuBusyTableRead(x.vlFuLatencyMap))) } 121 122 class WakeupQueueFlush extends Bundle { 123 val redirect = ValidIO(new Redirect) 124 val ldCancel = Vec(backendParams.LduCnt + backendParams.HyuCnt, new LoadCancelIO) 125 val og0Fail = Output(Bool()) 126 val og1Fail = Output(Bool()) 127 } 128 129 private def flushFunc(exuInput: ExuInput, flush: WakeupQueueFlush, stage: Int): Bool = { 130 val redirectFlush = exuInput.robIdx.needFlush(flush.redirect) 131 val loadDependencyFlush = LoadShouldCancel(exuInput.loadDependency, flush.ldCancel) 132 val ogFailFlush = stage match { 133 case 1 => flush.og0Fail 134 case 2 => flush.og1Fail 135 case _ => false.B 136 } 137 redirectFlush || loadDependencyFlush || ogFailFlush 138 } 139 140 private def modificationFunc(exuInput: ExuInput): ExuInput = { 141 val newExuInput = WireDefault(exuInput) 142 newExuInput.loadDependency match { 143 case Some(deps) => deps.zip(exuInput.loadDependency.get).foreach(x => x._1 := x._2 << 1) 144 case None => 145 } 146 newExuInput 147 } 148 149 private def lastConnectFunc(exuInput: ExuInput, newInput: ExuInput): ExuInput = { 150 val lastExuInput = WireDefault(exuInput) 151 val newExuInput = WireDefault(newInput) 152 newExuInput.elements.foreach { case (name, data) => 153 if (lastExuInput.elements.contains(name)) { 154 data := lastExuInput.elements(name) 155 } 156 } 157 if (newExuInput.pdestCopy.nonEmpty && !lastExuInput.pdestCopy.nonEmpty) { 158 newExuInput.pdestCopy.get.foreach(_ := lastExuInput.pdest) 159 } 160 if (newExuInput.rfWenCopy.nonEmpty && !lastExuInput.rfWenCopy.nonEmpty) { 161 newExuInput.rfWenCopy.get.foreach(_ := lastExuInput.rfWen.get) 162 } 163 if (newExuInput.fpWenCopy.nonEmpty && !lastExuInput.fpWenCopy.nonEmpty) { 164 newExuInput.fpWenCopy.get.foreach(_ := lastExuInput.fpWen.get) 165 } 166 if (newExuInput.vecWenCopy.nonEmpty && !lastExuInput.vecWenCopy.nonEmpty) { 167 newExuInput.vecWenCopy.get.foreach(_ := lastExuInput.vecWen.get) 168 } 169 if (newExuInput.v0WenCopy.nonEmpty && !lastExuInput.v0WenCopy.nonEmpty) { 170 newExuInput.v0WenCopy.get.foreach(_ := lastExuInput.v0Wen.get) 171 } 172 if (newExuInput.vlWenCopy.nonEmpty && !lastExuInput.vlWenCopy.nonEmpty) { 173 newExuInput.vlWenCopy.get.foreach(_ := lastExuInput.vlWen.get) 174 } 175 if (newExuInput.loadDependencyCopy.nonEmpty && !lastExuInput.loadDependencyCopy.nonEmpty) { 176 newExuInput.loadDependencyCopy.get.foreach(_ := lastExuInput.loadDependency.get) 177 } 178 newExuInput 179 } 180 181 val wakeUpQueues: Seq[Option[MultiWakeupQueue[ExuInput, WakeupQueueFlush]]] = params.exuBlockParams.map { x => Option.when(x.isIQWakeUpSource && !x.hasLoadExu)(Module( 182 new MultiWakeupQueue(new ExuInput(x), new ExuInput(x, x.copyWakeupOut, x.copyNum), new WakeupQueueFlush, x.wakeUpFuLatancySet, flushFunc, modificationFunc, lastConnectFunc) 183 ))} 184 val deqBeforeDly = Wire(params.genIssueDecoupledBundle) 185 186 val intWbBusyTableIn = io.wbBusyTableRead.map(_.intWbBusyTable) 187 val fpWbBusyTableIn = io.wbBusyTableRead.map(_.fpWbBusyTable) 188 val vfWbBusyTableIn = io.wbBusyTableRead.map(_.vfWbBusyTable) 189 val v0WbBusyTableIn = io.wbBusyTableRead.map(_.v0WbBusyTable) 190 val vlWbBusyTableIn = io.wbBusyTableRead.map(_.vlWbBusyTable) 191 192 val intWbBusyTableOut = io.wbBusyTableWrite.map(_.intWbBusyTable) 193 val fpWbBusyTableOut = io.wbBusyTableWrite.map(_.fpWbBusyTable) 194 val vfWbBusyTableOut = io.wbBusyTableWrite.map(_.vfWbBusyTable) 195 val v0WbBusyTableOut = io.wbBusyTableWrite.map(_.v0WbBusyTable) 196 val vlWbBusyTableOut = io.wbBusyTableWrite.map(_.vlWbBusyTable) 197 198 val intDeqRespSetOut = io.wbBusyTableWrite.map(_.intDeqRespSet) 199 val fpDeqRespSetOut = io.wbBusyTableWrite.map(_.fpDeqRespSet) 200 val vfDeqRespSetOut = io.wbBusyTableWrite.map(_.vfDeqRespSet) 201 val v0DeqRespSetOut = io.wbBusyTableWrite.map(_.v0DeqRespSet) 202 val vlDeqRespSetOut = io.wbBusyTableWrite.map(_.vlDeqRespSet) 203 204 val fuBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 205 val intWbBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 206 val fpWbBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 207 val vfWbBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 208 val v0WbBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 209 val vlWbBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 210 211 val s0_enqValidVec = io.enq.map(_.valid) 212 val s0_enqSelValidVec = Wire(Vec(params.numEnq, Bool())) 213 val s0_enqNotFlush = !io.flush.valid 214 val s0_enqBits = WireInit(VecInit(io.enq.map(_.bits))) 215 val s0_doEnqSelValidVec = s0_enqSelValidVec.map(_ && s0_enqNotFlush) //enqValid && notFlush && enqReady 216 217 218 val finalDeqSelValidVec = Wire(Vec(params.numDeq, Bool())) 219 val finalDeqSelOHVec = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 220 221 val validVec = VecInit(entries.io.valid.asBools) 222 val issuedVec = VecInit(entries.io.issued.asBools) 223 val requestForTrans = VecInit(validVec.zip(issuedVec).map(x => x._1 && !x._2)) 224 val canIssueVec = VecInit(entries.io.canIssue.asBools) 225 dontTouch(canIssueVec) 226 val deqFirstIssueVec = entries.io.isFirstIssue 227 228 val dataSources: Vec[Vec[DataSource]] = entries.io.dataSources 229 val finalDataSources: Vec[Vec[DataSource]] = VecInit(finalDeqSelOHVec.map(oh => Mux1H(oh, dataSources))) 230 val loadDependency: Vec[Vec[UInt]] = entries.io.loadDependency 231 val finalLoadDependency: IndexedSeq[Vec[UInt]] = VecInit(finalDeqSelOHVec.map(oh => Mux1H(oh, loadDependency))) 232 // (entryIdx)(srcIdx)(exuIdx) 233 val wakeUpL1ExuOH: Option[Vec[Vec[Vec[Bool]]]] = entries.io.srcWakeUpL1ExuOH 234 // (deqIdx)(srcIdx)(exuIdx) 235 val finalWakeUpL1ExuOH: Option[Vec[Vec[Vec[Bool]]]] = wakeUpL1ExuOH.map(x => VecInit(finalDeqSelOHVec.map(oh => Mux1H(oh, x)))) 236 237 val fuTypeVec = Wire(Vec(params.numEntries, FuType())) 238 val deqEntryVec = Wire(Vec(params.numDeq, ValidIO(new EntryBundle))) 239 val canIssueMergeAllBusy = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 240 val deqCanIssue = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 241 242 //deq 243 val enqEntryOldestSel = Wire(Vec(params.numDeq, ValidIO(UInt(params.numEnq.W)))) 244 val simpEntryOldestSel = Option.when(params.hasCompAndSimp)(Wire(Vec(params.numDeq + params.numEnq, ValidIO(UInt(params.numSimp.W))))) 245 val compEntryOldestSel = Option.when(params.hasCompAndSimp)(Wire(Vec(params.numDeq, ValidIO(UInt(params.numComp.W))))) 246 val othersEntryOldestSel = Wire(Vec(params.numDeq, ValidIO(UInt((params.numEntries - params.numEnq).W)))) 247 val deqSelValidVec = Wire(Vec(params.numDeq, Bool())) 248 val deqSelOHVec = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 249 val cancelDeqVec = Wire(Vec(params.numDeq, Bool())) 250 251 val subDeqSelValidVec = Option.when(params.deqFuSame)(Wire(Vec(params.numDeq, Bool()))) 252 val subDeqSelOHVec = Option.when(params.deqFuSame)(Wire(Vec(params.numDeq, UInt(params.numEntries.W)))) 253 val subDeqRequest = Option.when(params.deqFuSame)(Wire(UInt(params.numEntries.W))) 254 255 //trans 256 val simpEntryEnqSelVec = Option.when(params.hasCompAndSimp)(Wire(Vec(params.numEnq, UInt(params.numSimp.W)))) 257 val compEntryEnqSelVec = Option.when(params.hasCompAndSimp)(Wire(Vec(params.numEnq, UInt(params.numComp.W)))) 258 val othersEntryEnqSelVec = Option.when(params.isAllComp || params.isAllSimp)(Wire(Vec(params.numEnq, UInt((params.numEntries - params.numEnq).W)))) 259 val simpAgeDetectRequest = Option.when(params.hasCompAndSimp)(Wire(Vec(params.numDeq + params.numEnq, UInt(params.numSimp.W)))) 260 simpAgeDetectRequest.foreach(_ := 0.U.asTypeOf(simpAgeDetectRequest.get)) 261 262 // when vf exu (with og2) wake up int/mem iq (without og2), the wakeup signals should delay 1 cycle 263 // as vf exu's min latency is 1, we do not need consider og0cancel 264 val wakeupFromIQ = Wire(chiselTypeOf(io.wakeupFromIQ)) 265 wakeupFromIQ.zip(io.wakeupFromIQ).foreach { case (w, w_src) => 266 if (!params.inVfSchd && params.readVfRf && params.hasWakeupFromVf && w_src.bits.params.isVfExeUnit) { 267 val noCancel = !LoadShouldCancel(Some(w_src.bits.loadDependency), io.ldCancel) 268 w := RegNext(Mux(noCancel, w_src, 0.U.asTypeOf(w))) 269 w.bits.loadDependency.zip(w_src.bits.loadDependency).foreach{ case (ld, ld_src) => ld := RegNext(Mux(noCancel, ld_src << 1, 0.U.asTypeOf(ld))) } 270 } else { 271 w := w_src 272 } 273 } 274 275 /** 276 * Connection of [[entries]] 277 */ 278 entries.io match { case entriesIO: EntriesIO => 279 entriesIO.flush := io.flush 280 entriesIO.enq.zipWithIndex.foreach { case (enq, enqIdx) => 281 enq.valid := s0_doEnqSelValidVec(enqIdx) 282 enq.bits.status.robIdx := s0_enqBits(enqIdx).robIdx 283 enq.bits.status.fuType := IQFuType.readFuType(VecInit(s0_enqBits(enqIdx).fuType.asBools), params.getFuCfgs.map(_.fuType)) 284 val numLsrc = s0_enqBits(enqIdx).srcType.size.min(enq.bits.status.srcStatus.map(_.srcType).size) 285 for(j <- 0 until numLsrc) { 286 enq.bits.status.srcStatus(j).psrc := s0_enqBits(enqIdx).psrc(j) 287 enq.bits.status.srcStatus(j).srcType := s0_enqBits(enqIdx).srcType(j) 288 enq.bits.status.srcStatus(j).srcState := (if (j < 3) { 289 Mux(SrcType.isVp(s0_enqBits(enqIdx).srcType(j)) && (s0_enqBits(enqIdx).psrc(j) === 0.U), 290 SrcState.rdy, 291 s0_enqBits(enqIdx).srcState(j)) 292 } else { 293 s0_enqBits(enqIdx).srcState(j) 294 }) 295 enq.bits.status.srcStatus(j).dataSources.value := (if (j < 3) { 296 MuxCase(DataSource.reg, Seq( 297 (SrcType.isXp(s0_enqBits(enqIdx).srcType(j)) && (s0_enqBits(enqIdx).psrc(j) === 0.U)) -> DataSource.zero, 298 SrcType.isNotReg(s0_enqBits(enqIdx).srcType(j)) -> DataSource.imm, 299 (SrcType.isVp(s0_enqBits(enqIdx).srcType(j)) && (s0_enqBits(enqIdx).psrc(j) === 0.U)) -> DataSource.v0, 300 )) 301 } else { 302 MuxCase(DataSource.reg, Seq( 303 SrcType.isNotReg(s0_enqBits(enqIdx).srcType(j)) -> DataSource.imm, 304 )) 305 }) 306 enq.bits.status.srcStatus(j).srcLoadDependency := VecInit(s0_enqBits(enqIdx).srcLoadDependency(j).map(x => x << 1)) 307 if(params.hasIQWakeUp) { 308 enq.bits.status.srcStatus(j).srcWakeUpL1ExuOH.get := 0.U.asTypeOf(ExuVec()) 309 } 310 enq.bits.status.srcStatus(j).useRegCache.foreach(_ := s0_enqBits(enqIdx).useRegCache(j)) 311 enq.bits.status.srcStatus(j).regCacheIdx.foreach(_ := s0_enqBits(enqIdx).regCacheIdx(j)) 312 } 313 enq.bits.status.blocked := false.B 314 enq.bits.status.issued := false.B 315 enq.bits.status.firstIssue := false.B 316 enq.bits.status.issueTimer := "b11".U 317 enq.bits.status.deqPortIdx := 0.U 318 enq.bits.imm.foreach(_ := s0_enqBits(enqIdx).imm) 319 enq.bits.payload := s0_enqBits(enqIdx) 320 } 321 entriesIO.og0Resp.zipWithIndex.foreach { case (og0Resp, i) => 322 og0Resp := io.og0Resp(i) 323 } 324 entriesIO.og1Resp.zipWithIndex.foreach { case (og1Resp, i) => 325 og1Resp := io.og1Resp(i) 326 } 327 if (params.needOg2Resp) { 328 entriesIO.og2Resp.get.zipWithIndex.foreach { case (og2Resp, i) => 329 og2Resp := io.og2Resp.get(i) 330 } 331 } 332 if (params.isLdAddrIQ || params.isHyAddrIQ) { 333 entriesIO.fromLoad.get.finalIssueResp.zipWithIndex.foreach { case (finalIssueResp, i) => 334 finalIssueResp := io.finalIssueResp.get(i) 335 } 336 entriesIO.fromLoad.get.memAddrIssueResp.zipWithIndex.foreach { case (memAddrIssueResp, i) => 337 memAddrIssueResp := io.memAddrIssueResp.get(i) 338 } 339 } 340 if (params.isVecLduIQ) { 341 entriesIO.vecLdIn.get.finalIssueResp.zipWithIndex.foreach { case (resp, i) => 342 resp := io.finalIssueResp.get(i) 343 } 344 entriesIO.vecLdIn.get.resp.zipWithIndex.foreach { case (resp, i) => 345 resp := io.vecLoadIssueResp.get(i) 346 } 347 } 348 for(deqIdx <- 0 until params.numDeq) { 349 entriesIO.deqReady(deqIdx) := deqBeforeDly(deqIdx).ready 350 entriesIO.deqSelOH(deqIdx).valid := deqSelValidVec(deqIdx) 351 entriesIO.deqSelOH(deqIdx).bits := deqSelOHVec(deqIdx) 352 entriesIO.enqEntryOldestSel(deqIdx) := enqEntryOldestSel(deqIdx) 353 entriesIO.simpEntryOldestSel.foreach(_(deqIdx) := simpEntryOldestSel.get(deqIdx)) 354 entriesIO.compEntryOldestSel.foreach(_(deqIdx) := compEntryOldestSel.get(deqIdx)) 355 entriesIO.othersEntryOldestSel.foreach(_(deqIdx) := othersEntryOldestSel(deqIdx)) 356 entriesIO.subDeqRequest.foreach(_(deqIdx) := subDeqRequest.get) 357 entriesIO.subDeqSelOH.foreach(_(deqIdx) := subDeqSelOHVec.get(deqIdx)) 358 } 359 entriesIO.wakeUpFromWB := io.wakeupFromWB 360 entriesIO.wakeUpFromIQ := wakeupFromIQ 361 entriesIO.vlFromIntIsZero := io.vlFromIntIsZero 362 entriesIO.vlFromIntIsVlmax := io.vlFromIntIsVlmax 363 entriesIO.vlFromVfIsZero := io.vlFromVfIsZero 364 entriesIO.vlFromVfIsVlmax := io.vlFromVfIsVlmax 365 entriesIO.og0Cancel := io.og0Cancel 366 entriesIO.og1Cancel := io.og1Cancel 367 entriesIO.ldCancel := io.ldCancel 368 entriesIO.simpEntryDeqSelVec.foreach(_ := VecInit(simpEntryOldestSel.get.takeRight(params.numEnq).map(_.bits))) 369 //output 370 fuTypeVec := entriesIO.fuType 371 deqEntryVec := entriesIO.deqEntry 372 cancelDeqVec := entriesIO.cancelDeqVec 373 simpEntryEnqSelVec.foreach(_ := entriesIO.simpEntryEnqSelVec.get) 374 compEntryEnqSelVec.foreach(_ := entriesIO.compEntryEnqSelVec.get) 375 othersEntryEnqSelVec.foreach(_ := entriesIO.othersEntryEnqSelVec.get) 376 } 377 378 379 s0_enqSelValidVec := s0_enqValidVec.zip(io.enq).map{ case (enqValid, enq) => enqValid && enq.ready} 380 381 protected val commonAccept: UInt = Cat(fuTypeVec.map(fuType => 382 FuType.FuTypeOrR(fuType, commonFuCfgs.map(_.fuType)) 383 ).reverse) 384 385 // if deq port can accept the uop 386 protected val canAcceptVec: Seq[UInt] = deqFuCfgs.map { fuCfgs: Seq[FuConfig] => 387 Cat(fuTypeVec.map(fuType => 388 FuType.FuTypeOrR(fuType, fuCfgs.map(_.fuType)) 389 ).reverse) 390 } 391 392 protected val deqCanAcceptVec: Seq[IndexedSeq[Bool]] = deqFuCfgs.map { fuCfgs: Seq[FuConfig] => 393 fuTypeVec.map(fuType => 394 FuType.FuTypeOrR(fuType, fuCfgs.map(_.fuType))) 395 } 396 397 canIssueMergeAllBusy.zipWithIndex.foreach { case (merge, i) => 398 val mergeFuBusy = { 399 if (fuBusyTableWrite(i).nonEmpty) canIssueVec.asUInt & (~fuBusyTableMask(i)) 400 else canIssueVec.asUInt 401 } 402 val mergeIntWbBusy = { 403 if (intWbBusyTableRead(i).nonEmpty) mergeFuBusy & (~intWbBusyTableMask(i)) 404 else mergeFuBusy 405 } 406 val mergefpWbBusy = { 407 if (fpWbBusyTableRead(i).nonEmpty) mergeIntWbBusy & (~fpWbBusyTableMask(i)) 408 else mergeIntWbBusy 409 } 410 val mergeVfWbBusy = { 411 if (vfWbBusyTableRead(i).nonEmpty) mergefpWbBusy & (~vfWbBusyTableMask(i)) 412 else mergefpWbBusy 413 } 414 val mergeV0WbBusy = { 415 if (v0WbBusyTableRead(i).nonEmpty) mergeVfWbBusy & (~v0WbBusyTableMask(i)) 416 else mergeVfWbBusy 417 } 418 val mergeVlWbBusy = { 419 if (vlWbBusyTableRead(i).nonEmpty) mergeV0WbBusy & (~vlWbBusyTableMask(i)) 420 else mergeV0WbBusy 421 } 422 merge := mergeVlWbBusy 423 } 424 425 deqCanIssue.zipWithIndex.foreach { case (req, i) => 426 req := canIssueMergeAllBusy(i) & VecInit(deqCanAcceptVec(i)).asUInt 427 } 428 dontTouch(fuTypeVec) 429 dontTouch(canIssueMergeAllBusy) 430 dontTouch(deqCanIssue) 431 432 if (params.numDeq == 2) { 433 require(params.deqFuSame || params.deqFuDiff, "The 2 deq ports need to be identical or completely different") 434 } 435 436 if (params.numDeq == 2 && params.deqFuSame) { 437 val subDeqPolicy = Module(new DeqPolicy()) 438 439 enqEntryOldestSel := DontCare 440 441 if (params.isAllComp || params.isAllSimp) { 442 othersEntryOldestSel(0) := AgeDetector(numEntries = params.numEntries - params.numEnq, 443 enq = othersEntryEnqSelVec.get, 444 canIssue = canIssueVec.asUInt(params.numEntries-1, params.numEnq) 445 ) 446 othersEntryOldestSel(1) := DontCare 447 448 subDeqPolicy.io.request := subDeqRequest.get 449 subDeqSelValidVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => oh.valid) 450 subDeqSelOHVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => oh.bits) 451 } 452 else { 453 simpAgeDetectRequest.get(0) := canIssueVec.asUInt(params.numEnq + params.numSimp - 1, params.numEnq) 454 simpAgeDetectRequest.get(1) := DontCare 455 simpAgeDetectRequest.get(params.numDeq) := VecInit(requestForTrans.drop(params.numEnq).take(params.numSimp)).asUInt 456 if (params.numEnq == 2) { 457 simpAgeDetectRequest.get(params.numDeq + 1) := VecInit(requestForTrans.drop(params.numEnq).take(params.numSimp)).asUInt & ~simpEntryOldestSel.get(params.numDeq).bits 458 } 459 460 simpEntryOldestSel.get := AgeDetector(numEntries = params.numSimp, 461 enq = simpEntryEnqSelVec.get, 462 canIssue = simpAgeDetectRequest.get 463 ) 464 465 compEntryOldestSel.get(0) := AgeDetector(numEntries = params.numComp, 466 enq = compEntryEnqSelVec.get, 467 canIssue = canIssueVec.asUInt(params.numEntries - 1, params.numEnq + params.numSimp) 468 ) 469 compEntryOldestSel.get(1) := DontCare 470 471 othersEntryOldestSel(0).valid := compEntryOldestSel.get(0).valid || simpEntryOldestSel.get(0).valid 472 othersEntryOldestSel(0).bits := Cat( 473 compEntryOldestSel.get(0).bits, 474 Fill(params.numSimp, !compEntryOldestSel.get(0).valid) & simpEntryOldestSel.get(0).bits, 475 ) 476 othersEntryOldestSel(1) := DontCare 477 478 subDeqPolicy.io.request := Reverse(subDeqRequest.get) 479 subDeqSelValidVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => oh.valid) 480 subDeqSelOHVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => Reverse(oh.bits)) 481 } 482 483 subDeqRequest.get := canIssueVec.asUInt & ~Cat(othersEntryOldestSel(0).bits, 0.U((params.numEnq).W)) 484 485 deqSelValidVec(0) := othersEntryOldestSel(0).valid || subDeqSelValidVec.get(1) 486 deqSelValidVec(1) := subDeqSelValidVec.get(0) 487 deqSelOHVec(0) := Mux(othersEntryOldestSel(0).valid, 488 Cat(othersEntryOldestSel(0).bits, 0.U((params.numEnq).W)), 489 subDeqSelOHVec.get(1)) & canIssueMergeAllBusy(0) 490 deqSelOHVec(1) := subDeqSelOHVec.get(0) & canIssueMergeAllBusy(1) 491 492 finalDeqSelValidVec.zip(finalDeqSelOHVec).zip(deqSelValidVec).zip(deqSelOHVec).zipWithIndex.foreach { case ((((selValid, selOH), deqValid), deqOH), i) => 493 selValid := deqValid && deqOH.orR 494 selOH := deqOH 495 } 496 } 497 else { 498 enqEntryOldestSel := NewAgeDetector(numEntries = params.numEnq, 499 enq = VecInit(s0_doEnqSelValidVec), 500 canIssue = VecInit(deqCanIssue.map(_(params.numEnq - 1, 0))) 501 ) 502 503 if (params.isAllComp || params.isAllSimp) { 504 othersEntryOldestSel := AgeDetector(numEntries = params.numEntries - params.numEnq, 505 enq = othersEntryEnqSelVec.get, 506 canIssue = VecInit(deqCanIssue.map(_(params.numEntries - 1, params.numEnq))) 507 ) 508 509 deqSelValidVec.zip(deqSelOHVec).zipWithIndex.foreach { case ((selValid, selOH), i) => 510 if (params.exuBlockParams(i).fuConfigs.contains(FuConfig.FakeHystaCfg)) { 511 selValid := false.B 512 selOH := 0.U.asTypeOf(selOH) 513 } else { 514 selValid := othersEntryOldestSel(i).valid || enqEntryOldestSel(i).valid 515 selOH := Cat(othersEntryOldestSel(i).bits, Fill(params.numEnq, !othersEntryOldestSel(i).valid) & enqEntryOldestSel(i).bits) 516 } 517 } 518 } 519 else { 520 othersEntryOldestSel := DontCare 521 522 deqCanIssue.zipWithIndex.foreach { case (req, i) => 523 simpAgeDetectRequest.get(i) := req(params.numEnq + params.numSimp - 1, params.numEnq) 524 } 525 simpAgeDetectRequest.get(params.numDeq) := VecInit(requestForTrans.drop(params.numEnq).take(params.numSimp)).asUInt 526 if (params.numEnq == 2) { 527 simpAgeDetectRequest.get(params.numDeq + 1) := VecInit(requestForTrans.drop(params.numEnq).take(params.numSimp)).asUInt & ~simpEntryOldestSel.get(params.numDeq).bits 528 } 529 530 simpEntryOldestSel.get := AgeDetector(numEntries = params.numSimp, 531 enq = simpEntryEnqSelVec.get, 532 canIssue = simpAgeDetectRequest.get 533 ) 534 535 compEntryOldestSel.get := AgeDetector(numEntries = params.numComp, 536 enq = compEntryEnqSelVec.get, 537 canIssue = VecInit(deqCanIssue.map(_(params.numEntries - 1, params.numEnq + params.numSimp))) 538 ) 539 540 deqSelValidVec.zip(deqSelOHVec).zipWithIndex.foreach { case ((selValid, selOH), i) => 541 if (params.exuBlockParams(i).fuConfigs.contains(FuConfig.FakeHystaCfg)) { 542 selValid := false.B 543 selOH := 0.U.asTypeOf(selOH) 544 } else { 545 selValid := compEntryOldestSel.get(i).valid || simpEntryOldestSel.get(i).valid || enqEntryOldestSel(i).valid 546 selOH := Cat( 547 compEntryOldestSel.get(i).bits, 548 Fill(params.numSimp, !compEntryOldestSel.get(i).valid) & simpEntryOldestSel.get(i).bits, 549 Fill(params.numEnq, !compEntryOldestSel.get(i).valid && !simpEntryOldestSel.get(i).valid) & enqEntryOldestSel(i).bits 550 ) 551 } 552 } 553 } 554 555 finalDeqSelValidVec.zip(finalDeqSelOHVec).zip(deqSelValidVec).zip(deqSelOHVec).zipWithIndex.foreach { case ((((selValid, selOH), deqValid), deqOH), i) => 556 selValid := deqValid 557 selOH := deqOH 558 } 559 } 560 561 val toBusyTableDeqResp = Wire(Vec(params.numDeq, ValidIO(new IssueQueueDeqRespBundle))) 562 563 toBusyTableDeqResp.zipWithIndex.foreach { case (deqResp, i) => 564 deqResp.valid := deqBeforeDly(i).valid 565 deqResp.bits.resp := RespType.success 566 deqResp.bits.robIdx := DontCare 567 deqResp.bits.sqIdx.foreach(_ := DontCare) 568 deqResp.bits.lqIdx.foreach(_ := DontCare) 569 deqResp.bits.fuType := deqBeforeDly(i).bits.common.fuType 570 deqResp.bits.uopIdx.foreach(_ := DontCare) 571 } 572 573 //fuBusyTable 574 fuBusyTableWrite.zip(fuBusyTableRead).zipWithIndex.foreach { case ((busyTableWrite: Option[FuBusyTableWrite], busyTableRead: Option[FuBusyTableRead]), i) => 575 if(busyTableWrite.nonEmpty) { 576 val btwr = busyTableWrite.get 577 val btrd = busyTableRead.get 578 btwr.io.in.deqResp := toBusyTableDeqResp(i) 579 btwr.io.in.og0Resp := io.og0Resp(i) 580 btwr.io.in.og1Resp := io.og1Resp(i) 581 btrd.io.in.fuBusyTable := btwr.io.out.fuBusyTable 582 btrd.io.in.fuTypeRegVec := fuTypeVec 583 fuBusyTableMask(i) := btrd.io.out.fuBusyTableMask 584 } 585 else { 586 fuBusyTableMask(i) := 0.U(params.numEntries.W) 587 } 588 } 589 590 //wbfuBusyTable write 591 intWbBusyTableWrite.zip(intWbBusyTableOut).zip(intDeqRespSetOut).zipWithIndex.foreach { case (((busyTableWrite: Option[FuBusyTableWrite], busyTable: Option[UInt]), deqResp), i) => 592 if(busyTableWrite.nonEmpty) { 593 val btwr = busyTableWrite.get 594 val bt = busyTable.get 595 val dq = deqResp.get 596 btwr.io.in.deqResp := toBusyTableDeqResp(i) 597 btwr.io.in.deqResp.valid := toBusyTableDeqResp(i).valid && deqBeforeDly(i).bits.common.rfWen.getOrElse(false.B) 598 btwr.io.in.og0Resp := io.og0Resp(i) 599 btwr.io.in.og1Resp := io.og1Resp(i) 600 bt := btwr.io.out.fuBusyTable 601 dq := btwr.io.out.deqRespSet 602 } 603 } 604 605 fpWbBusyTableWrite.zip(fpWbBusyTableOut).zip(fpDeqRespSetOut).zipWithIndex.foreach { case (((busyTableWrite: Option[FuBusyTableWrite], busyTable: Option[UInt]), deqResp), i) => 606 if (busyTableWrite.nonEmpty) { 607 val btwr = busyTableWrite.get 608 val bt = busyTable.get 609 val dq = deqResp.get 610 btwr.io.in.deqResp := toBusyTableDeqResp(i) 611 btwr.io.in.deqResp.valid := toBusyTableDeqResp(i).valid && deqBeforeDly(i).bits.common.fpWen.getOrElse(false.B) 612 btwr.io.in.og0Resp := io.og0Resp(i) 613 btwr.io.in.og1Resp := io.og1Resp(i) 614 bt := btwr.io.out.fuBusyTable 615 dq := btwr.io.out.deqRespSet 616 } 617 } 618 619 vfWbBusyTableWrite.zip(vfWbBusyTableOut).zip(vfDeqRespSetOut).zipWithIndex.foreach { case (((busyTableWrite: Option[FuBusyTableWrite], busyTable: Option[UInt]), deqResp), i) => 620 if (busyTableWrite.nonEmpty) { 621 val btwr = busyTableWrite.get 622 val bt = busyTable.get 623 val dq = deqResp.get 624 btwr.io.in.deqResp := toBusyTableDeqResp(i) 625 btwr.io.in.deqResp.valid := toBusyTableDeqResp(i).valid && deqBeforeDly(i).bits.common.vecWen.getOrElse(false.B) 626 btwr.io.in.og0Resp := io.og0Resp(i) 627 btwr.io.in.og1Resp := io.og1Resp(i) 628 bt := btwr.io.out.fuBusyTable 629 dq := btwr.io.out.deqRespSet 630 } 631 } 632 633 v0WbBusyTableWrite.zip(v0WbBusyTableOut).zip(v0DeqRespSetOut).zipWithIndex.foreach { case (((busyTableWrite: Option[FuBusyTableWrite], busyTable: Option[UInt]), deqResp), i) => 634 if (busyTableWrite.nonEmpty) { 635 val btwr = busyTableWrite.get 636 val bt = busyTable.get 637 val dq = deqResp.get 638 btwr.io.in.deqResp := toBusyTableDeqResp(i) 639 btwr.io.in.deqResp.valid := toBusyTableDeqResp(i).valid && deqBeforeDly(i).bits.common.v0Wen.getOrElse(false.B) 640 btwr.io.in.og0Resp := io.og0Resp(i) 641 btwr.io.in.og1Resp := io.og1Resp(i) 642 bt := btwr.io.out.fuBusyTable 643 dq := btwr.io.out.deqRespSet 644 } 645 } 646 647 vlWbBusyTableWrite.zip(vlWbBusyTableOut).zip(vlDeqRespSetOut).zipWithIndex.foreach { case (((busyTableWrite: Option[FuBusyTableWrite], busyTable: Option[UInt]), deqResp), i) => 648 if (busyTableWrite.nonEmpty) { 649 val btwr = busyTableWrite.get 650 val bt = busyTable.get 651 val dq = deqResp.get 652 btwr.io.in.deqResp := toBusyTableDeqResp(i) 653 btwr.io.in.deqResp.valid := toBusyTableDeqResp(i).valid && deqBeforeDly(i).bits.common.vlWen.getOrElse(false.B) 654 btwr.io.in.og0Resp := io.og0Resp(i) 655 btwr.io.in.og1Resp := io.og1Resp(i) 656 bt := btwr.io.out.fuBusyTable 657 dq := btwr.io.out.deqRespSet 658 } 659 } 660 661 //wbfuBusyTable read 662 intWbBusyTableRead.zip(intWbBusyTableIn).zipWithIndex.foreach { case ((busyTableRead: Option[FuBusyTableRead], busyTable: Option[UInt]), i) => 663 if(busyTableRead.nonEmpty) { 664 val btrd = busyTableRead.get 665 val bt = busyTable.get 666 btrd.io.in.fuBusyTable := bt 667 btrd.io.in.fuTypeRegVec := fuTypeVec 668 intWbBusyTableMask(i) := btrd.io.out.fuBusyTableMask 669 } 670 else { 671 intWbBusyTableMask(i) := 0.U(params.numEntries.W) 672 } 673 } 674 fpWbBusyTableRead.zip(fpWbBusyTableIn).zipWithIndex.foreach { case ((busyTableRead: Option[FuBusyTableRead], busyTable: Option[UInt]), i) => 675 if (busyTableRead.nonEmpty) { 676 val btrd = busyTableRead.get 677 val bt = busyTable.get 678 btrd.io.in.fuBusyTable := bt 679 btrd.io.in.fuTypeRegVec := fuTypeVec 680 fpWbBusyTableMask(i) := btrd.io.out.fuBusyTableMask 681 } 682 else { 683 fpWbBusyTableMask(i) := 0.U(params.numEntries.W) 684 } 685 } 686 vfWbBusyTableRead.zip(vfWbBusyTableIn).zipWithIndex.foreach { case ((busyTableRead: Option[FuBusyTableRead], busyTable: Option[UInt]), i) => 687 if (busyTableRead.nonEmpty) { 688 val btrd = busyTableRead.get 689 val bt = busyTable.get 690 btrd.io.in.fuBusyTable := bt 691 btrd.io.in.fuTypeRegVec := fuTypeVec 692 vfWbBusyTableMask(i) := btrd.io.out.fuBusyTableMask 693 } 694 else { 695 vfWbBusyTableMask(i) := 0.U(params.numEntries.W) 696 } 697 } 698 v0WbBusyTableRead.zip(v0WbBusyTableIn).zipWithIndex.foreach { case ((busyTableRead: Option[FuBusyTableRead], busyTable: Option[UInt]), i) => 699 if (busyTableRead.nonEmpty) { 700 val btrd = busyTableRead.get 701 val bt = busyTable.get 702 btrd.io.in.fuBusyTable := bt 703 btrd.io.in.fuTypeRegVec := fuTypeVec 704 v0WbBusyTableMask(i) := btrd.io.out.fuBusyTableMask 705 } 706 else { 707 v0WbBusyTableMask(i) := 0.U(params.numEntries.W) 708 } 709 } 710 vlWbBusyTableRead.zip(vlWbBusyTableIn).zipWithIndex.foreach { case ((busyTableRead: Option[FuBusyTableRead], busyTable: Option[UInt]), i) => 711 if (busyTableRead.nonEmpty) { 712 val btrd = busyTableRead.get 713 val bt = busyTable.get 714 btrd.io.in.fuBusyTable := bt 715 btrd.io.in.fuTypeRegVec := fuTypeVec 716 vlWbBusyTableMask(i) := btrd.io.out.fuBusyTableMask 717 } 718 else { 719 vlWbBusyTableMask(i) := 0.U(params.numEntries.W) 720 } 721 } 722 723 wakeUpQueues.zipWithIndex.foreach { case (wakeUpQueueOption, i) => 724 wakeUpQueueOption.foreach { 725 wakeUpQueue => 726 val flush = Wire(new WakeupQueueFlush) 727 flush.redirect := io.flush 728 flush.ldCancel := io.ldCancel 729 flush.og0Fail := io.og0Resp(i).valid && RespType.isBlocked(io.og0Resp(i).bits.resp) 730 flush.og1Fail := io.og1Resp(i).valid && RespType.isBlocked(io.og1Resp(i).bits.resp) 731 wakeUpQueue.io.flush := flush 732 wakeUpQueue.io.enq.valid := deqBeforeDly(i).valid 733 wakeUpQueue.io.enq.bits.uop :<= deqBeforeDly(i).bits.common 734 wakeUpQueue.io.enq.bits.uop.pdestCopy.foreach(_ := 0.U) 735 wakeUpQueue.io.enq.bits.lat := getDeqLat(i, deqBeforeDly(i).bits.common.fuType) 736 } 737 } 738 739 deqBeforeDly.zipWithIndex.foreach { case (deq, i) => 740 deq.valid := finalDeqSelValidVec(i) && !cancelDeqVec(i) 741 deq.bits.addrOH := finalDeqSelOHVec(i) 742 deq.bits.common.isFirstIssue := deqFirstIssueVec(i) 743 deq.bits.common.iqIdx := OHToUInt(finalDeqSelOHVec(i)) 744 deq.bits.common.fuType := IQFuType.readFuType(deqEntryVec(i).bits.status.fuType, params.getFuCfgs.map(_.fuType)).asUInt 745 deq.bits.common.fuOpType := deqEntryVec(i).bits.payload.fuOpType 746 deq.bits.common.rfWen.foreach(_ := deqEntryVec(i).bits.payload.rfWen) 747 deq.bits.common.fpWen.foreach(_ := deqEntryVec(i).bits.payload.fpWen) 748 deq.bits.common.vecWen.foreach(_ := deqEntryVec(i).bits.payload.vecWen) 749 deq.bits.common.v0Wen.foreach(_ := deqEntryVec(i).bits.payload.v0Wen) 750 deq.bits.common.vlWen.foreach(_ := deqEntryVec(i).bits.payload.vlWen) 751 deq.bits.common.flushPipe.foreach(_ := deqEntryVec(i).bits.payload.flushPipe) 752 deq.bits.common.pdest := deqEntryVec(i).bits.payload.pdest 753 deq.bits.common.robIdx := deqEntryVec(i).bits.status.robIdx 754 755 require(deq.bits.common.dataSources.size <= finalDataSources(i).size) 756 deq.bits.common.dataSources.zip(finalDataSources(i)).foreach { case (sink, source) => sink := source} 757 deq.bits.common.l1ExuOH.foreach(_.zip(finalWakeUpL1ExuOH.get(i)).foreach { case (sink, source) => sink := source}) 758 deq.bits.common.srcTimer.foreach(_ := DontCare) 759 deq.bits.common.loadDependency.foreach(_.zip(finalLoadDependency(i)).foreach { case (sink, source) => sink := source}) 760 deq.bits.common.src := DontCare 761 deq.bits.common.preDecode.foreach(_ := deqEntryVec(i).bits.payload.preDecodeInfo) 762 763 deq.bits.rf.zip(deqEntryVec(i).bits.status.srcStatus.map(_.psrc)).zip(deqEntryVec(i).bits.status.srcStatus.map(_.srcType)).foreach { case ((rf, psrc), srcType) => 764 // psrc in status array can be pregIdx of IntRegFile or VfRegFile 765 rf.foreach(_.addr := psrc) 766 rf.foreach(_.srcType := srcType) 767 } 768 deq.bits.srcType.zip(deqEntryVec(i).bits.status.srcStatus.map(_.srcType)).foreach { case (sink, source) => 769 sink := source 770 } 771 deq.bits.immType := deqEntryVec(i).bits.payload.selImm 772 deq.bits.common.imm := deqEntryVec(i).bits.imm.getOrElse(0.U) 773 deq.bits.rcIdx.foreach(_ := deqEntryVec(i).bits.status.srcStatus.map(_.regCacheIdx.get)) 774 775 deq.bits.common.perfDebugInfo := deqEntryVec(i).bits.payload.debugInfo 776 deq.bits.common.perfDebugInfo.selectTime := GTimer() 777 deq.bits.common.perfDebugInfo.issueTime := GTimer() + 1.U 778 } 779 780 val deqDelay = Reg(params.genIssueValidBundle) 781 deqDelay.zip(deqBeforeDly).foreach { case (deqDly, deq) => 782 deqDly.valid := deq.valid 783 when(validVec.asUInt.orR) { 784 deqDly.bits := deq.bits 785 } 786 // deqBeforeDly.ready is always true 787 deq.ready := true.B 788 } 789 io.deqDelay.zip(deqDelay).foreach { case (sink, source) => 790 sink.valid := source.valid 791 sink.bits := source.bits 792 } 793 if(backendParams.debugEn) { 794 dontTouch(deqDelay) 795 dontTouch(io.deqDelay) 796 dontTouch(deqBeforeDly) 797 } 798 io.wakeupToIQ.zipWithIndex.foreach { case (wakeup, i) => 799 if (wakeUpQueues(i).nonEmpty) { 800 wakeup.valid := wakeUpQueues(i).get.io.deq.valid 801 wakeup.bits.fromExuInput(wakeUpQueues(i).get.io.deq.bits) 802 wakeup.bits.loadDependency := wakeUpQueues(i).get.io.deq.bits.loadDependency.getOrElse(0.U.asTypeOf(wakeup.bits.loadDependency)) 803 wakeup.bits.is0Lat := getDeqLat(i, wakeUpQueues(i).get.io.deq.bits.fuType) === 0.U 804 wakeup.bits.rcDest.foreach(_ := io.replaceRCIdx.get(i)) 805 } else { 806 wakeup.valid := false.B 807 wakeup.bits := 0.U.asTypeOf(wakeup.bits) 808 } 809 if (wakeUpQueues(i).nonEmpty) { 810 wakeup.bits.rfWen := (if (wakeUpQueues(i).get.io.deq.bits.rfWen .nonEmpty) wakeUpQueues(i).get.io.deq.valid && wakeUpQueues(i).get.io.deq.bits.rfWen .get else false.B) 811 wakeup.bits.fpWen := (if (wakeUpQueues(i).get.io.deq.bits.fpWen .nonEmpty) wakeUpQueues(i).get.io.deq.valid && wakeUpQueues(i).get.io.deq.bits.fpWen .get else false.B) 812 wakeup.bits.vecWen := (if (wakeUpQueues(i).get.io.deq.bits.vecWen.nonEmpty) wakeUpQueues(i).get.io.deq.valid && wakeUpQueues(i).get.io.deq.bits.vecWen.get else false.B) 813 wakeup.bits.v0Wen := (if (wakeUpQueues(i).get.io.deq.bits.v0Wen .nonEmpty) wakeUpQueues(i).get.io.deq.valid && wakeUpQueues(i).get.io.deq.bits.v0Wen.get else false.B) 814 wakeup.bits.vlWen := (if (wakeUpQueues(i).get.io.deq.bits.vlWen .nonEmpty) wakeUpQueues(i).get.io.deq.valid && wakeUpQueues(i).get.io.deq.bits.vlWen.get else false.B) 815 } 816 817 if(wakeUpQueues(i).nonEmpty && wakeup.bits.pdestCopy.nonEmpty){ 818 wakeup.bits.pdestCopy.get := wakeUpQueues(i).get.io.deq.bits.pdestCopy.get 819 } 820 if (wakeUpQueues(i).nonEmpty && wakeup.bits.rfWenCopy.nonEmpty) { 821 wakeup.bits.rfWenCopy.get := wakeUpQueues(i).get.io.deq.bits.rfWenCopy.get 822 } 823 if (wakeUpQueues(i).nonEmpty && wakeup.bits.fpWenCopy.nonEmpty) { 824 wakeup.bits.fpWenCopy.get := wakeUpQueues(i).get.io.deq.bits.fpWenCopy.get 825 } 826 if (wakeUpQueues(i).nonEmpty && wakeup.bits.vecWenCopy.nonEmpty) { 827 wakeup.bits.vecWenCopy.get := wakeUpQueues(i).get.io.deq.bits.vecWenCopy.get 828 } 829 if (wakeUpQueues(i).nonEmpty && wakeup.bits.v0WenCopy.nonEmpty) { 830 wakeup.bits.v0WenCopy.get := wakeUpQueues(i).get.io.deq.bits.v0WenCopy.get 831 } 832 if (wakeUpQueues(i).nonEmpty && wakeup.bits.vlWenCopy.nonEmpty) { 833 wakeup.bits.vlWenCopy.get := wakeUpQueues(i).get.io.deq.bits.vlWenCopy.get 834 } 835 if (wakeUpQueues(i).nonEmpty && wakeup.bits.loadDependencyCopy.nonEmpty) { 836 wakeup.bits.loadDependencyCopy.get := wakeUpQueues(i).get.io.deq.bits.loadDependencyCopy.get 837 } 838 } 839 840 // Todo: better counter implementation 841 private val enqHasValid = validVec.take(params.numEnq).reduce(_ | _) 842 private val enqHasIssued = validVec.zip(issuedVec).take(params.numEnq).map(x => x._1 & x._2).reduce(_ | _) 843 private val enqEntryValidCnt = PopCount(validVec.take(params.numEnq)) 844 private val othersValidCnt = PopCount(validVec.drop(params.numEnq)) 845 private val enqEntryValidCntDeq0 = PopCount( 846 validVec.take(params.numEnq).zip(deqCanAcceptVec(0).take(params.numEnq)).map { case (a, b) => a && b } 847 ) 848 private val othersValidCntDeq0 = PopCount( 849 validVec.drop(params.numEnq).zip(deqCanAcceptVec(0).drop(params.numEnq)).map { case (a, b) => a && b } 850 ) 851 private val enqEntryValidCntDeq1 = PopCount( 852 validVec.take(params.numEnq).zip(deqCanAcceptVec.last.take(params.numEnq)).map { case (a, b) => a && b } 853 ) 854 private val othersValidCntDeq1 = PopCount( 855 validVec.drop(params.numEnq).zip(deqCanAcceptVec.last.drop(params.numEnq)).map { case (a, b) => a && b } 856 ) 857 protected val deqCanAcceptVecEnq: Seq[IndexedSeq[Bool]] = deqFuCfgs.map { fuCfgs: Seq[FuConfig] => 858 io.enq.map(_.bits.fuType).map(fuType => 859 FuType.FuTypeOrR(fuType, fuCfgs.map(_.fuType))) 860 } 861 protected val enqValidCntDeq0 = PopCount(io.enq.map(_.fire).zip(deqCanAcceptVecEnq(0)).map { case (a, b) => a && b }) 862 protected val enqValidCntDeq1 = PopCount(io.enq.map(_.fire).zip(deqCanAcceptVecEnq.last).map { case (a, b) => a && b }) 863 io.validCntDeqVec.head := RegNext(enqEntryValidCntDeq0 +& othersValidCntDeq0 - io.deqDelay.head.fire) // validCntDeqVec(0) 864 io.validCntDeqVec.last := RegNext(enqEntryValidCntDeq1 +& othersValidCntDeq1 - io.deqDelay.last.fire) // validCntDeqVec(1) 865 io.status.leftVec(0) := validVec.drop(params.numEnq).reduce(_ & _) 866 for (i <- 0 until params.numEnq) { 867 io.status.leftVec(i + 1) := othersValidCnt === (params.numEntries - params.numEnq - (i + 1)).U 868 } 869 private val othersLeftOneCaseVec = Wire(Vec(params.numEntries - params.numEnq, UInt((params.numEntries - params.numEnq).W))) 870 othersLeftOneCaseVec.zipWithIndex.foreach { case (leftone, i) => 871 leftone := ~(1.U((params.numEntries - params.numEnq).W) << i) 872 } 873 private val othersLeftOne = othersLeftOneCaseVec.map(_ === VecInit(validVec.drop(params.numEnq)).asUInt).reduce(_ | _) 874 private val othersCanotIn = Wire(Bool()) 875 othersCanotIn := othersLeftOne || validVec.drop(params.numEnq).reduce(_ & _) 876 // if has simp Entry, othersCanotIn will be simpCanotIn 877 if (params.numSimp > 0) { 878 val simpLeftOneCaseVec = Wire(Vec(params.numSimp, UInt((params.numSimp).W))) 879 simpLeftOneCaseVec.zipWithIndex.foreach { case (leftone, i) => 880 leftone := ~(1.U((params.numSimp).W) << i) 881 } 882 val simpLeftOne = simpLeftOneCaseVec.map(_ === VecInit(validVec.drop(params.numEnq).take(params.numSimp)).asUInt).reduce(_ | _) 883 val simpCanotIn = simpLeftOne || validVec.drop(params.numEnq).take(params.numSimp).reduce(_ & _) 884 othersCanotIn := simpCanotIn 885 } 886 io.enq.foreach(_.ready := (!othersCanotIn || !enqHasValid) && !enqHasIssued) 887 io.status.empty := !Cat(validVec).orR 888 io.status.full := othersCanotIn 889 io.status.validCnt := PopCount(validVec) 890 891 protected def getDeqLat(deqPortIdx: Int, fuType: UInt) : UInt = { 892 Mux1H(wakeupFuLatencyMaps(deqPortIdx) map { case (k, v) => (fuType(k.id), v.U) }) 893 } 894 895 // issue perf counter 896 // enq count 897 XSPerfAccumulate("enq_valid_cnt", PopCount(io.enq.map(_.fire))) 898 XSPerfAccumulate("enq_fire_cnt", PopCount(io.enq.map(_.fire))) 899 XSPerfAccumulate("enq_alu_fire_cnt", PopCount(io.enq.map { case enq => enq.fire && FuType.isAlu(enq.bits.fuType) })) 900 XSPerfAccumulate("enq_brh_fire_cnt", PopCount(io.enq.map { case enq => enq.fire && FuType.isBrh(enq.bits.fuType) })) 901 XSPerfAccumulate("deqDelay0_fire_cnt", PopCount(io.deqDelay.head.fire)) 902 XSPerfAccumulate("deqDelay1_fire_cnt", PopCount(io.deqDelay.last.fire)) 903 // valid count 904 XSPerfHistogram("enq_entry_valid_cnt", enqEntryValidCnt, true.B, 0, params.numEnq + 1) 905 XSPerfHistogram("other_entry_valid_cnt", othersValidCnt, true.B, 0, params.numEntries - params.numEnq + 1) 906 XSPerfHistogram("valid_cnt", PopCount(validVec), true.B, 0, params.numEntries + 1) 907 // only split when more than 1 func type 908 if (params.getFuCfgs.size > 0) { 909 for (t <- FuType.functionNameMap.keys) { 910 val fuName = FuType.functionNameMap(t) 911 if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _)) { 912 XSPerfHistogram(s"valid_cnt_hist_futype_${fuName}", PopCount(validVec.zip(fuTypeVec).map { case (v, fu) => v && fu === t.U }), true.B, 0, params.numEntries, 1) 913 } 914 } 915 } 916 // ready instr count 917 private val readyEntriesCnt = PopCount(validVec.zip(canIssueVec).map(x => x._1 && x._2)) 918 XSPerfHistogram("ready_cnt", readyEntriesCnt, true.B, 0, params.numEntries + 1) 919 // only split when more than 1 func type 920 if (params.getFuCfgs.size > 0) { 921 for (t <- FuType.functionNameMap.keys) { 922 val fuName = FuType.functionNameMap(t) 923 if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _)) { 924 XSPerfHistogram(s"ready_cnt_hist_futype_${fuName}", PopCount(validVec.zip(canIssueVec).zip(fuTypeVec).map { case ((v, c), fu) => v && c && fu === t.U }), true.B, 0, params.numEntries, 1) 925 } 926 } 927 } 928 929 // deq instr count 930 XSPerfAccumulate("issue_instr_pre_count", PopCount(deqBeforeDly.map(_.valid))) 931 XSPerfHistogram("issue_instr_pre_count_hist", PopCount(deqBeforeDly.map(_.valid)), true.B, 0, params.numDeq + 1, 1) 932 XSPerfAccumulate("issue_instr_count", PopCount(io.deqDelay.map(_.valid))) 933 XSPerfHistogram("issue_instr_count_hist", PopCount(io.deqDelay.map(_.valid)), true.B, 0, params.numDeq + 1, 1) 934 935 // deq instr data source count 936 XSPerfAccumulate("issue_datasource_reg", deqBeforeDly.map{ deq => 937 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) }) 938 }.reduce(_ +& _)) 939 XSPerfAccumulate("issue_datasource_bypass", deqBeforeDly.map{ deq => 940 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) }) 941 }.reduce(_ +& _)) 942 XSPerfAccumulate("issue_datasource_forward", deqBeforeDly.map{ deq => 943 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) }) 944 }.reduce(_ +& _)) 945 XSPerfAccumulate("issue_datasource_noreg", deqBeforeDly.map{ deq => 946 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) }) 947 }.reduce(_ +& _)) 948 949 XSPerfHistogram("issue_datasource_reg_hist", deqBeforeDly.map{ deq => 950 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) }) 951 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 952 XSPerfHistogram("issue_datasource_bypass_hist", deqBeforeDly.map{ deq => 953 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) }) 954 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 955 XSPerfHistogram("issue_datasource_forward_hist", deqBeforeDly.map{ deq => 956 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) }) 957 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 958 XSPerfHistogram("issue_datasource_noreg_hist", deqBeforeDly.map{ deq => 959 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) }) 960 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 961 962 // deq instr data source count for each futype 963 for (t <- FuType.functionNameMap.keys) { 964 val fuName = FuType.functionNameMap(t) 965 if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _)) { 966 XSPerfAccumulate(s"issue_datasource_reg_futype_${fuName}", deqBeforeDly.map{ deq => 967 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 968 }.reduce(_ +& _)) 969 XSPerfAccumulate(s"issue_datasource_bypass_futype_${fuName}", deqBeforeDly.map{ deq => 970 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 971 }.reduce(_ +& _)) 972 XSPerfAccumulate(s"issue_datasource_forward_futype_${fuName}", deqBeforeDly.map{ deq => 973 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 974 }.reduce(_ +& _)) 975 XSPerfAccumulate(s"issue_datasource_noreg_futype_${fuName}", deqBeforeDly.map{ deq => 976 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 977 }.reduce(_ +& _)) 978 979 XSPerfHistogram(s"issue_datasource_reg_hist_futype_${fuName}", deqBeforeDly.map{ deq => 980 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 981 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 982 XSPerfHistogram(s"issue_datasource_bypass_hist_futype_${fuName}", deqBeforeDly.map{ deq => 983 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 984 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 985 XSPerfHistogram(s"issue_datasource_forward_hist_futype_${fuName}", deqBeforeDly.map{ deq => 986 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 987 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 988 XSPerfHistogram(s"issue_datasource_noreg_hist_futype_${fuName}", deqBeforeDly.map{ deq => 989 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 990 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 991 } 992 } 993} 994 995class IssueQueueLoadBundle(implicit p: Parameters) extends XSBundle { 996 val fastMatch = UInt(backendParams.LduCnt.W) 997 val fastImm = UInt(12.W) 998} 999 1000class IssueQueueIntIO()(implicit p: Parameters, params: IssueBlockParams) extends IssueQueueIO 1001 1002class IssueQueueIntImp(override val wrapper: IssueQueue)(implicit p: Parameters, iqParams: IssueBlockParams) 1003 extends IssueQueueImp(wrapper) 1004{ 1005 io.suggestName("none") 1006 override lazy val io = IO(new IssueQueueIntIO).suggestName("io") 1007 1008 deqBeforeDly.zipWithIndex.foreach{ case (deq, i) => { 1009 deq.bits.common.pc.foreach(_ := DontCare) 1010 deq.bits.common.preDecode.foreach(_ := deqEntryVec(i).bits.payload.preDecodeInfo) 1011 deq.bits.common.ftqIdx.foreach(_ := deqEntryVec(i).bits.payload.ftqPtr) 1012 deq.bits.common.ftqOffset.foreach(_ := deqEntryVec(i).bits.payload.ftqOffset) 1013 deq.bits.common.predictInfo.foreach(x => { 1014 x.target := DontCare 1015 x.taken := deqEntryVec(i).bits.payload.pred_taken 1016 }) 1017 // for std 1018 deq.bits.common.sqIdx.foreach(_ := deqEntryVec(i).bits.payload.sqIdx) 1019 // for i2f 1020 deq.bits.common.fpu.foreach(_ := deqEntryVec(i).bits.payload.fpu) 1021 }} 1022} 1023 1024class IssueQueueVfImp(override val wrapper: IssueQueue)(implicit p: Parameters, iqParams: IssueBlockParams) 1025 extends IssueQueueImp(wrapper) 1026{ 1027 deqBeforeDly.zipWithIndex.foreach{ case (deq, i) => { 1028 deq.bits.common.fpu.foreach(_ := deqEntryVec(i).bits.payload.fpu) 1029 deq.bits.common.vpu.foreach(_ := deqEntryVec(i).bits.payload.vpu) 1030 deq.bits.common.vpu.foreach(_.vuopIdx := deqEntryVec(i).bits.payload.uopIdx) 1031 deq.bits.common.vpu.foreach(_.lastUop := deqEntryVec(i).bits.payload.lastUop) 1032 }} 1033} 1034 1035class IssueQueueFpImp(override val wrapper: IssueQueue)(implicit p: Parameters, iqParams: IssueBlockParams) 1036 extends IssueQueueImp(wrapper) 1037{ 1038 deqBeforeDly.zipWithIndex.foreach{ case (deq, i) => { 1039 deq.bits.common.fpu.foreach(_ := deqEntryVec(i).bits.payload.fpu) 1040 deq.bits.common.vpu.foreach(_ := deqEntryVec(i).bits.payload.vpu) 1041 deq.bits.common.vpu.foreach(_.vuopIdx := deqEntryVec(i).bits.payload.uopIdx) 1042 deq.bits.common.vpu.foreach(_.lastUop := deqEntryVec(i).bits.payload.lastUop) 1043 }} 1044} 1045 1046class IssueQueueMemBundle(implicit p: Parameters, params: IssueBlockParams) extends Bundle { 1047 val feedbackIO = Flipped(Vec(params.numDeq, new MemRSFeedbackIO(params.isVecMemIQ))) 1048 1049 // TODO: is still needed? 1050 val checkWait = new Bundle { 1051 val stIssuePtr = Input(new SqPtr) 1052 val memWaitUpdateReq = Flipped(new MemWaitUpdateReq) 1053 } 1054 val loadFastMatch = Output(Vec(params.LdExuCnt, new IssueQueueLoadBundle)) 1055 1056 // load wakeup 1057 val loadWakeUp = Input(Vec(params.LdExuCnt, ValidIO(new DynInst()))) 1058 1059 // vector 1060 val sqDeqPtr = Option.when(params.isVecMemIQ)(Input(new SqPtr)) 1061 val lqDeqPtr = Option.when(params.isVecMemIQ)(Input(new LqPtr)) 1062} 1063 1064class IssueQueueMemIO(implicit p: Parameters, params: IssueBlockParams) extends IssueQueueIO { 1065 val memIO = Some(new IssueQueueMemBundle) 1066} 1067 1068class IssueQueueMemAddrImp(override val wrapper: IssueQueue)(implicit p: Parameters, params: IssueBlockParams) 1069 extends IssueQueueImp(wrapper) with HasCircularQueuePtrHelper { 1070 1071 require(params.StdCnt == 0 && (params.LduCnt + params.StaCnt + params.HyuCnt) > 0, "IssueQueueMemAddrImp can only be instance of MemAddr IQ, " + 1072 s"StdCnt: ${params.StdCnt}, LduCnt: ${params.LduCnt}, StaCnt: ${params.StaCnt}, HyuCnt: ${params.HyuCnt}") 1073 println(s"[IssueQueueMemAddrImp] StdCnt: ${params.StdCnt}, LduCnt: ${params.LduCnt}, StaCnt: ${params.StaCnt}, HyuCnt: ${params.HyuCnt}") 1074 1075 io.suggestName("none") 1076 override lazy val io = IO(new IssueQueueMemIO).suggestName("io") 1077 private val memIO = io.memIO.get 1078 1079 memIO.loadFastMatch := 0.U.asTypeOf(memIO.loadFastMatch) // TODO: is still needed? 1080 1081 entries.io.fromMem.get.slowResp.zipWithIndex.foreach { case (slowResp, i) => 1082 slowResp.valid := memIO.feedbackIO(i).feedbackSlow.valid 1083 slowResp.bits.robIdx := memIO.feedbackIO(i).feedbackSlow.bits.robIdx 1084 slowResp.bits.sqIdx.foreach( _ := memIO.feedbackIO(i).feedbackSlow.bits.sqIdx) 1085 slowResp.bits.lqIdx.foreach( _ := memIO.feedbackIO(i).feedbackSlow.bits.lqIdx) 1086 slowResp.bits.resp := Mux(memIO.feedbackIO(i).feedbackSlow.bits.hit, RespType.success, RespType.block) 1087 slowResp.bits.fuType := DontCare 1088 } 1089 1090 entries.io.fromMem.get.fastResp.zipWithIndex.foreach { case (fastResp, i) => 1091 fastResp.valid := memIO.feedbackIO(i).feedbackFast.valid 1092 fastResp.bits.robIdx := memIO.feedbackIO(i).feedbackFast.bits.robIdx 1093 fastResp.bits.sqIdx.foreach( _ := memIO.feedbackIO(i).feedbackFast.bits.sqIdx) 1094 fastResp.bits.lqIdx.foreach( _ := memIO.feedbackIO(i).feedbackFast.bits.lqIdx) 1095 fastResp.bits.resp := Mux(memIO.feedbackIO(i).feedbackFast.bits.hit, RespType.success, RespType.block) 1096 fastResp.bits.fuType := DontCare 1097 } 1098 1099 // load wakeup 1100 val loadWakeUpIter = memIO.loadWakeUp.iterator 1101 io.wakeupToIQ.zip(params.exuBlockParams).zipWithIndex.foreach { case ((wakeup, param), i) => 1102 if (param.hasLoadExu) { 1103 require(wakeUpQueues(i).isEmpty) 1104 val uop = loadWakeUpIter.next() 1105 1106 wakeup.valid := GatedValidRegNext(uop.fire) 1107 wakeup.bits.rfWen := (if (params.writeIntRf) GatedValidRegNext(uop.bits.rfWen && uop.fire) else false.B) 1108 wakeup.bits.fpWen := (if (params.writeFpRf) GatedValidRegNext(uop.bits.fpWen && uop.fire) else false.B) 1109 wakeup.bits.vecWen := (if (params.writeVecRf) GatedValidRegNext(uop.bits.vecWen && uop.fire) else false.B) 1110 wakeup.bits.v0Wen := (if (params.writeV0Rf) GatedValidRegNext(uop.bits.v0Wen && uop.fire) else false.B) 1111 wakeup.bits.vlWen := (if (params.writeVlRf) GatedValidRegNext(uop.bits.vlWen && uop.fire) else false.B) 1112 wakeup.bits.pdest := RegEnable(uop.bits.pdest, uop.fire) 1113 wakeup.bits.rcDest.foreach(_ := io.replaceRCIdx.get(i)) 1114 wakeup.bits.loadDependency.foreach(_ := 0.U) // this is correct for load only 1115 1116 wakeup.bits.rfWenCopy .foreach(_.foreach(_ := (if (params.writeIntRf) GatedValidRegNext(uop.bits.rfWen && uop.fire) else false.B))) 1117 wakeup.bits.fpWenCopy .foreach(_.foreach(_ := (if (params.writeFpRf) GatedValidRegNext(uop.bits.fpWen && uop.fire) else false.B))) 1118 wakeup.bits.vecWenCopy.foreach(_.foreach(_ := (if (params.writeVecRf) GatedValidRegNext(uop.bits.vecWen && uop.fire) else false.B))) 1119 wakeup.bits.v0WenCopy .foreach(_.foreach(_ := (if (params.writeV0Rf) GatedValidRegNext(uop.bits.v0Wen && uop.fire) else false.B))) 1120 wakeup.bits.vlWenCopy .foreach(_.foreach(_ := (if (params.writeVlRf) GatedValidRegNext(uop.bits.vlWen && uop.fire) else false.B))) 1121 wakeup.bits.pdestCopy .foreach(_.foreach(_ := RegEnable(uop.bits.pdest, uop.fire))) 1122 wakeup.bits.loadDependencyCopy.foreach(x => x := 0.U.asTypeOf(x)) // this is correct for load only 1123 1124 wakeup.bits.is0Lat := 0.U 1125 } 1126 } 1127 require(!loadWakeUpIter.hasNext) 1128 1129 deqBeforeDly.zipWithIndex.foreach { case (deq, i) => 1130 deq.bits.common.loadWaitBit.foreach(_ := deqEntryVec(i).bits.payload.loadWaitBit) 1131 deq.bits.common.waitForRobIdx.foreach(_ := deqEntryVec(i).bits.payload.waitForRobIdx) 1132 deq.bits.common.storeSetHit.foreach(_ := deqEntryVec(i).bits.payload.storeSetHit) 1133 deq.bits.common.loadWaitStrict.foreach(_ := deqEntryVec(i).bits.payload.loadWaitStrict) 1134 deq.bits.common.ssid.foreach(_ := deqEntryVec(i).bits.payload.ssid) 1135 deq.bits.common.sqIdx.get := deqEntryVec(i).bits.payload.sqIdx 1136 deq.bits.common.lqIdx.get := deqEntryVec(i).bits.payload.lqIdx 1137 deq.bits.common.ftqIdx.foreach(_ := deqEntryVec(i).bits.payload.ftqPtr) 1138 deq.bits.common.ftqOffset.foreach(_ := deqEntryVec(i).bits.payload.ftqOffset) 1139 } 1140} 1141 1142class IssueQueueVecMemImp(override val wrapper: IssueQueue)(implicit p: Parameters, params: IssueBlockParams) 1143 extends IssueQueueImp(wrapper) with HasCircularQueuePtrHelper { 1144 1145 require((params.VlduCnt + params.VstuCnt) > 0, "IssueQueueVecMemImp can only be instance of VecMem IQ") 1146 println(s"[IssueQueueVecMemImp] VlduCnt: ${params.VlduCnt}, VstuCnt: ${params.VstuCnt}") 1147 1148 io.suggestName("none") 1149 override lazy val io = IO(new IssueQueueMemIO).suggestName("io") 1150 private val memIO = io.memIO.get 1151 1152 require(params.numExu == 1, "VecMem IssueQueue has not supported more than 1 deq ports") 1153 1154 for (i <- entries.io.enq.indices) { 1155 entries.io.enq(i).bits.status match { case enqData => 1156 enqData.vecMem.get.sqIdx := s0_enqBits(i).sqIdx 1157 enqData.vecMem.get.lqIdx := s0_enqBits(i).lqIdx 1158 // MemAddrIQ also handle vector insts 1159 enqData.vecMem.get.numLsElem := s0_enqBits(i).numLsElem 1160 1161 val isFirstLoad = s0_enqBits(i).lqIdx <= memIO.lqDeqPtr.get 1162 val isVleff = s0_enqBits(i).vpu.isVleff 1163 enqData.blocked := !isFirstLoad && isVleff 1164 } 1165 } 1166 1167 entries.io.fromMem.get.slowResp.zipWithIndex.foreach { case (slowResp, i) => 1168 slowResp.valid := memIO.feedbackIO(i).feedbackSlow.valid 1169 slowResp.bits.robIdx := memIO.feedbackIO(i).feedbackSlow.bits.robIdx 1170 slowResp.bits.sqIdx.get := memIO.feedbackIO(i).feedbackSlow.bits.sqIdx 1171 slowResp.bits.lqIdx.get := memIO.feedbackIO(i).feedbackSlow.bits.lqIdx 1172 slowResp.bits.resp := Mux(memIO.feedbackIO(i).feedbackSlow.bits.hit, RespType.success, RespType.block) 1173 slowResp.bits.fuType := DontCare 1174 slowResp.bits.uopIdx.get := DontCare 1175 } 1176 1177 entries.io.fromMem.get.fastResp.zipWithIndex.foreach { case (fastResp, i) => 1178 fastResp.valid := memIO.feedbackIO(i).feedbackFast.valid 1179 fastResp.bits.robIdx := memIO.feedbackIO(i).feedbackFast.bits.robIdx 1180 fastResp.bits.sqIdx.get := memIO.feedbackIO(i).feedbackFast.bits.sqIdx 1181 fastResp.bits.lqIdx.get := memIO.feedbackIO(i).feedbackFast.bits.lqIdx 1182 fastResp.bits.resp := Mux(memIO.feedbackIO(i).feedbackFast.bits.hit, RespType.success, RespType.block) 1183 fastResp.bits.fuType := DontCare 1184 fastResp.bits.uopIdx.get := DontCare 1185 } 1186 1187 entries.io.vecMemIn.get.sqDeqPtr := memIO.sqDeqPtr.get 1188 entries.io.vecMemIn.get.lqDeqPtr := memIO.lqDeqPtr.get 1189 1190 deqBeforeDly.zipWithIndex.foreach { case (deq, i) => 1191 deq.bits.common.sqIdx.foreach(_ := deqEntryVec(i).bits.status.vecMem.get.sqIdx) 1192 deq.bits.common.lqIdx.foreach(_ := deqEntryVec(i).bits.status.vecMem.get.lqIdx) 1193 deq.bits.common.numLsElem.foreach(_ := deqEntryVec(i).bits.status.vecMem.get.numLsElem) 1194 if (params.isVecLduIQ) { 1195 deq.bits.common.ftqIdx.get := deqEntryVec(i).bits.payload.ftqPtr 1196 deq.bits.common.ftqOffset.get := deqEntryVec(i).bits.payload.ftqOffset 1197 } 1198 deq.bits.common.fpu.foreach(_ := deqEntryVec(i).bits.payload.fpu) 1199 deq.bits.common.vpu.foreach(_ := deqEntryVec(i).bits.payload.vpu) 1200 deq.bits.common.vpu.foreach(_.vuopIdx := deqEntryVec(i).bits.payload.uopIdx) 1201 deq.bits.common.vpu.foreach(_.lastUop := deqEntryVec(i).bits.payload.lastUop) 1202 } 1203 1204 io.vecLoadIssueResp.foreach(dontTouch(_)) 1205} 1206