xref: /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala (revision 60912d849144743291f10504e7db8e814730135c) 
1package xiangshan.backend.issue
2
3import org.chipsalliance.cde.config.Parameters
4import chisel3._
5import chisel3.util._
6import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
7import utility.{GTimer, HasCircularQueuePtrHelper, SelectOne}
8import utils._
9import xiangshan._
10import xiangshan.backend.Bundles._
11import xiangshan.backend.decode.{ImmUnion, Imm_LUI_LOAD}
12import xiangshan.backend.datapath.DataConfig._
13import xiangshan.backend.datapath.DataSource
14import xiangshan.backend.fu.{FuConfig, FuType}
15import xiangshan.mem.{MemWaitUpdateReq, SqPtr, LqPtr}
16import xiangshan.backend.rob.RobPtr
17import xiangshan.backend.datapath.NewPipelineConnect
18
19class IssueQueue(params: IssueBlockParams)(implicit p: Parameters) extends LazyModule with HasXSParameter {
20  override def shouldBeInlined: Boolean = false
21
22  implicit val iqParams = params
23  lazy val module: IssueQueueImp = iqParams.schdType match {
24    case IntScheduler() => new IssueQueueIntImp(this)
25    case VfScheduler() => new IssueQueueVfImp(this)
26    case MemScheduler() =>
27      if (iqParams.StdCnt == 0 && !iqParams.isVecMemIQ) new IssueQueueMemAddrImp(this)
28      else if (iqParams.isVecMemIQ) new IssueQueueVecMemImp(this)
29      else new IssueQueueIntImp(this)
30    case _ => null
31  }
32}
33
34class IssueQueueStatusBundle(numEnq: Int, numEntries: Int) extends Bundle {
35  val empty = Output(Bool())
36  val full = Output(Bool())
37  val validCnt = Output(UInt(log2Ceil(numEntries).W))
38  val leftVec = Output(Vec(numEnq + 1, Bool()))
39}
40
41class IssueQueueDeqRespBundle(implicit p:Parameters, params: IssueBlockParams) extends EntryDeqRespBundle
42
43class IssueQueueIO()(implicit p: Parameters, params: IssueBlockParams) extends XSBundle {
44  // Inputs
45  val flush = Flipped(ValidIO(new Redirect))
46  val enq = Vec(params.numEnq, Flipped(DecoupledIO(new DynInst)))
47
48  val og0Resp = Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle)))
49  val og1Resp = Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle)))
50  val finalIssueResp = OptionWrapper(params.LdExuCnt > 0, Vec(params.LdExuCnt, Flipped(ValidIO(new IssueQueueDeqRespBundle))))
51  val memAddrIssueResp = OptionWrapper(params.LdExuCnt > 0, Vec(params.LdExuCnt, Flipped(ValidIO(new IssueQueueDeqRespBundle))))
52  val wbBusyTableRead = Input(params.genWbFuBusyTableReadBundle())
53  val wbBusyTableWrite = Output(params.genWbFuBusyTableWriteBundle())
54  val wakeupFromWB: MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = Flipped(params.genWBWakeUpSinkValidBundle)
55  val wakeupFromIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(params.genIQWakeUpSinkValidBundle)
56  val og0Cancel = Input(ExuOH(backendParams.numExu))
57  val og1Cancel = Input(ExuOH(backendParams.numExu))
58  val ldCancel = Vec(backendParams.LduCnt + backendParams.HyuCnt, Flipped(new LoadCancelIO))
59  val finalBlock = Vec(params.numExu, Input(Bool()))
60
61  // Outputs
62  val wakeupToIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = params.genIQWakeUpSourceValidBundle
63  val status = Output(new IssueQueueStatusBundle(params.numEnq, params.numEntries))
64  // val statusNext = Output(new IssueQueueStatusBundle(params.numEnq))
65
66  val deqDelay: MixedVec[DecoupledIO[IssueQueueIssueBundle]] = params.genIssueDecoupledBundle// = deq.cloneType
67  def allWakeUp = wakeupFromWB ++ wakeupFromIQ
68}
69
70class IssueQueueImp(override val wrapper: IssueQueue)(implicit p: Parameters, val params: IssueBlockParams)
71  extends LazyModuleImp(wrapper)
72  with HasXSParameter {
73
74  println(s"[IssueQueueImp] ${params.getIQName} wakeupFromWB(${io.wakeupFromWB.size}), " +
75    s"wakeup exu in(${params.wakeUpInExuSources.size}): ${params.wakeUpInExuSources.map(_.name).mkString("{",",","}")}, " +
76    s"wakeup exu out(${params.wakeUpOutExuSources.size}): ${params.wakeUpOutExuSources.map(_.name).mkString("{",",","}")}, " +
77    s"numEntries: ${params.numEntries}, numRegSrc: ${params.numRegSrc}")
78
79  require(params.numExu <= 2, "IssueQueue has not supported more than 2 deq ports")
80  val deqFuCfgs     : Seq[Seq[FuConfig]] = params.exuBlockParams.map(_.fuConfigs)
81  val allDeqFuCfgs  : Seq[FuConfig] = params.exuBlockParams.flatMap(_.fuConfigs)
82  val fuCfgsCnt     : Map[FuConfig, Int] = allDeqFuCfgs.groupBy(x => x).map { case (cfg, cfgSeq) => (cfg, cfgSeq.length) }
83  val commonFuCfgs  : Seq[FuConfig] = fuCfgsCnt.filter(_._2 > 1).keys.toSeq
84  val fuLatencyMaps : Seq[Map[FuType.OHType, Int]] = params.exuBlockParams.map(x => x.fuLatencyMap)
85
86  println(s"[IssueQueueImp] ${params.getIQName} fuLatencyMaps: ${fuLatencyMaps}")
87  println(s"[IssueQueueImp] ${params.getIQName} commonFuCfgs: ${commonFuCfgs.map(_.name)}")
88  lazy val io = IO(new IssueQueueIO())
89  // Modules
90
91  val entries = Module(new Entries)
92  val fuBusyTableWrite = params.exuBlockParams.map { case x => OptionWrapper(x.latencyValMax > 0, Module(new FuBusyTableWrite(x.fuLatencyMap))) }
93  val fuBusyTableRead = params.exuBlockParams.map { case x => OptionWrapper(x.latencyValMax > 0, Module(new FuBusyTableRead(x.fuLatencyMap))) }
94  val intWbBusyTableWrite = params.exuBlockParams.map { case x => OptionWrapper(x.intLatencyCertain, Module(new FuBusyTableWrite(x.intFuLatencyMap))) }
95  val intWbBusyTableRead = params.exuBlockParams.map { case x => OptionWrapper(x.intLatencyCertain, Module(new FuBusyTableRead(x.intFuLatencyMap))) }
96  val vfWbBusyTableWrite = params.exuBlockParams.map { case x => OptionWrapper(x.vfLatencyCertain, Module(new FuBusyTableWrite(x.vfFuLatencyMap))) }
97  val vfWbBusyTableRead = params.exuBlockParams.map { case x => OptionWrapper(x.vfLatencyCertain, Module(new FuBusyTableRead(x.vfFuLatencyMap))) }
98
99  class WakeupQueueFlush extends Bundle {
100    val redirect = ValidIO(new Redirect)
101    val ldCancel = Vec(backendParams.LduCnt + backendParams.HyuCnt, new LoadCancelIO)
102    val og0Fail = Output(Bool())
103    val og1Fail = Output(Bool())
104    val finalFail = Output(Bool())
105  }
106
107  private def flushFunc(exuInput: ExuInput, flush: WakeupQueueFlush, stage: Int): Bool = {
108    val redirectFlush = exuInput.robIdx.needFlush(flush.redirect)
109    val loadDependencyFlush = LoadShouldCancel(exuInput.loadDependency, flush.ldCancel)
110    val ogFailFlush = stage match {
111      case 1 => flush.og0Fail
112      case 2 => flush.og1Fail
113      case 3 => flush.finalFail
114      case _ => false.B
115    }
116    redirectFlush || loadDependencyFlush || ogFailFlush
117  }
118
119  private def modificationFunc(exuInput: ExuInput, newInput: ExuInput): ExuInput = {
120    val lastExuInput = WireDefault(exuInput)
121    val newExuInput = WireDefault(newInput)
122    newExuInput.elements.foreach{ case (name, data) =>
123      if (lastExuInput.elements.contains(name)){
124        data := lastExuInput.elements(name)
125      }
126    }
127    newExuInput.loadDependency match {
128      case Some(deps) => deps.zip(exuInput.loadDependency.get).foreach(x => x._1 := x._2 << 1)
129      case None =>
130    }
131    if (newExuInput.pdestCopy.nonEmpty && !lastExuInput.pdestCopy.nonEmpty) {
132      newExuInput.pdestCopy.get.foreach(_ := lastExuInput.pdest)
133    }
134    newExuInput
135  }
136
137  val wakeUpQueues: Seq[Option[MultiWakeupQueue[ExuInput, WakeupQueueFlush]]] = params.exuBlockParams.map { x => OptionWrapper(x.isIQWakeUpSource, Module(
138    new MultiWakeupQueue(new ExuInput(x), new ExuInput(x, x.copyPdest, x.iqWakeUpSourcePairs.size / x.copyDistance), new WakeupQueueFlush, x.fuLatancySet, flushFunc, modificationFunc)
139  ))}
140  val deqBeforeDly = Wire(params.genIssueDecoupledBundle)
141
142  val intWbBusyTableIn = io.wbBusyTableRead.map(_.intWbBusyTable)
143  val vfWbBusyTableIn = io.wbBusyTableRead.map(_.vfWbBusyTable)
144  val intWbBusyTableOut = io.wbBusyTableWrite.map(_.intWbBusyTable)
145  val vfWbBusyTableOut = io.wbBusyTableWrite.map(_.vfWbBusyTable)
146  val intDeqRespSetOut = io.wbBusyTableWrite.map(_.intDeqRespSet)
147  val vfDeqRespSetOut = io.wbBusyTableWrite.map(_.vfDeqRespSet)
148  val fuBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W)))
149  val intWbBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W)))
150  val vfWbBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W)))
151  val s0_enqValidVec = io.enq.map(_.valid)
152  val s0_enqSelValidVec = Wire(Vec(params.numEnq, Bool()))
153  val s0_enqNotFlush = !io.flush.valid
154  val s0_enqBits = WireInit(VecInit(io.enq.map(_.bits)))
155  val s0_doEnqSelValidVec = s0_enqSelValidVec.map(_ && s0_enqNotFlush) //enqValid && notFlush && enqReady
156
157
158  val finalDeqSelValidVec = Wire(Vec(params.numDeq, Bool()))
159  val finalDeqSelOHVec    = Wire(Vec(params.numDeq, UInt(params.numEntries.W)))
160
161  val validVec = VecInit(entries.io.valid.asBools)
162  val canIssueVec = VecInit(entries.io.canIssue.asBools)
163  val clearVec = VecInit(entries.io.clear.asBools)
164  val deqFirstIssueVec = VecInit(entries.io.deq.map(_.isFirstIssue))
165
166  val dataSources: Vec[Vec[DataSource]] = entries.io.dataSources
167  val finalDataSources: Vec[Vec[DataSource]] = VecInit(finalDeqSelOHVec.map(oh => Mux1H(oh, dataSources)))
168  // (entryIdx)(srcIdx)(exuIdx)
169  val wakeUpL1ExuOH: Option[Vec[Vec[UInt]]] = entries.io.srcWakeUpL1ExuOH
170  val srcTimer: Option[Vec[Vec[UInt]]] = entries.io.srcTimer
171
172  // (deqIdx)(srcIdx)(exuIdx)
173  val finalWakeUpL1ExuOH: Option[Vec[Vec[UInt]]] = wakeUpL1ExuOH.map(x => VecInit(finalDeqSelOHVec.map(oh => Mux1H(oh, x))))
174  val finalSrcTimer = srcTimer.map(x => VecInit(finalDeqSelOHVec.map(oh => Mux1H(oh, x))))
175
176  val fuTypeVec = Wire(Vec(params.numEntries, FuType()))
177  val transEntryDeqVec = Wire(Vec(params.numEnq, ValidIO(new EntryBundle)))
178  val deqEntryVec = Wire(Vec(params.numDeq, ValidIO(new EntryBundle)))
179  val transSelVec = Wire(Vec(params.numEnq, UInt((params.numEntries-params.numEnq).W)))
180  val canIssueMergeAllBusy = Wire(Vec(params.numDeq, UInt(params.numEntries.W)))
181  val deqCanIssue = Wire(Vec(params.numDeq, UInt(params.numEntries.W)))
182
183  val enqEntryOldestSel = Wire(Vec(params.numDeq, ValidIO(UInt(params.numEnq.W))))
184  val othersEntryOldestSel = Wire(Vec(params.numDeq, ValidIO(UInt((params.numEntries - params.numEnq).W))))
185  val deqSelValidVec = Wire(Vec(params.numDeq, Bool()))
186  val deqSelOHVec    = Wire(Vec(params.numDeq, UInt(params.numEntries.W)))
187  val cancelDeqVec = Wire(Vec(params.numDeq, Bool()))
188
189  val subDeqSelValidVec = OptionWrapper(params.deqFuSame, Wire(Vec(params.numDeq, Bool())))
190  val subDeqSelOHVec = OptionWrapper(params.deqFuSame, Wire(Vec(params.numDeq, UInt(params.numEntries.W))))
191  val subDeqRequest = OptionWrapper(params.deqFuSame, Wire(UInt(params.numEntries.W)))
192
193  /**
194    * Connection of [[entries]]
195    */
196  entries.io match { case entriesIO: EntriesIO =>
197    entriesIO.flush <> io.flush
198    entriesIO.wakeUpFromWB := io.wakeupFromWB
199    entriesIO.wakeUpFromIQ := io.wakeupFromIQ
200    entriesIO.og0Cancel := io.og0Cancel
201    entriesIO.og1Cancel := io.og1Cancel
202    entriesIO.ldCancel := io.ldCancel
203    entriesIO.enq.zipWithIndex.foreach { case (enq: ValidIO[EntryBundle], i) =>
204      enq.valid := s0_doEnqSelValidVec(i)
205      val numLsrc = s0_enqBits(i).srcType.size.min(enq.bits.status.srcType.size)
206      for (j <- 0 until numLsrc) {
207        enq.bits.status.srcState(j) := s0_enqBits(i).srcState(j) & !LoadShouldCancel(Some(s0_enqBits(i).srcLoadDependency(j)), io.ldCancel)
208        enq.bits.status.psrc(j) := s0_enqBits(i).psrc(j)
209        enq.bits.status.srcType(j) := s0_enqBits(i).srcType(j)
210        enq.bits.status.dataSources(j).value := DataSource.reg
211        enq.bits.payload.debugInfo.enqRsTime := GTimer()
212      }
213      enq.bits.status.fuType := s0_enqBits(i).fuType
214      enq.bits.status.robIdx := s0_enqBits(i).robIdx
215      enq.bits.status.uopIdx.foreach(_ := s0_enqBits(i).uopIdx)
216      enq.bits.status.issueTimer := "b10".U
217      enq.bits.status.deqPortIdx := 0.U
218      enq.bits.status.issued := false.B
219      enq.bits.status.firstIssue := false.B
220      enq.bits.status.blocked := false.B
221
222      if (params.hasIQWakeUp) {
223        enq.bits.status.srcWakeUpL1ExuOH.get := 0.U.asTypeOf(enq.bits.status.srcWakeUpL1ExuOH.get)
224        enq.bits.status.srcTimer.get := 0.U.asTypeOf(enq.bits.status.srcTimer.get)
225        enq.bits.status.srcLoadDependency.foreach(_.zipWithIndex.foreach {
226          case (dep, srcIdx) =>
227            dep := VecInit(s0_enqBits(i).srcLoadDependency(srcIdx).map(x => x(x.getWidth - 2, 0) << 1))
228        })
229      }
230      if (params.inIntSchd && params.AluCnt > 0) {
231        // dirty code for lui+addi(w) fusion
232        val isLuiAddiFusion = s0_enqBits(i).isLUI32
233        val luiImm = Cat(s0_enqBits(i).lsrc(1), s0_enqBits(i).lsrc(0), s0_enqBits(i).imm(ImmUnion.maxLen - 1, 0))
234        enq.bits.imm.foreach(_ := Mux(isLuiAddiFusion, ImmUnion.LUI32.toImm32(luiImm), s0_enqBits(i).imm))
235      }
236      else if (params.inMemSchd && params.LduCnt > 0) {
237        // dirty code for fused_lui_load
238        val isLuiLoadFusion = SrcType.isNotReg(s0_enqBits(i).srcType(0)) && FuType.isLoad(s0_enqBits(i).fuType)
239        enq.bits.imm.foreach(_ := Mux(isLuiLoadFusion, Imm_LUI_LOAD().getLuiImm(s0_enqBits(i)), s0_enqBits(i).imm))
240      }
241      else {
242        enq.bits.imm.foreach(_ := s0_enqBits(i).imm)
243      }
244      enq.bits.payload := s0_enqBits(i)
245    }
246    entriesIO.deq.zipWithIndex.foreach { case (deq, i) =>
247      deq.enqEntryOldestSel := enqEntryOldestSel(i)
248      deq.othersEntryOldestSel := othersEntryOldestSel(i)
249      deq.subDeqRequest.foreach(_ := subDeqRequest.get)
250      deq.subDeqSelOH.foreach(_ := subDeqSelOHVec.get(i))
251      deq.deqReady := deqBeforeDly(i).ready
252      deq.deqSelOH.valid := deqSelValidVec(i)
253      deq.deqSelOH.bits := deqSelOHVec(i)
254    }
255    entriesIO.og0Resp.zipWithIndex.foreach { case (og0Resp, i) =>
256      og0Resp.valid := io.og0Resp(i).valid
257      og0Resp.bits.robIdx := io.og0Resp(i).bits.robIdx
258      og0Resp.bits.uopIdx := io.og0Resp(i).bits.uopIdx
259      og0Resp.bits.dataInvalidSqIdx := io.og0Resp(i).bits.dataInvalidSqIdx
260      og0Resp.bits.respType := io.og0Resp(i).bits.respType
261      og0Resp.bits.rfWen := io.og0Resp(i).bits.rfWen
262      og0Resp.bits.fuType := io.og0Resp(i).bits.fuType
263    }
264    entriesIO.og1Resp.zipWithIndex.foreach { case (og1Resp, i) =>
265      og1Resp.valid := io.og1Resp(i).valid
266      og1Resp.bits.robIdx := io.og1Resp(i).bits.robIdx
267      og1Resp.bits.uopIdx := io.og1Resp(i).bits.uopIdx
268      og1Resp.bits.dataInvalidSqIdx := io.og1Resp(i).bits.dataInvalidSqIdx
269      og1Resp.bits.respType := io.og1Resp(i).bits.respType
270      og1Resp.bits.rfWen := io.og1Resp(i).bits.rfWen
271      og1Resp.bits.fuType := io.og1Resp(i).bits.fuType
272    }
273    entriesIO.finalIssueResp.foreach(_.zipWithIndex.foreach { case (finalIssueResp, i) =>
274      finalIssueResp := io.finalIssueResp.get(i)
275    })
276    entriesIO.memAddrIssueResp.foreach(_.zipWithIndex.foreach { case (memAddrIssueResp, i) =>
277      memAddrIssueResp := io.memAddrIssueResp.get(i)
278    })
279    transEntryDeqVec := entriesIO.transEntryDeqVec
280    deqEntryVec := entriesIO.deq.map(_.deqEntry)
281    fuTypeVec := entriesIO.fuType
282    cancelDeqVec := entriesIO.cancelDeqVec
283    transSelVec := entriesIO.transSelVec
284  }
285
286
287  s0_enqSelValidVec := s0_enqValidVec.zip(io.enq).map{ case (enqValid, enq) => enqValid && enq.ready}
288
289  protected val commonAccept: UInt = Cat(fuTypeVec.map(fuType =>
290    FuType.FuTypeOrR(fuType, commonFuCfgs.map(_.fuType))
291  ).reverse)
292
293  // if deq port can accept the uop
294  protected val canAcceptVec: Seq[UInt] = deqFuCfgs.map { fuCfgs: Seq[FuConfig] =>
295    Cat(fuTypeVec.map(fuType =>
296      FuType.FuTypeOrR(fuType, fuCfgs.map(_.fuType))
297    ).reverse)
298  }
299
300  protected val deqCanAcceptVec: Seq[IndexedSeq[Bool]] = deqFuCfgs.map { fuCfgs: Seq[FuConfig] =>
301    fuTypeVec.map(fuType =>
302      FuType.FuTypeOrR(fuType, fuCfgs.map(_.fuType)))
303  }
304
305  canIssueMergeAllBusy.zipWithIndex.foreach { case (merge, i) =>
306    val mergeFuBusy = {
307      if (fuBusyTableWrite(i).nonEmpty) canIssueVec.asUInt & (~fuBusyTableMask(i))
308      else canIssueVec.asUInt
309    }
310    val mergeIntWbBusy = {
311      if (intWbBusyTableRead(i).nonEmpty) mergeFuBusy & (~intWbBusyTableMask(i))
312      else mergeFuBusy
313    }
314    val mergeVfWbBusy = {
315      if (vfWbBusyTableRead(i).nonEmpty) mergeIntWbBusy & (~vfWbBusyTableMask(i))
316      else mergeIntWbBusy
317    }
318    merge := mergeVfWbBusy
319  }
320
321  deqCanIssue.zipWithIndex.foreach { case (req, i) =>
322    req := canIssueMergeAllBusy(i) & VecInit(deqCanAcceptVec(i)).asUInt
323  }
324
325  if (params.numDeq == 2) {
326    require(params.deqFuSame || params.deqFuDiff, "The 2 deq ports need to be identical or completely different")
327  }
328
329  if (params.numDeq == 2 && params.deqFuSame) {
330    enqEntryOldestSel := DontCare
331
332    othersEntryOldestSel(0) := AgeDetector(numEntries = params.numEntries - params.numEnq,
333      enq = VecInit(transEntryDeqVec.zip(transSelVec).map{ case (transEntry, transSel) => Fill(params.numEntries-params.numEnq, transEntry.valid) & transSel }),
334      canIssue = canIssueVec.asUInt(params.numEntries-1, params.numEnq)
335    )
336    othersEntryOldestSel(1) := DontCare
337
338    subDeqRequest.get := canIssueVec.asUInt & ~Cat(othersEntryOldestSel(0).bits, 0.U((params.numEnq).W))
339
340    val subDeqPolicy = Module(new DeqPolicy())
341    subDeqPolicy.io.request := subDeqRequest.get
342    subDeqSelValidVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => oh.valid)
343    subDeqSelOHVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => oh.bits)
344
345    deqSelValidVec(0) := othersEntryOldestSel(0).valid || subDeqSelValidVec.get(1)
346    deqSelValidVec(1) := subDeqSelValidVec.get(0)
347    deqSelOHVec(0) := Mux(othersEntryOldestSel(0).valid,
348                          Cat(othersEntryOldestSel(0).bits, 0.U((params.numEnq).W)),
349                          subDeqSelOHVec.get(1)) & canIssueMergeAllBusy(0)
350    deqSelOHVec(1) := subDeqSelOHVec.get(0) & canIssueMergeAllBusy(1)
351
352    finalDeqSelValidVec.zip(finalDeqSelOHVec).zip(deqSelValidVec).zip(deqSelOHVec).zipWithIndex.foreach { case ((((selValid, selOH), deqValid), deqOH), i) =>
353      selValid := deqValid && deqOH.orR && deqBeforeDly(i).ready
354      selOH := deqOH
355    }
356  }
357  else {
358    enqEntryOldestSel := NewAgeDetector(numEntries = params.numEnq,
359      enq = VecInit(s0_doEnqSelValidVec),
360      canIssue = VecInit(deqCanIssue.map(_(params.numEnq-1, 0)))
361    )
362
363    othersEntryOldestSel := AgeDetector(numEntries = params.numEntries - params.numEnq,
364      enq = VecInit(transEntryDeqVec.zip(transSelVec).map{ case (transEntry, transSel) => Fill(params.numEntries-params.numEnq, transEntry.valid) & transSel }),
365      canIssue = VecInit(deqCanIssue.map(_(params.numEntries-1, params.numEnq)))
366    )
367
368    deqSelValidVec.zip(deqSelOHVec).zipWithIndex.foreach { case ((selValid, selOH), i) =>
369      if (params.exuBlockParams(i).fuConfigs.contains(FuConfig.FakeHystaCfg)) {
370        selValid := false.B
371        selOH := 0.U.asTypeOf(selOH)
372      } else {
373        selValid := othersEntryOldestSel(i).valid || enqEntryOldestSel(i).valid
374        selOH := Cat(othersEntryOldestSel(i).bits, Fill(params.numEnq, enqEntryOldestSel(i).valid && !othersEntryOldestSel(i).valid) & enqEntryOldestSel(i).bits)
375      }
376    }
377
378    finalDeqSelValidVec.zip(finalDeqSelOHVec).zip(deqSelValidVec).zip(deqSelOHVec).zipWithIndex.foreach { case ((((selValid, selOH), deqValid), deqOH), i) =>
379      selValid := deqValid && deqBeforeDly(i).ready
380      selOH := deqOH
381    }
382  }
383
384  val toBusyTableDeqResp = Wire(Vec(params.numDeq, ValidIO(new IssueQueueDeqRespBundle)))
385
386  toBusyTableDeqResp.zipWithIndex.foreach { case (deqResp, i) =>
387    deqResp.valid := finalDeqSelValidVec(i)
388    deqResp.bits.respType := RSFeedbackType.issueSuccess
389    deqResp.bits.robIdx := DontCare
390    deqResp.bits.dataInvalidSqIdx := DontCare
391    deqResp.bits.rfWen := DontCare
392    deqResp.bits.fuType := deqBeforeDly(i).bits.common.fuType
393    deqResp.bits.uopIdx := DontCare
394  }
395
396  //fuBusyTable
397  fuBusyTableWrite.zip(fuBusyTableRead).zipWithIndex.foreach { case ((busyTableWrite: Option[FuBusyTableWrite], busyTableRead: Option[FuBusyTableRead]), i) =>
398    if(busyTableWrite.nonEmpty) {
399      val btwr = busyTableWrite.get
400      val btrd = busyTableRead.get
401      btwr.io.in.deqResp := toBusyTableDeqResp(i)
402      btwr.io.in.og0Resp := io.og0Resp(i)
403      btwr.io.in.og1Resp := io.og1Resp(i)
404      btrd.io.in.fuBusyTable := btwr.io.out.fuBusyTable
405      btrd.io.in.fuTypeRegVec := fuTypeVec
406      fuBusyTableMask(i) := btrd.io.out.fuBusyTableMask
407    }
408    else {
409      fuBusyTableMask(i) := 0.U(params.numEntries.W)
410    }
411  }
412
413  //wbfuBusyTable write
414  intWbBusyTableWrite.zip(intWbBusyTableOut).zip(intDeqRespSetOut).zipWithIndex.foreach { case (((busyTableWrite: Option[FuBusyTableWrite], busyTable: Option[UInt]), deqResp), i) =>
415    if(busyTableWrite.nonEmpty) {
416      val btwr = busyTableWrite.get
417      val bt = busyTable.get
418      val dq = deqResp.get
419      btwr.io.in.deqResp := toBusyTableDeqResp(i)
420      btwr.io.in.og0Resp := io.og0Resp(i)
421      btwr.io.in.og1Resp := io.og1Resp(i)
422      bt := btwr.io.out.fuBusyTable
423      dq := btwr.io.out.deqRespSet
424    }
425  }
426
427  vfWbBusyTableWrite.zip(vfWbBusyTableOut).zip(vfDeqRespSetOut).zipWithIndex.foreach { case (((busyTableWrite: Option[FuBusyTableWrite], busyTable: Option[UInt]), deqResp), i) =>
428    if (busyTableWrite.nonEmpty) {
429      val btwr = busyTableWrite.get
430      val bt = busyTable.get
431      val dq = deqResp.get
432      btwr.io.in.deqResp := toBusyTableDeqResp(i)
433      btwr.io.in.og0Resp := io.og0Resp(i)
434      btwr.io.in.og1Resp := io.og1Resp(i)
435      bt := btwr.io.out.fuBusyTable
436      dq := btwr.io.out.deqRespSet
437    }
438  }
439
440  //wbfuBusyTable read
441  intWbBusyTableRead.zip(intWbBusyTableIn).zipWithIndex.foreach { case ((busyTableRead: Option[FuBusyTableRead], busyTable: Option[UInt]), i) =>
442    if(busyTableRead.nonEmpty) {
443      val btrd = busyTableRead.get
444      val bt = busyTable.get
445      btrd.io.in.fuBusyTable := bt
446      btrd.io.in.fuTypeRegVec := fuTypeVec
447      intWbBusyTableMask(i) := btrd.io.out.fuBusyTableMask
448    }
449    else {
450      intWbBusyTableMask(i) := 0.U(params.numEntries.W)
451    }
452  }
453  vfWbBusyTableRead.zip(vfWbBusyTableIn).zipWithIndex.foreach { case ((busyTableRead: Option[FuBusyTableRead], busyTable: Option[UInt]), i) =>
454    if (busyTableRead.nonEmpty) {
455      val btrd = busyTableRead.get
456      val bt = busyTable.get
457      btrd.io.in.fuBusyTable := bt
458      btrd.io.in.fuTypeRegVec := fuTypeVec
459      vfWbBusyTableMask(i) := btrd.io.out.fuBusyTableMask
460    }
461    else {
462      vfWbBusyTableMask(i) := 0.U(params.numEntries.W)
463    }
464  }
465
466  wakeUpQueues.zipWithIndex.foreach { case (wakeUpQueueOption, i) =>
467    val og0RespEach = io.og0Resp(i)
468    val og1RespEach = io.og1Resp(i)
469    wakeUpQueueOption.foreach {
470      wakeUpQueue =>
471        val flush = Wire(new WakeupQueueFlush)
472        flush.redirect := io.flush
473        flush.ldCancel := io.ldCancel
474        flush.og0Fail := io.og0Resp(i).valid && RSFeedbackType.isBlocked(io.og0Resp(i).bits.respType)
475        flush.og1Fail := io.og1Resp(i).valid && RSFeedbackType.isBlocked(io.og1Resp(i).bits.respType)
476        flush.finalFail := io.finalBlock(i)
477        wakeUpQueue.io.flush := flush
478        wakeUpQueue.io.enq.valid := deqBeforeDly(i).fire
479        wakeUpQueue.io.enq.bits.uop :<= deqBeforeDly(i).bits.common
480        wakeUpQueue.io.enq.bits.uop.pdestCopy.foreach(_ := 0.U)
481        wakeUpQueue.io.enq.bits.lat := getDeqLat(i, deqBeforeDly(i).bits.common.fuType)
482        wakeUpQueue.io.og0IssueFail := flush.og0Fail
483        wakeUpQueue.io.og1IssueFail := flush.og1Fail
484    }
485  }
486
487  deqBeforeDly.zipWithIndex.foreach { case (deq, i) =>
488    deq.valid                := finalDeqSelValidVec(i) && !cancelDeqVec(i)
489    deq.bits.addrOH          := finalDeqSelOHVec(i)
490    deq.bits.common.isFirstIssue := deqFirstIssueVec(i)
491    deq.bits.common.iqIdx    := OHToUInt(finalDeqSelOHVec(i))
492    deq.bits.common.fuType   := deqEntryVec(i).bits.status.fuType
493    deq.bits.common.fuOpType := deqEntryVec(i).bits.payload.fuOpType
494    deq.bits.common.rfWen.foreach(_ := deqEntryVec(i).bits.payload.rfWen)
495    deq.bits.common.fpWen.foreach(_ := deqEntryVec(i).bits.payload.fpWen)
496    deq.bits.common.vecWen.foreach(_ := deqEntryVec(i).bits.payload.vecWen)
497    deq.bits.common.flushPipe.foreach(_ := deqEntryVec(i).bits.payload.flushPipe)
498    deq.bits.common.pdest := deqEntryVec(i).bits.payload.pdest
499    deq.bits.common.robIdx := deqEntryVec(i).bits.status.robIdx
500
501    require(deq.bits.common.dataSources.size <= finalDataSources(i).size)
502    deq.bits.common.dataSources.zip(finalDataSources(i)).foreach { case (sink, source) => sink := source}
503    deq.bits.common.l1ExuOH.foreach(_ := finalWakeUpL1ExuOH.get(i))
504    deq.bits.common.srcTimer.foreach(_ := finalSrcTimer.get(i))
505    deq.bits.common.loadDependency.foreach(_ := deqEntryVec(i).bits.status.mergedLoadDependency.get)
506    deq.bits.common.deqLdExuIdx.foreach(_ := params.backendParam.getLdExuIdx(deq.bits.exuParams).U)
507    deq.bits.common.src := DontCare
508    deq.bits.common.preDecode.foreach(_ := deqEntryVec(i).bits.payload.preDecodeInfo)
509
510    deq.bits.rf.zip(deqEntryVec(i).bits.status.psrc).zip(deqEntryVec(i).bits.status.srcType).foreach { case ((rf, psrc), srcType) =>
511      // psrc in status array can be pregIdx of IntRegFile or VfRegFile
512      rf.foreach(_.addr := psrc)
513      rf.foreach(_.srcType := srcType)
514    }
515    deq.bits.srcType.zip(deqEntryVec(i).bits.status.srcType).foreach { case (sink, source) =>
516      sink := source
517    }
518    deq.bits.immType := deqEntryVec(i).bits.payload.selImm
519    deq.bits.common.imm := deqEntryVec(i).bits.imm.getOrElse(0.U)
520
521    deq.bits.common.perfDebugInfo := deqEntryVec(i).bits.payload.debugInfo
522    deq.bits.common.perfDebugInfo.selectTime := GTimer()
523    deq.bits.common.perfDebugInfo.issueTime := GTimer() + 1.U
524  }
525
526  private val deqShift = WireDefault(deqBeforeDly)
527  deqShift.zip(deqBeforeDly).foreach {
528    case (shifted, original) =>
529      original.ready := shifted.ready // this will not cause combinational loop
530      shifted.bits.common.loadDependency.foreach(
531        _ := original.bits.common.loadDependency.get.map(_ << 1)
532      )
533  }
534  io.deqDelay.zip(deqShift).foreach { case (deqDly, deq) =>
535    NewPipelineConnect(
536      deq, deqDly, deqDly.valid,
537      false.B,
538      Option("Scheduler2DataPathPipe")
539    )
540  }
541  if(backendParams.debugEn) {
542    dontTouch(io.deqDelay)
543  }
544  io.wakeupToIQ.zipWithIndex.foreach { case (wakeup, i) =>
545    if (wakeUpQueues(i).nonEmpty && finalWakeUpL1ExuOH.nonEmpty) {
546      wakeup.valid := wakeUpQueues(i).get.io.deq.valid
547      wakeup.bits.fromExuInput(wakeUpQueues(i).get.io.deq.bits, finalWakeUpL1ExuOH.get(i))
548      wakeup.bits.loadDependency := wakeUpQueues(i).get.io.deq.bits.loadDependency.getOrElse(0.U.asTypeOf(wakeup.bits.loadDependency))
549      wakeup.bits.is0Lat := getDeqLat(i, wakeUpQueues(i).get.io.deq.bits.fuType) === 0.U
550    } else if (wakeUpQueues(i).nonEmpty) {
551      wakeup.valid := wakeUpQueues(i).get.io.deq.valid
552      wakeup.bits.fromExuInput(wakeUpQueues(i).get.io.deq.bits)
553      wakeup.bits.loadDependency := wakeUpQueues(i).get.io.deq.bits.loadDependency.getOrElse(0.U.asTypeOf(wakeup.bits.loadDependency))
554      wakeup.bits.is0Lat := getDeqLat(i, wakeUpQueues(i).get.io.deq.bits.fuType) === 0.U
555    } else {
556      wakeup.valid := false.B
557      wakeup.bits := 0.U.asTypeOf(wakeup.bits)
558      wakeup.bits.is0Lat :=  0.U
559    }
560    if(wakeup.bits.pdestCopy.nonEmpty){
561      wakeup.bits.pdestCopy.get := wakeUpQueues(i).get.io.deq.bits.pdestCopy.get
562    }
563  }
564
565  // Todo: better counter implementation
566  private val enqHasValid = validVec.take(params.numEnq).reduce(_ | _)
567  private val enqEntryValidCnt = PopCount(validVec.take(params.numEnq))
568  private val othersValidCnt = PopCount(validVec.drop(params.numEnq))
569  io.status.leftVec(0) := validVec.drop(params.numEnq).reduce(_ & _)
570  for (i <- 0 until params.numEnq) {
571    io.status.leftVec(i + 1) := othersValidCnt === (params.numEntries - params.numEnq - (i + 1)).U
572  }
573  private val othersLeftOneCaseVec = Wire(Vec(params.numEntries - params.numEnq, UInt((params.numEntries - params.numEnq).W)))
574  othersLeftOneCaseVec.zipWithIndex.foreach { case (leftone, i) =>
575    leftone := ~(1.U((params.numEntries - params.numEnq).W) << i)
576  }
577  private val othersLeftOne = othersLeftOneCaseVec.map(_ === VecInit(validVec.drop(params.numEnq)).asUInt).reduce(_ | _)
578  private val othersCanotIn = othersLeftOne || validVec.drop(params.numEnq).reduce(_ & _)
579
580  io.enq.foreach(_.ready := !othersCanotIn || !enqHasValid)
581  io.status.empty := !Cat(validVec).orR
582  io.status.full := othersCanotIn
583  io.status.validCnt := PopCount(validVec)
584
585  protected def getDeqLat(deqPortIdx: Int, fuType: UInt) : UInt = {
586    Mux1H(fuLatencyMaps(deqPortIdx) map { case (k, v) => (fuType(k.id), v.U) })
587  }
588
589  // issue perf counter
590  // enq count
591  XSPerfAccumulate("enq_valid_cnt", PopCount(io.enq.map(_.fire)))
592  XSPerfAccumulate("enq_fire_cnt", PopCount(io.enq.map(_.fire)))
593  // valid count
594  XSPerfHistogram("enq_entry_valid_cnt", enqEntryValidCnt, true.B, 0, params.numEnq + 1)
595  XSPerfHistogram("other_entry_valid_cnt", othersValidCnt, true.B, 0, params.numEntries - params.numEnq + 1)
596  XSPerfHistogram("valid_cnt", PopCount(validVec), true.B, 0, params.numEntries + 1)
597  // only split when more than 1 func type
598  if (params.getFuCfgs.size > 0) {
599    for (t <- FuType.functionNameMap.keys) {
600      val fuName = FuType.functionNameMap(t)
601      if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _)) {
602        XSPerfHistogram(s"valid_cnt_hist_futype_${fuName}", PopCount(validVec.zip(fuTypeVec).map { case (v, fu) => v && fu === t.U }), true.B, 0, params.numEntries, 1)
603      }
604    }
605  }
606  // ready instr count
607  private val readyEntriesCnt = PopCount(validVec.zip(canIssueVec).map(x => x._1 && x._2))
608  XSPerfHistogram("ready_cnt", readyEntriesCnt, true.B, 0, params.numEntries + 1)
609  // only split when more than 1 func type
610  if (params.getFuCfgs.size > 0) {
611    for (t <- FuType.functionNameMap.keys) {
612      val fuName = FuType.functionNameMap(t)
613      if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _)) {
614        XSPerfHistogram(s"ready_cnt_hist_futype_${fuName}", PopCount(validVec.zip(canIssueVec).zip(fuTypeVec).map { case ((v, c), fu) => v && c && fu === t.U }), true.B, 0, params.numEntries, 1)
615      }
616    }
617  }
618
619  // deq instr count
620  XSPerfAccumulate("issue_instr_pre_count", PopCount(deqBeforeDly.map(_.valid)))
621  XSPerfHistogram("issue_instr_pre_count_hist", PopCount(deqBeforeDly.map(_.valid)), true.B, 0, params.numDeq + 1, 1)
622  XSPerfAccumulate("issue_instr_count", PopCount(io.deqDelay.map(_.valid)))
623  XSPerfHistogram("issue_instr_count_hist", PopCount(io.deqDelay.map(_.valid)), true.B, 0, params.numDeq + 1, 1)
624
625  // deq instr data source count
626  XSPerfAccumulate("issue_datasource_reg", deqBeforeDly.map{ deq =>
627    PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) })
628  }.reduce(_ +& _))
629  XSPerfAccumulate("issue_datasource_bypass", deqBeforeDly.map{ deq =>
630    PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) })
631  }.reduce(_ +& _))
632  XSPerfAccumulate("issue_datasource_forward", deqBeforeDly.map{ deq =>
633    PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) })
634  }.reduce(_ +& _))
635  XSPerfAccumulate("issue_datasource_noreg", deqBeforeDly.map{ deq =>
636    PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) })
637  }.reduce(_ +& _))
638
639  XSPerfHistogram("issue_datasource_reg_hist", deqBeforeDly.map{ deq =>
640    PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) })
641  }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1)
642  XSPerfHistogram("issue_datasource_bypass_hist", deqBeforeDly.map{ deq =>
643    PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) })
644  }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1)
645  XSPerfHistogram("issue_datasource_forward_hist", deqBeforeDly.map{ deq =>
646    PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) })
647  }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1)
648  XSPerfHistogram("issue_datasource_noreg_hist", deqBeforeDly.map{ deq =>
649    PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) })
650  }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1)
651
652  // deq instr data source count for each futype
653  for (t <- FuType.functionNameMap.keys) {
654    val fuName = FuType.functionNameMap(t)
655    if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _)) {
656      XSPerfAccumulate(s"issue_datasource_reg_futype_${fuName}", deqBeforeDly.map{ deq =>
657        PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U })
658      }.reduce(_ +& _))
659      XSPerfAccumulate(s"issue_datasource_bypass_futype_${fuName}", deqBeforeDly.map{ deq =>
660        PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U })
661      }.reduce(_ +& _))
662      XSPerfAccumulate(s"issue_datasource_forward_futype_${fuName}", deqBeforeDly.map{ deq =>
663        PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U })
664      }.reduce(_ +& _))
665      XSPerfAccumulate(s"issue_datasource_noreg_futype_${fuName}", deqBeforeDly.map{ deq =>
666        PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U })
667      }.reduce(_ +& _))
668
669      XSPerfHistogram(s"issue_datasource_reg_hist_futype_${fuName}", deqBeforeDly.map{ deq =>
670        PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U })
671      }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1)
672      XSPerfHistogram(s"issue_datasource_bypass_hist_futype_${fuName}", deqBeforeDly.map{ deq =>
673        PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U })
674      }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1)
675      XSPerfHistogram(s"issue_datasource_forward_hist_futype_${fuName}", deqBeforeDly.map{ deq =>
676        PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U })
677      }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1)
678      XSPerfHistogram(s"issue_datasource_noreg_hist_futype_${fuName}", deqBeforeDly.map{ deq =>
679        PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U })
680      }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1)
681    }
682  }
683
684  // cancel instr count
685  if (params.hasIQWakeUp) {
686    val cancelVec: Vec[Bool] = entries.io.cancel.get
687    XSPerfAccumulate("cancel_instr_count", PopCount(validVec.zip(cancelVec).map(x => x._1 & x._2)))
688    XSPerfHistogram("cancel_instr_hist", PopCount(validVec.zip(cancelVec).map(x => x._1 & x._2)), true.B, 0, params.numEntries, 1)
689    for (t <- FuType.functionNameMap.keys) {
690      val fuName = FuType.functionNameMap(t)
691      if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _)) {
692        XSPerfAccumulate(s"cancel_instr_count_futype_${fuName}", PopCount(validVec.zip(cancelVec).zip(fuTypeVec).map{ case ((x, y), fu) => x & y & fu === t.U }))
693        XSPerfHistogram(s"cancel_instr_hist_futype_${fuName}", PopCount(validVec.zip(cancelVec).zip(fuTypeVec).map{ case ((x, y), fu) => x & y & fu === t.U }), true.B, 0, params.numEntries, 1)
694      }
695    }
696  }
697}
698
699class IssueQueueJumpBundle extends Bundle {
700  val pc = UInt(VAddrData().dataWidth.W)
701}
702
703class IssueQueueLoadBundle(implicit p: Parameters) extends XSBundle {
704  val fastMatch = UInt(backendParams.LduCnt.W)
705  val fastImm = UInt(12.W)
706}
707
708class IssueQueueIntIO()(implicit p: Parameters, params: IssueBlockParams) extends IssueQueueIO
709
710class IssueQueueIntImp(override val wrapper: IssueQueue)(implicit p: Parameters, iqParams: IssueBlockParams)
711  extends IssueQueueImp(wrapper)
712{
713  io.suggestName("none")
714  override lazy val io = IO(new IssueQueueIntIO).suggestName("io")
715
716  deqBeforeDly.zipWithIndex.foreach{ case (deq, i) => {
717    deq.bits.common.pc.foreach(_ := deqEntryVec(i).bits.payload.pc)
718    deq.bits.common.preDecode.foreach(_ := deqEntryVec(i).bits.payload.preDecodeInfo)
719    deq.bits.common.ftqIdx.foreach(_ := deqEntryVec(i).bits.payload.ftqPtr)
720    deq.bits.common.ftqOffset.foreach(_ := deqEntryVec(i).bits.payload.ftqOffset)
721    deq.bits.common.predictInfo.foreach(x => {
722      x.target := DontCare
723      x.taken := deqEntryVec(i).bits.payload.pred_taken
724    })
725    // for std
726    deq.bits.common.sqIdx.foreach(_ := deqEntryVec(i).bits.payload.sqIdx)
727    // for i2f
728    deq.bits.common.fpu.foreach(_ := deqEntryVec(i).bits.payload.fpu)
729  }}
730}
731
732class IssueQueueVfImp(override val wrapper: IssueQueue)(implicit p: Parameters, iqParams: IssueBlockParams)
733  extends IssueQueueImp(wrapper)
734{
735  s0_enqBits.foreach{ x =>
736    x.srcType(3) := SrcType.vp // v0: mask src
737    x.srcType(4) := SrcType.vp // vl&vtype
738  }
739  deqBeforeDly.zipWithIndex.foreach{ case (deq, i) => {
740    deq.bits.common.fpu.foreach(_ := deqEntryVec(i).bits.payload.fpu)
741    deq.bits.common.vpu.foreach(_ := deqEntryVec(i).bits.payload.vpu)
742    deq.bits.common.vpu.foreach(_.vuopIdx := deqEntryVec(i).bits.payload.uopIdx)
743    deq.bits.common.vpu.foreach(_.lastUop := deqEntryVec(i).bits.payload.lastUop)
744  }}
745}
746
747class IssueQueueMemBundle(implicit p: Parameters, params: IssueBlockParams) extends Bundle {
748  val feedbackIO = Flipped(Vec(params.numDeq, new MemRSFeedbackIO))
749  val checkWait = new Bundle {
750    val stIssuePtr = Input(new SqPtr)
751    val memWaitUpdateReq = Flipped(new MemWaitUpdateReq)
752  }
753  val loadFastMatch = Output(Vec(params.LduCnt, new IssueQueueLoadBundle))
754
755  // vector
756  val sqDeqPtr = OptionWrapper(params.isVecMemIQ, Input(new SqPtr))
757  val lqDeqPtr = OptionWrapper(params.isVecMemIQ, Input(new LqPtr))
758}
759
760class IssueQueueMemIO(implicit p: Parameters, params: IssueBlockParams) extends IssueQueueIO {
761  val memIO = Some(new IssueQueueMemBundle)
762}
763
764class IssueQueueMemAddrImp(override val wrapper: IssueQueue)(implicit p: Parameters, params: IssueBlockParams)
765  extends IssueQueueImp(wrapper) with HasCircularQueuePtrHelper {
766
767  require(params.StdCnt == 0 && (params.LduCnt + params.StaCnt + params.HyuCnt + params.VlduCnt) > 0, "IssueQueueMemAddrImp can only be instance of MemAddr IQ, " +
768    s"StdCnt: ${params.StdCnt}, LduCnt: ${params.LduCnt}, StaCnt: ${params.StaCnt}, HyuCnt: ${params.HyuCnt}")
769  println(s"[IssueQueueMemAddrImp] StdCnt: ${params.StdCnt}, LduCnt: ${params.LduCnt}, StaCnt: ${params.StaCnt}, HyuCnt: ${params.HyuCnt}")
770
771  io.suggestName("none")
772  override lazy val io = IO(new IssueQueueMemIO).suggestName("io")
773  private val memIO = io.memIO.get
774
775  memIO.loadFastMatch := 0.U.asTypeOf(memIO.loadFastMatch) // TODO: is still needed?
776
777  for (i <- io.enq.indices) {
778    val blockNotReleased = isAfter(io.enq(i).bits.sqIdx, memIO.checkWait.stIssuePtr)
779    val storeAddrWaitForIsIssuing = VecInit((0 until StorePipelineWidth).map(i => {
780      memIO.checkWait.memWaitUpdateReq.robIdx(i).valid &&
781        memIO.checkWait.memWaitUpdateReq.robIdx(i).bits.value === io.enq(i).bits.waitForRobIdx.value
782    })).asUInt.orR && !io.enq(i).bits.loadWaitStrict // is waiting for store addr ready
783    s0_enqBits(i).loadWaitBit := io.enq(i).bits.loadWaitBit && !storeAddrWaitForIsIssuing && blockNotReleased
784    // when have vpu
785    if (params.VlduCnt > 0 || params.VstuCnt > 0) {
786      s0_enqBits(i).srcType(3) := SrcType.vp // v0: mask src
787      s0_enqBits(i).srcType(4) := SrcType.vp // vl&vtype
788    }
789  }
790
791  for (i <- entries.io.enq.indices) {
792    entries.io.enq(i).bits.status match { case enqData =>
793      enqData.blocked := false.B // s0_enqBits(i).loadWaitBit
794      enqData.mem.get.strictWait := s0_enqBits(i).loadWaitStrict
795      enqData.mem.get.waitForStd := false.B
796      enqData.mem.get.waitForRobIdx := s0_enqBits(i).waitForRobIdx
797      enqData.mem.get.waitForSqIdx := 0.U.asTypeOf(enqData.mem.get.waitForSqIdx) // generated by sq, will be updated later
798      enqData.mem.get.sqIdx := s0_enqBits(i).sqIdx
799    }
800
801    entries.io.fromMem.get.slowResp.zipWithIndex.foreach { case (slowResp, i) =>
802      slowResp.valid                 := memIO.feedbackIO(i).feedbackSlow.valid
803      slowResp.bits.robIdx           := memIO.feedbackIO(i).feedbackSlow.bits.robIdx
804      slowResp.bits.uopIdx           := DontCare
805      slowResp.bits.respType         := Mux(memIO.feedbackIO(i).feedbackSlow.bits.hit, RSFeedbackType.fuIdle, RSFeedbackType.feedbackInvalid)
806      slowResp.bits.dataInvalidSqIdx := memIO.feedbackIO(i).feedbackSlow.bits.dataInvalidSqIdx
807      slowResp.bits.rfWen := DontCare
808      slowResp.bits.fuType := DontCare
809    }
810
811    entries.io.fromMem.get.fastResp.zipWithIndex.foreach { case (fastResp, i) =>
812      fastResp.valid                 := memIO.feedbackIO(i).feedbackFast.valid
813      fastResp.bits.robIdx           := memIO.feedbackIO(i).feedbackFast.bits.robIdx
814      fastResp.bits.uopIdx           := DontCare
815      fastResp.bits.respType         := Mux(memIO.feedbackIO(i).feedbackFast.bits.hit, RSFeedbackType.fuIdle, memIO.feedbackIO(i).feedbackFast.bits.sourceType)
816      fastResp.bits.dataInvalidSqIdx := 0.U.asTypeOf(fastResp.bits.dataInvalidSqIdx)
817      fastResp.bits.rfWen := DontCare
818      fastResp.bits.fuType := DontCare
819    }
820
821    entries.io.fromMem.get.memWaitUpdateReq := memIO.checkWait.memWaitUpdateReq
822    entries.io.fromMem.get.stIssuePtr := memIO.checkWait.stIssuePtr
823  }
824
825  deqBeforeDly.zipWithIndex.foreach { case (deq, i) =>
826    deq.bits.common.loadWaitBit.foreach(_ := deqEntryVec(i).bits.payload.loadWaitBit)
827    deq.bits.common.waitForRobIdx.foreach(_ := deqEntryVec(i).bits.payload.waitForRobIdx)
828    deq.bits.common.storeSetHit.foreach(_ := deqEntryVec(i).bits.payload.storeSetHit)
829    deq.bits.common.loadWaitStrict.foreach(_ := deqEntryVec(i).bits.payload.loadWaitStrict)
830    deq.bits.common.ssid.foreach(_ := deqEntryVec(i).bits.payload.ssid)
831    deq.bits.common.sqIdx.get := deqEntryVec(i).bits.payload.sqIdx
832    deq.bits.common.lqIdx.get := deqEntryVec(i).bits.payload.lqIdx
833    deq.bits.common.ftqIdx.foreach(_ := deqEntryVec(i).bits.payload.ftqPtr)
834    deq.bits.common.ftqOffset.foreach(_ := deqEntryVec(i).bits.payload.ftqOffset)
835    // when have vpu
836    if (params.VlduCnt > 0 || params.VstuCnt > 0) {
837      deq.bits.common.vpu.foreach(_ := deqEntryVec(i).bits.payload.vpu)
838      deq.bits.common.vpu.foreach(_.vuopIdx := deqEntryVec(i).bits.payload.uopIdx)
839    }
840  }
841}
842
843class IssueQueueVecMemImp(override val wrapper: IssueQueue)(implicit p: Parameters, params: IssueBlockParams)
844  extends IssueQueueImp(wrapper) with HasCircularQueuePtrHelper {
845
846  require((params.VstdCnt + params.VlduCnt + params.VstaCnt) > 0, "IssueQueueVecMemImp can only be instance of VecMem IQ")
847
848  io.suggestName("none")
849  override lazy val io = IO(new IssueQueueMemIO).suggestName("io")
850  private val memIO = io.memIO.get
851
852  def selectOldUop(robIdx: Seq[RobPtr], uopIdx: Seq[UInt], valid: Seq[Bool]): Vec[Bool] = {
853    val compareVec = (0 until robIdx.length).map(i => (0 until i).map(j => isAfter(robIdx(j), robIdx(i)) || (robIdx(j).value === robIdx(i).value && uopIdx(i) < uopIdx(j))))
854    val resultOnehot = VecInit((0 until robIdx.length).map(i => Cat((0 until robIdx.length).map(j =>
855      (if (j < i) !valid(j) || compareVec(i)(j)
856      else if (j == i) valid(i)
857      else !valid(j) || !compareVec(j)(i))
858    )).andR))
859    resultOnehot
860  }
861
862  val robIdxVec = entries.io.robIdx.get
863  val uopIdxVec = entries.io.uopIdx.get
864  val allEntryOldestOH = selectOldUop(robIdxVec, uopIdxVec, validVec)
865
866  finalDeqSelValidVec.head := (allEntryOldestOH.asUInt & canIssueVec.asUInt).orR
867  finalDeqSelOHVec.head := allEntryOldestOH.asUInt & canIssueVec.asUInt
868
869  if (params.isVecMemAddrIQ) {
870    s0_enqBits.foreach{ x =>
871      x.srcType(3) := SrcType.vp // v0: mask src
872      x.srcType(4) := SrcType.vp // vl&vtype
873    }
874
875    for (i <- io.enq.indices) {
876      s0_enqBits(i).loadWaitBit := false.B
877    }
878
879    for (i <- entries.io.enq.indices) {
880      entries.io.enq(i).bits.status match { case enqData =>
881        enqData.blocked := false.B // s0_enqBits(i).loadWaitBit
882        enqData.mem.get.strictWait := s0_enqBits(i).loadWaitStrict
883        enqData.mem.get.waitForStd := false.B
884        enqData.mem.get.waitForRobIdx := s0_enqBits(i).waitForRobIdx
885        enqData.mem.get.waitForSqIdx := 0.U.asTypeOf(enqData.mem.get.waitForSqIdx) // generated by sq, will be updated later
886        enqData.mem.get.sqIdx := s0_enqBits(i).sqIdx
887      }
888
889      entries.io.fromMem.get.slowResp.zipWithIndex.foreach { case (slowResp, i) =>
890        slowResp.valid                 := memIO.feedbackIO(i).feedbackSlow.valid
891        slowResp.bits.robIdx           := memIO.feedbackIO(i).feedbackSlow.bits.robIdx
892        slowResp.bits.uopIdx           := DontCare
893        slowResp.bits.respType         := Mux(memIO.feedbackIO(i).feedbackSlow.bits.hit, RSFeedbackType.fuIdle, RSFeedbackType.feedbackInvalid)
894        slowResp.bits.dataInvalidSqIdx := memIO.feedbackIO(i).feedbackSlow.bits.dataInvalidSqIdx
895        slowResp.bits.rfWen := DontCare
896        slowResp.bits.fuType := DontCare
897      }
898
899      entries.io.fromMem.get.fastResp.zipWithIndex.foreach { case (fastResp, i) =>
900        fastResp.valid                 := memIO.feedbackIO(i).feedbackFast.valid
901        fastResp.bits.robIdx           := memIO.feedbackIO(i).feedbackFast.bits.robIdx
902        fastResp.bits.uopIdx           := DontCare
903        fastResp.bits.respType         := memIO.feedbackIO(i).feedbackFast.bits.sourceType
904        fastResp.bits.dataInvalidSqIdx := 0.U.asTypeOf(fastResp.bits.dataInvalidSqIdx)
905        fastResp.bits.rfWen := DontCare
906        fastResp.bits.fuType := DontCare
907      }
908
909      entries.io.fromMem.get.memWaitUpdateReq := memIO.checkWait.memWaitUpdateReq
910      entries.io.fromMem.get.stIssuePtr := memIO.checkWait.stIssuePtr
911    }
912  }
913
914  for (i <- entries.io.enq.indices) {
915    entries.io.enq(i).bits.status match { case enqData =>
916      enqData.vecMem.get.sqIdx := s0_enqBits(i).sqIdx
917      enqData.vecMem.get.lqIdx := s0_enqBits(i).lqIdx
918    }
919  }
920
921  entries.io.fromLsq.get.sqDeqPtr := memIO.sqDeqPtr.get
922  entries.io.fromLsq.get.lqDeqPtr := memIO.lqDeqPtr.get
923
924  deqBeforeDly.zipWithIndex.foreach { case (deq, i) =>
925    deq.bits.common.sqIdx.foreach(_ := deqEntryVec(i).bits.payload.sqIdx)
926    deq.bits.common.lqIdx.foreach(_ := deqEntryVec(i).bits.payload.lqIdx)
927    if (params.isVecLdAddrIQ) {
928      deq.bits.common.ftqIdx.get := deqEntryVec(i).bits.payload.ftqPtr
929      deq.bits.common.ftqOffset.get := deqEntryVec(i).bits.payload.ftqOffset
930    }
931    deq.bits.common.fpu.foreach(_ := deqEntryVec(i).bits.payload.fpu)
932    deq.bits.common.vpu.foreach(_ := deqEntryVec(i).bits.payload.vpu)
933    deq.bits.common.vpu.foreach(_.vuopIdx := deqEntryVec(i).bits.payload.uopIdx)
934    deq.bits.common.vpu.foreach(_.lastUop := deqEntryVec(i).bits.payload.lastUop)
935  }
936}
937