1package xiangshan.backend.issue 2 3import chisel3._ 4import chisel3.util._ 5import xiangshan._ 6import xiangshan.utils._ 7 8trait IQConst{ 9 val iqSize = 8 10 val iqIdxWidth = log2Up(iqSize) 11} 12 13sealed abstract class IQBundle extends XSBundle with IQConst 14sealed abstract class IQModule extends XSModule with IQConst //with NeedImpl 15 16sealed class CmpInputBundle extends IQBundle{ 17 val instRdy = Input(Bool()) 18 val roqIdx = Input(UInt(RoqIdxWidth.W)) 19 val iqIdx = Input(UInt(iqIdxWidth.W)) 20 21 def apply(instRdy: Bool,roqIdx: UInt,iqIdx: UInt ) = { 22 this.instRdy := instRdy 23 this.roqIdx := roqIdx 24 this.iqIdx := iqIdx 25 this 26 } 27} 28 29 30sealed class CompareCircuitUnit extends IQModule { 31 val io = IO(new Bundle(){ 32 val in1 = new CmpInputBundle 33 val in2 = new CmpInputBundle 34 val out = Flipped(new CmpInputBundle) 35 }) 36 37 val roqIdx1 = io.in1.roqIdx 38 val roqIdx2 = io.in2.roqIdx 39 val iqIdx1 = io.in1.iqIdx 40 val iqIdx2 = io.in2.iqIdx 41 42 val inst1Rdy = io.in1.instRdy 43 val inst2Rdy = io.in2.instRdy 44 45 io.out.instRdy := inst1Rdy | inst2Rdy 46 io.out.roqIdx := roqIdx2 47 io.out.iqIdx := iqIdx2 48 49 when((inst1Rdy && !inst2Rdy) || (inst1Rdy && inst2Rdy && (roqIdx1 < roqIdx2))){ 50 io.out.roqIdx := roqIdx1 51 io.out.iqIdx := iqIdx1 52 } 53 54} 55 56object CCU{ 57 def apply(in1: CmpInputBundle, in2: CmpInputBundle) = { 58 val CCU = Module(new CompareCircuitUnit) 59 CCU.io.in1 <> in1 60 CCU.io.in2 <> in2 61 CCU.io.out 62 } 63} 64 65object ParallelSel { 66 def apply(iq: Seq[CmpInputBundle]): CmpInputBundle = { 67 iq match { 68 case Seq(a) => a 69 case Seq(a, b) => CCU(a, b) 70 case _ => 71 apply(Seq(apply(iq take iq.size/2), apply(iq drop iq.size/2))) 72 } 73 } 74} 75 76class IssueQueue(val fuTypeInt: BigInt, val wakeupCnt: Int, val bypassCnt: Int = 0, val fixedDelay: Int = 1) extends IQModule { 77 78 val useBypass = bypassCnt > 0 79 80 val io = IO(new Bundle() { 81 // flush Issue Queue 82 val redirect = Flipped(ValidIO(new Redirect)) 83 84 // enq Ctrl sigs at dispatch-2 85 val enqCtrl = Flipped(DecoupledIO(new MicroOp)) 86 // enq Data at next cycle (regfile has 1 cycle latency) 87 val enqData = Flipped(ValidIO(new ExuInput)) 88 89 // broadcast selected uop to other issue queues which has bypasses 90 val selectedUop = if(useBypass) ValidIO(new MicroOp) else null 91 92 // send to exu 93 val deq = DecoupledIO(new ExuInput) 94 95 // listen to write back bus 96 val wakeUpPorts = Vec(wakeupCnt, Flipped(ValidIO(new ExuOutput))) 97 98 // use bypass uops to speculative wake-up 99 val bypassUops = if(useBypass) Vec(bypassCnt, Flipped(ValidIO(new MicroOp))) else null 100 val bypassData = if(useBypass) Vec(bypassCnt, Flipped(ValidIO(new ExuOutput))) else null 101 }) 102 //--------------------------------------------------------- 103 // Issue Queue 104 //--------------------------------------------------------- 105 106 //Tag Queue 107 val ctrlFlow = Mem(iqSize,new CtrlFlow) 108 val ctrlSig = Mem(iqSize,new CtrlSignals) 109 val brMask = Reg(Vec(iqSize, UInt(BrqSize.W))) 110 val brTag = Reg(Vec(iqSize, UInt(BrTagWidth.W))) 111 val validReg = RegInit(VecInit(Seq.fill(iqSize)(false.B))) 112 val validWillFalse= WireInit(VecInit(Seq.fill(iqSize)(false.B))) 113 val valid = validReg.asUInt & ~validWillFalse.asUInt 114 val src1Rdy = Reg(Vec(iqSize, Bool())) 115 val src2Rdy = Reg(Vec(iqSize, Bool())) 116 val src3Rdy = Reg(Vec(iqSize, Bool())) 117 val prfSrc1 = Reg(Vec(iqSize, UInt(PhyRegIdxWidth.W))) 118 val prfSrc2 = Reg(Vec(iqSize, UInt(PhyRegIdxWidth.W))) 119 val prfSrc3 = Reg(Vec(iqSize, UInt(PhyRegIdxWidth.W))) 120 val prfDest = Reg(Vec(iqSize, UInt(PhyRegIdxWidth.W))) 121 val oldPDest = Reg(Vec(iqSize, UInt(PhyRegIdxWidth.W))) 122 val freelistAllocPtr = Reg(Vec(iqSize, UInt(PhyRegIdxWidth.W))) 123 val roqIdx = Reg(Vec(iqSize, UInt(RoqIdxWidth.W))) 124 125 val instRdy = WireInit(VecInit(List.tabulate(iqSize)(i => src1Rdy(i) && src2Rdy(i) && src3Rdy(i)&& valid(i)))) 126 127 128 //tag enqueue 129 val iqEmty = !valid.asUInt.orR 130 val iqFull = valid.asUInt.andR 131 val iqAllowIn = !iqFull 132 io.enqCtrl.ready := iqAllowIn 133 134 //enqueue pointer 135 val emptySlot = ~valid.asUInt 136 val enqueueSelect = PriorityEncoder(emptySlot) 137 //assert(!(io.enqCtrl.valid && io.redirect.valid),"enqueue valid should be false when redirect valid") 138 XSError(io.enqCtrl.valid && io.redirect.valid,"enqueue valid should be false when redirect valid") 139 val srcEnqRdy = WireInit(VecInit(false.B, false.B, false.B)) 140 141 srcEnqRdy(0) := Mux(io.enqCtrl.bits.ctrl.src1Type =/= SrcType.reg , true.B ,io.enqCtrl.bits.src1State === SrcState.rdy) 142 srcEnqRdy(1) := Mux(io.enqCtrl.bits.ctrl.src2Type =/= SrcType.reg , true.B ,io.enqCtrl.bits.src2State === SrcState.rdy) 143 //TODO: 144 if(fuTypeInt != FuType.fmac.litValue()){ srcEnqRdy(2) := true.B} 145 else{srcEnqRdy(2) := Mux(io.enqCtrl.bits.ctrl.src3Type =/= SrcType.reg , true.B ,io.enqCtrl.bits.src3State === SrcState.rdy)} 146 147 when (io.enqCtrl.fire()) { 148 ctrlFlow(enqueueSelect) := io.enqCtrl.bits.cf 149 ctrlSig(enqueueSelect) := io.enqCtrl.bits.ctrl 150 brMask(enqueueSelect) := io.enqCtrl.bits.brMask 151 brTag(enqueueSelect) := io.enqCtrl.bits.brTag 152 validReg(enqueueSelect) := true.B 153 src1Rdy(enqueueSelect) := srcEnqRdy(0) 154 src2Rdy(enqueueSelect) := srcEnqRdy(1) 155 src3Rdy(enqueueSelect) := srcEnqRdy(2) 156 prfSrc1(enqueueSelect) := io.enqCtrl.bits.psrc1 157 prfSrc2(enqueueSelect) := io.enqCtrl.bits.psrc2 158 prfSrc3(enqueueSelect) := io.enqCtrl.bits.psrc3 159 prfDest(enqueueSelect) := io.enqCtrl.bits.pdest 160 oldPDest(enqueueSelect) := io.enqCtrl.bits.old_pdest 161 freelistAllocPtr(enqueueSelect) := io.enqCtrl.bits.freelistAllocPtr 162 roqIdx(enqueueSelect) := io.enqCtrl.bits.roqIdx 163 XSDebug("[IQ enq]: enqSelect:%d | s1Rd:%d s2Rd:%d s3Rd:%d\n",enqueueSelect.asUInt, 164 (io.enqCtrl.bits.src1State === SrcState.rdy), 165 (io.enqCtrl.bits.src2State === SrcState.rdy), 166 (io.enqCtrl.bits.src3State === SrcState.rdy)) 167 168 } 169 170 //Data Queue 171 val src1Data = Reg(Vec(iqSize, UInt(XLEN.W))) 172 val src2Data = Reg(Vec(iqSize, UInt(XLEN.W))) 173 val src3Data = Reg(Vec(iqSize, UInt(XLEN.W))) 174 175 176 val enqSelNext = RegNext(enqueueSelect) 177 val enqFireNext = RegNext(io.enqCtrl.fire()) 178 179 // Read RegFile 180 //Ready data will written at next cycle 181 when (enqFireNext) { 182 when(src1Rdy(enqSelNext)){src1Data(enqSelNext) := io.enqData.bits.src1} 183 when(src2Rdy(enqSelNext)){src2Data(enqSelNext) := io.enqData.bits.src2} 184 when(src3Rdy(enqSelNext)){src3Data(enqSelNext) := io.enqData.bits.src3} 185 } 186 187 XSDebug("[Reg info-ENQ] enqSelNext:%d | enqFireNext:%d \n",enqSelNext,enqFireNext) 188 XSDebug("[IQ content] valid vr vf| pc insruction | src1rdy src1 | src2Rdy src2 pdest \n") 189 for(i <- 0 to (iqSize -1)){ 190 val ins = ctrlFlow(i).instr 191 val pc = ctrlFlow(i).pc 192 XSDebug(valid(i),"[IQ content][%d] %d%d%d |%x %x| %x %x | %x %x | %d valid|\n",i.asUInt, valid(i), validReg(i), validWillFalse(i), pc,ins,src1Rdy(i), src1Data(i), src2Rdy(i), src2Data(i),prfDest(i)) 193 XSDebug(validReg(i) && validWillFalse(i),"[IQ content][%d] %d%d%d |%x %x| %x %x | %x %x | %d valid will be False|\n",i.asUInt, valid(i), validReg(i), validWillFalse(i),pc,ins, src1Rdy(i), src1Data(i), src2Rdy(i), src2Data(i),prfDest(i)) 194 XSDebug("[IQ content][%d] %d%d%d |%x %x| %x %x | %x %x | %d\n",i.asUInt, valid(i), validReg(i), validWillFalse(i),pc,ins, src1Rdy(i), src1Data(i), src2Rdy(i), src2Data(i),prfDest(i)) 195 } 196 // From Common Data Bus(wakeUpPort) 197 // chisel claims that firrtl will optimize Mux1H to and/or tree 198 // TODO: ignore ALU'cdb srcRdy, for byPass has done it 199 if(wakeupCnt > 0) { 200 val cdbValid = List.tabulate(wakeupCnt)(i => io.wakeUpPorts(i).valid) 201 val cdbData = List.tabulate(wakeupCnt)(i => io.wakeUpPorts(i).bits.data) 202 val cdbPdest = List.tabulate(wakeupCnt)(i => io.wakeUpPorts(i).bits.uop.pdest) 203 204 val srcNum = 3 205 val prfSrc = List(prfSrc1, prfSrc2, prfSrc3) 206 val srcRdy = List(src1Rdy, src2Rdy, src3Rdy) 207 val srcData = List(src1Data, src2Data, src3Data) 208 val srcHitVec = List.tabulate(srcNum)(k => 209 List.tabulate(iqSize)(i => 210 List.tabulate(wakeupCnt)(j => 211 (prfSrc(k)(i) === cdbPdest(j)) && cdbValid(j)))) 212 val srcHit = List.tabulate(srcNum)(k => 213 List.tabulate(iqSize)(i => 214 ParallelOR(srcHitVec(k)(i)).asBool())) 215 // VecInit(srcHitVec(k)(i)).asUInt.orR)) 216 for(k <- 0 until srcNum){ 217 for(i <- 0 until iqSize)( when (valid(i)) { 218 when(!srcRdy(k)(i) && srcHit(k)(i)) { 219 srcRdy(k)(i) := true.B 220 // srcData(k)(i) := Mux1H(srcHitVec(k)(i), cdbData) 221 srcData(k)(i) := ParallelMux(srcHitVec(k)(i) zip cdbData) 222 } 223 }) 224 } 225 // From byPass [speculative] (just for ALU to listen to other ALU's res, include itself) 226 // just need Tag(Ctrl). send out Tag when Tag is decided. other ALUIQ listen to them and decide Tag 227 // byPassUops is one cycle before byPassDatas 228 if (bypassCnt > 0) { 229 val bypassPdest = List.tabulate(bypassCnt)(i => io.bypassUops(i).bits.pdest) 230 val bypassValid = List.tabulate(bypassCnt)(i => io.bypassUops(i).valid) // may only need valid not fire() 231 val bypassData = List.tabulate(bypassCnt)(i => io.bypassData(i).bits.data) 232 val srcBpHitVec = List.tabulate(srcNum)(k => 233 List.tabulate(iqSize)(i => 234 List.tabulate(bypassCnt)(j => 235 (prfSrc(k)(i) === bypassPdest(j)) && bypassValid(j)))) 236 val srcBpHit = List.tabulate(srcNum)(k => 237 List.tabulate(iqSize)(i => 238 ParallelOR(srcBpHitVec(k)(i)).asBool())) 239 // VecInit(srcBpHitVec(k)(i)).asUInt.orR)) 240 val srcBpHitVecNext = List.tabulate(srcNum)(k => 241 List.tabulate(iqSize)(i => 242 List.tabulate(bypassCnt)(j => RegNext(srcBpHitVec(k)(i)(j))))) 243 val srcBpHitNext = List.tabulate(srcNum)(k => 244 List.tabulate(iqSize)(i => 245 RegNext(srcBpHit(k)(i)))) 246 val srcBpData = List.tabulate(srcNum)(k => 247 List.tabulate(iqSize)(i => 248 ParallelMux(srcBpHitVecNext(k)(i) zip bypassData))) 249 // Mux1H(srcBpHitVecNext(k)(i), bypassData))) 250 for(k <- 0 until srcNum){ 251 for(i <- 0 until iqSize){ when (valid(i)) { 252 when(valid(i) && !srcRdy(k)(i) && srcBpHit(k)(i)) { srcRdy(k)(i) := true.B } 253 when(srcBpHitNext(k)(i)) { srcData(k)(i) := srcBpData(k)(i)} 254 }} 255 } 256 257 // Enqueue Bypass 258 val enqBypass = WireInit(VecInit(false.B, false.B, false.B)) 259 val enqBypassHitVec = List(List.tabulate(bypassCnt)(j => io.enqCtrl.bits.psrc1 === bypassPdest(j) && bypassValid(j) && io.enqCtrl.fire()), 260 List.tabulate(bypassCnt)(j => io.enqCtrl.bits.psrc2 === bypassPdest(j) && bypassValid(j) && io.enqCtrl.fire()), 261 List.tabulate(bypassCnt)(j => io.enqCtrl.bits.psrc3 === bypassPdest(j) && bypassValid(j) && io.enqCtrl.fire())) 262 val enqBypassHitVecNext = enqBypassHitVec.map(i => i.map(j => RegNext(j))) 263 enqBypass(0) := ParallelOR(enqBypassHitVec(0)) 264 enqBypass(1) := ParallelOR(enqBypassHitVec(1)) 265 enqBypass(2) := ParallelOR(enqBypassHitVec(2)) 266 when(enqBypass(0)) { src1Rdy(enqueueSelect) := true.B } 267 when(enqBypass(1)) { src2Rdy(enqueueSelect) := true.B } 268 when(enqBypass(2)) { src3Rdy(enqueueSelect) := true.B } 269 when(RegNext(enqBypass(0))) { src1Data(enqSelNext) := ParallelMux(enqBypassHitVecNext(0) zip bypassData)} 270 when(RegNext(enqBypass(1))) { src2Data(enqSelNext) := ParallelMux(enqBypassHitVecNext(1) zip bypassData)} 271 when(RegNext(enqBypass(2))) { src3Data(enqSelNext) := ParallelMux(enqBypassHitVecNext(2) zip bypassData)} 272 } 273 274 } 275 276 277 //--------------------------------------------------------- 278 // Select Circuit 279 //--------------------------------------------------------- 280 val selVec = List.tabulate(iqSize){ i => 281 Wire(new CmpInputBundle).apply(instRdy(i),roqIdx(i),i.U) 282 } 283 val selResult = ParallelSel(selVec) 284 XSDebug("[Sel Result] ResReady:%d || ResultId:%d\n",selResult.instRdy,selResult.iqIdx.asUInt) 285 //--------------------------------------------------------- 286 // Redirect Logic 287 //--------------------------------------------------------- 288 val expRedirect = io.redirect.valid && io.redirect.bits.isException 289 val brRedirect = io.redirect.valid && !io.redirect.bits.isException 290 291 List.tabulate(iqSize)( i => 292 when(brRedirect && (UIntToOH(io.redirect.bits.brTag) & brMask(i)).orR && validReg(i) ){ 293 validReg(i) := false.B 294 validWillFalse(i) := true.B 295 296 } .elsewhen(expRedirect) { 297 validReg(i) := false.B 298 validWillFalse(i) := true.B 299 } 300 ) 301 //--------------------------------------------------------- 302 // Dequeue Logic 303 //--------------------------------------------------------- 304 //hold the sel-index to wait for data 305 val selInstIdx = RegInit(0.U(iqIdxWidth.W)) 306 val selInstRdy = RegInit(false.B) 307 308 //issue the select instruction 309 val dequeueSelect = Wire(UInt(iqIdxWidth.W)) 310 dequeueSelect := selInstIdx 311 312 val brRedirectMaskMatch = (UIntToOH(io.redirect.bits.brTag) & brMask(dequeueSelect)).orR 313 val IQreadyGo = selInstRdy && !expRedirect && (!brRedirect || !brRedirectMaskMatch) 314 315 io.deq.valid := IQreadyGo 316 317 io.deq.bits.uop.cf := ctrlFlow(dequeueSelect) 318 io.deq.bits.uop.ctrl := ctrlSig(dequeueSelect) 319 io.deq.bits.uop.brMask := brMask(dequeueSelect) 320 io.deq.bits.uop.brTag := brTag(dequeueSelect) 321 322 io.deq.bits.uop.psrc1 := prfSrc1(dequeueSelect) 323 io.deq.bits.uop.psrc2 := prfSrc2(dequeueSelect) 324 io.deq.bits.uop.psrc3 := prfSrc3(dequeueSelect) 325 io.deq.bits.uop.pdest := prfDest(dequeueSelect) 326 io.deq.bits.uop.old_pdest := oldPDest(dequeueSelect) 327 io.deq.bits.uop.src1State := SrcState.rdy 328 io.deq.bits.uop.src2State := SrcState.rdy 329 io.deq.bits.uop.src3State := SrcState.rdy 330 io.deq.bits.uop.freelistAllocPtr := freelistAllocPtr(dequeueSelect) 331 io.deq.bits.uop.roqIdx := roqIdx(dequeueSelect) 332 333 io.deq.bits.src1 := src1Data(dequeueSelect) 334 io.deq.bits.src2 := src2Data(dequeueSelect) 335 io.deq.bits.src3 := src3Data(dequeueSelect) 336 337 XSDebug("[Reg Info-Sel] selInstRdy:%d || selIdx:%d\n",selInstRdy,selInstIdx.asUInt) 338 XSDebug(IQreadyGo,"[IQ dequeue] **dequeue fire:%d** roqIdx:%d dequeueSel:%d | src1Rd:%d src1:%d | src2Rd:%d src2:%d\n", io.deq.fire(), io.deq.bits.uop.roqIdx, dequeueSelect.asUInt, 339 (io.deq.bits.uop.src1State === SrcState.rdy), io.deq.bits.uop.psrc1, 340 (io.deq.bits.uop.src2State === SrcState.rdy), io.deq.bits.uop.psrc2 341 ) 342 343 //update the index register of instruction that can be issue, unless function unit not allow in 344 //then the issue will be stopped to wait the function unit 345 //clear the validBit of dequeued instruction in issuequeue 346 when(io.deq.fire()){ 347 validReg(dequeueSelect) := false.B 348 validWillFalse(dequeueSelect) := true.B 349 } 350 351 val selRegflush = expRedirect || (brRedirect && brRedirectMaskMatch) 352 353 selInstRdy := Mux(selRegflush,false.B,selResult.instRdy) 354 selInstIdx := Mux(selRegflush,0.U,selResult.iqIdx) 355 // SelectedUop (bypass / speculative) 356 if(useBypass) { 357 assert(fixedDelay==1) // only support fixedDelay is 1 now 358 def DelayPipe[T <: Data](a: T, delay: Int = 0) = { 359 // println(delay) 360 if(delay == 0) a 361 else { 362 val storage = Wire(VecInit(Seq.fill(delay+1)(a))) 363 // storage(0) := a 364 for(i <- 1 until delay) { 365 storage(i) := RegNext(storage(i-1)) 366 } 367 storage(delay) 368 } 369 } 370 val sel = io.selectedUop 371 val selIQIdx = selResult.iqIdx 372 val delayPipe = DelayPipe(VecInit(selResult.instRdy, prfDest(selIQIdx)), fixedDelay-1) 373 sel.bits := DontCare 374 sel.bits.pdest := delayPipe(fixedDelay-1)(1) 375 } 376} 377