xref: /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala (revision 596af5d2a6f4c7392bcb130e921b5de333b0cd93) 
1package xiangshan.backend.issue
2
3import org.chipsalliance.cde.config.Parameters
4import chisel3._
5import chisel3.util._
6import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
7import utility.{GTimer, HasCircularQueuePtrHelper, SelectOne}
8import utils._
9import xiangshan._
10import xiangshan.backend.Bundles._
11import xiangshan.backend.issue.EntryBundles._
12import xiangshan.backend.decode.{ImmUnion, Imm_LUI_LOAD}
13import xiangshan.backend.datapath.DataConfig._
14import xiangshan.backend.datapath.DataSource
15import xiangshan.backend.fu.{FuConfig, FuType}
16import xiangshan.mem.{MemWaitUpdateReq, SqPtr, LqPtr}
17import xiangshan.backend.rob.RobPtr
18import xiangshan.backend.datapath.NewPipelineConnect
19
20class IssueQueue(params: IssueBlockParams)(implicit p: Parameters) extends LazyModule with HasXSParameter {
21  override def shouldBeInlined: Boolean = false
22
23  implicit val iqParams = params
24  lazy val module: IssueQueueImp = iqParams.schdType match {
25    case IntScheduler() => new IssueQueueIntImp(this)
26    case VfScheduler() => new IssueQueueVfImp(this)
27    case MemScheduler() =>
28      if (iqParams.StdCnt == 0 && !iqParams.isVecMemIQ) new IssueQueueMemAddrImp(this)
29      else if (iqParams.isVecMemIQ) new IssueQueueVecMemImp(this)
30      else new IssueQueueIntImp(this)
31    case _ => null
32  }
33}
34
35class IssueQueueStatusBundle(numEnq: Int, numEntries: Int) extends Bundle {
36  val empty = Output(Bool())
37  val full = Output(Bool())
38  val validCnt = Output(UInt(log2Ceil(numEntries).W))
39  val leftVec = Output(Vec(numEnq + 1, Bool()))
40}
41
42class IssueQueueDeqRespBundle(implicit p:Parameters, params: IssueBlockParams) extends EntryDeqRespBundle
43
44class IssueQueueIO()(implicit p: Parameters, params: IssueBlockParams) extends XSBundle {
45  // Inputs
46  val flush = Flipped(ValidIO(new Redirect))
47  val enq = Vec(params.numEnq, Flipped(DecoupledIO(new DynInst)))
48
49  val og0Resp = Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle)))
50  val og1Resp = Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle)))
51  val finalIssueResp = OptionWrapper(params.LdExuCnt > 0, Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle))))
52  val memAddrIssueResp = OptionWrapper(params.LdExuCnt > 0, Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle))))
53  val wbBusyTableRead = Input(params.genWbFuBusyTableReadBundle())
54  val wbBusyTableWrite = Output(params.genWbFuBusyTableWriteBundle())
55  val wakeupFromWB: MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = Flipped(params.genWBWakeUpSinkValidBundle)
56  val wakeupFromIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(params.genIQWakeUpSinkValidBundle)
57  val og0Cancel = Input(ExuOH(backendParams.numExu))
58  val og1Cancel = Input(ExuOH(backendParams.numExu))
59  val ldCancel = Vec(backendParams.LduCnt + backendParams.HyuCnt, Flipped(new LoadCancelIO))
60
61  // Outputs
62  val wakeupToIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = params.genIQWakeUpSourceValidBundle
63  val status = Output(new IssueQueueStatusBundle(params.numEnq, params.numEntries))
64  // val statusNext = Output(new IssueQueueStatusBundle(params.numEnq))
65
66  val deqDelay: MixedVec[DecoupledIO[IssueQueueIssueBundle]] = params.genIssueDecoupledBundle// = deq.cloneType
67  def allWakeUp = wakeupFromWB ++ wakeupFromIQ
68}
69
70class IssueQueueImp(override val wrapper: IssueQueue)(implicit p: Parameters, val params: IssueBlockParams)
71  extends LazyModuleImp(wrapper)
72  with HasXSParameter {
73
74  override def desiredName: String = s"${params.getIQName}"
75
76  println(s"[IssueQueueImp] ${params.getIQName} wakeupFromWB(${io.wakeupFromWB.size}), " +
77    s"wakeup exu in(${params.wakeUpInExuSources.size}): ${params.wakeUpInExuSources.map(_.name).mkString("{",",","}")}, " +
78    s"wakeup exu out(${params.wakeUpOutExuSources.size}): ${params.wakeUpOutExuSources.map(_.name).mkString("{",",","}")}, " +
79    s"numEntries: ${params.numEntries}, numRegSrc: ${params.numRegSrc}")
80
81  require(params.numExu <= 2, "IssueQueue has not supported more than 2 deq ports")
82  val deqFuCfgs     : Seq[Seq[FuConfig]] = params.exuBlockParams.map(_.fuConfigs)
83  val allDeqFuCfgs  : Seq[FuConfig] = params.exuBlockParams.flatMap(_.fuConfigs)
84  val fuCfgsCnt     : Map[FuConfig, Int] = allDeqFuCfgs.groupBy(x => x).map { case (cfg, cfgSeq) => (cfg, cfgSeq.length) }
85  val commonFuCfgs  : Seq[FuConfig] = fuCfgsCnt.filter(_._2 > 1).keys.toSeq
86  val fuLatencyMaps : Seq[Map[FuType.OHType, Int]] = params.exuBlockParams.map(x => x.fuLatencyMap)
87
88  println(s"[IssueQueueImp] ${params.getIQName} fuLatencyMaps: ${fuLatencyMaps}")
89  println(s"[IssueQueueImp] ${params.getIQName} commonFuCfgs: ${commonFuCfgs.map(_.name)}")
90  lazy val io = IO(new IssueQueueIO())
91  // Modules
92
93  val entries = Module(new Entries)
94  val fuBusyTableWrite = params.exuBlockParams.map { case x => OptionWrapper(x.latencyValMax > 0, Module(new FuBusyTableWrite(x.fuLatencyMap))) }
95  val fuBusyTableRead = params.exuBlockParams.map { case x => OptionWrapper(x.latencyValMax > 0, Module(new FuBusyTableRead(x.fuLatencyMap))) }
96  val intWbBusyTableWrite = params.exuBlockParams.map { case x => OptionWrapper(x.intLatencyCertain, Module(new FuBusyTableWrite(x.intFuLatencyMap))) }
97  val intWbBusyTableRead = params.exuBlockParams.map { case x => OptionWrapper(x.intLatencyCertain, Module(new FuBusyTableRead(x.intFuLatencyMap))) }
98  val vfWbBusyTableWrite = params.exuBlockParams.map { case x => OptionWrapper(x.vfLatencyCertain, Module(new FuBusyTableWrite(x.vfFuLatencyMap))) }
99  val vfWbBusyTableRead = params.exuBlockParams.map { case x => OptionWrapper(x.vfLatencyCertain, Module(new FuBusyTableRead(x.vfFuLatencyMap))) }
100
101  class WakeupQueueFlush extends Bundle {
102    val redirect = ValidIO(new Redirect)
103    val ldCancel = Vec(backendParams.LduCnt + backendParams.HyuCnt, new LoadCancelIO)
104    val og0Fail = Output(Bool())
105    val og1Fail = Output(Bool())
106  }
107
108  private def flushFunc(exuInput: ExuInput, flush: WakeupQueueFlush, stage: Int): Bool = {
109    val redirectFlush = exuInput.robIdx.needFlush(flush.redirect)
110    val loadDependencyFlush = LoadShouldCancel(exuInput.loadDependency, flush.ldCancel)
111    val ogFailFlush = stage match {
112      case 1 => flush.og0Fail
113      case 2 => flush.og1Fail
114      case _ => false.B
115    }
116    redirectFlush || loadDependencyFlush || ogFailFlush
117  }
118
119  private def modificationFunc(exuInput: ExuInput): ExuInput = {
120    val newExuInput = WireDefault(exuInput)
121    newExuInput.loadDependency match {
122      case Some(deps) => deps.zip(exuInput.loadDependency.get).foreach(x => x._1 := x._2 << 1)
123      case None =>
124    }
125    newExuInput
126  }
127
128  private def lastConnectFunc(exuInput: ExuInput, newInput: ExuInput): ExuInput = {
129    val lastExuInput = WireDefault(exuInput)
130    val newExuInput = WireDefault(newInput)
131    newExuInput.elements.foreach { case (name, data) =>
132      if (lastExuInput.elements.contains(name)) {
133        data := lastExuInput.elements(name)
134      }
135    }
136    if (newExuInput.pdestCopy.nonEmpty && !lastExuInput.pdestCopy.nonEmpty) {
137      newExuInput.pdestCopy.get.foreach(_ := lastExuInput.pdest)
138    }
139    if (newExuInput.rfWenCopy.nonEmpty && !lastExuInput.rfWenCopy.nonEmpty) {
140      newExuInput.rfWenCopy.get.foreach(_ := lastExuInput.rfWen.get)
141    }
142    if (newExuInput.fpWenCopy.nonEmpty && !lastExuInput.fpWenCopy.nonEmpty) {
143      newExuInput.fpWenCopy.get.foreach(_ := lastExuInput.fpWen.get)
144    }
145    if (newExuInput.vecWenCopy.nonEmpty && !lastExuInput.vecWenCopy.nonEmpty) {
146      newExuInput.vecWenCopy.get.foreach(_ := lastExuInput.rfWen.get)
147    }
148    if (newExuInput.loadDependencyCopy.nonEmpty && !lastExuInput.loadDependencyCopy.nonEmpty) {
149      newExuInput.loadDependencyCopy.get.foreach(_ := lastExuInput.loadDependency.get)
150    }
151    newExuInput
152  }
153
154  val wakeUpQueues: Seq[Option[MultiWakeupQueue[ExuInput, WakeupQueueFlush]]] = params.exuBlockParams.map { x =>
155    OptionWrapper(x.isIQWakeUpSource && !x.hasLoadExu, Module(
156      new MultiWakeupQueue(new ExuInput(x), new ExuInput(x, x.copyWakeupOut, x.copyNum), new WakeupQueueFlush, x.fuLatancySet, flushFunc, modificationFunc, lastConnectFunc)
157    ))
158  }
159  val deqBeforeDly = Wire(params.genIssueDecoupledBundle)
160
161  val intWbBusyTableIn = io.wbBusyTableRead.map(_.intWbBusyTable)
162  val vfWbBusyTableIn = io.wbBusyTableRead.map(_.vfWbBusyTable)
163  val intWbBusyTableOut = io.wbBusyTableWrite.map(_.intWbBusyTable)
164  val vfWbBusyTableOut = io.wbBusyTableWrite.map(_.vfWbBusyTable)
165  val intDeqRespSetOut = io.wbBusyTableWrite.map(_.intDeqRespSet)
166  val vfDeqRespSetOut = io.wbBusyTableWrite.map(_.vfDeqRespSet)
167  val fuBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W)))
168  val intWbBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W)))
169  val vfWbBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W)))
170  val s0_enqValidVec = io.enq.map(_.valid)
171  val s0_enqSelValidVec = Wire(Vec(params.numEnq, Bool()))
172  val s0_enqNotFlush = !io.flush.valid
173  val s0_enqBits = WireInit(VecInit(io.enq.map(_.bits)))
174  val s0_doEnqSelValidVec = s0_enqSelValidVec.map(_ && s0_enqNotFlush) //enqValid && notFlush && enqReady
175
176
177  val finalDeqSelValidVec = Wire(Vec(params.numDeq, Bool()))
178  val finalDeqSelOHVec    = Wire(Vec(params.numDeq, UInt(params.numEntries.W)))
179
180  val validVec = VecInit(entries.io.valid.asBools)
181  val canIssueVec = VecInit(entries.io.canIssue.asBools)
182  dontTouch(canIssueVec)
183  val deqFirstIssueVec = entries.io.isFirstIssue
184
185  val dataSources: Vec[Vec[DataSource]] = entries.io.dataSources
186  val finalDataSources: Vec[Vec[DataSource]] = VecInit(finalDeqSelOHVec.map(oh => Mux1H(oh, dataSources)))
187  // (entryIdx)(srcIdx)(exuIdx)
188  val wakeUpL1ExuOH: Option[Vec[Vec[UInt]]] = entries.io.srcWakeUpL1ExuOH
189  val srcTimer: Option[Vec[Vec[UInt]]] = entries.io.srcTimer
190
191  // (deqIdx)(srcIdx)(exuIdx)
192  val finalWakeUpL1ExuOH: Option[Vec[Vec[UInt]]] = wakeUpL1ExuOH.map(x => VecInit(finalDeqSelOHVec.map(oh => Mux1H(oh, x))))
193  val finalSrcTimer = srcTimer.map(x => VecInit(finalDeqSelOHVec.map(oh => Mux1H(oh, x))))
194
195  val fuTypeVec = Wire(Vec(params.numEntries, FuType()))
196  val transEntryDeqVec = Wire(Vec(params.numEnq, ValidIO(new EntryBundle)))
197  val deqEntryVec = Wire(Vec(params.numDeq, ValidIO(new EntryBundle)))
198  val transSelVec = Wire(Vec(params.numEnq, UInt((params.numEntries-params.numEnq).W)))
199  val canIssueMergeAllBusy = Wire(Vec(params.numDeq, UInt(params.numEntries.W)))
200  val deqCanIssue = Wire(Vec(params.numDeq, UInt(params.numEntries.W)))
201
202  val enqEntryOldestSel = Wire(Vec(params.numDeq, ValidIO(UInt(params.numEnq.W))))
203  val othersEntryOldestSel = Wire(Vec(params.numDeq, ValidIO(UInt((params.numEntries - params.numEnq).W))))
204  val deqSelValidVec = Wire(Vec(params.numDeq, Bool()))
205  val deqSelOHVec    = Wire(Vec(params.numDeq, UInt(params.numEntries.W)))
206  val cancelDeqVec = Wire(Vec(params.numDeq, Bool()))
207
208  val subDeqSelValidVec = OptionWrapper(params.deqFuSame, Wire(Vec(params.numDeq, Bool())))
209  val subDeqSelOHVec = OptionWrapper(params.deqFuSame, Wire(Vec(params.numDeq, UInt(params.numEntries.W))))
210  val subDeqRequest = OptionWrapper(params.deqFuSame, Wire(UInt(params.numEntries.W)))
211
212  /**
213    * Connection of [[entries]]
214    */
215  entries.io match { case entriesIO: EntriesIO =>
216    entriesIO.flush                                             := io.flush
217    entriesIO.enq.zipWithIndex.foreach { case (enq, enqIdx) =>
218      enq.valid                                                 := s0_doEnqSelValidVec(enqIdx)
219      enq.bits.status.robIdx                                    := s0_enqBits(enqIdx).robIdx
220      enq.bits.status.fuType                                    := IQFuType.readFuType(VecInit(s0_enqBits(enqIdx).fuType.asBools), params.getFuCfgs.map(_.fuType))
221      val numLsrc = s0_enqBits(enqIdx).srcType.size.min(enq.bits.status.srcStatus.map(_.srcType).size)
222      for(j <- 0 until numLsrc) {
223        enq.bits.status.srcStatus(j).psrc                       := s0_enqBits(enqIdx).psrc(j)
224        enq.bits.status.srcStatus(j).srcType                    := s0_enqBits(enqIdx).srcType(j)
225        enq.bits.status.srcStatus(j).srcState                   := s0_enqBits(enqIdx).srcState(j) & !LoadShouldCancel(Some(s0_enqBits(enqIdx).srcLoadDependency(j)), io.ldCancel)
226        enq.bits.status.srcStatus(j).dataSources.value          := DataSource.reg
227        if(params.hasIQWakeUp) {
228          enq.bits.status.srcStatus(j).srcTimer.get             := 0.U(3.W)
229          enq.bits.status.srcStatus(j).srcWakeUpL1ExuOH.get     := 0.U.asTypeOf(ExuVec())
230          enq.bits.status.srcStatus(j).srcLoadDependency.get    := VecInit(s0_enqBits(enqIdx).srcLoadDependency(j).map(x => x(x.getWidth - 2, 0) << 1))
231        }
232      }
233      enq.bits.status.blocked                                   := false.B
234      enq.bits.status.issued                                    := false.B
235      enq.bits.status.firstIssue                                := false.B
236      enq.bits.status.issueTimer                                := "b10".U
237      enq.bits.status.deqPortIdx                                := 0.U
238      if (params.isVecMemIQ) {
239        enq.bits.status.vecMem.get.uopIdx := s0_enqBits(enqIdx).uopIdx
240      }
241      if (params.inIntSchd && params.AluCnt > 0) {
242        // dirty code for lui+addi(w) fusion
243        val isLuiAddiFusion = s0_enqBits(enqIdx).isLUI32
244        val luiImm = Cat(s0_enqBits(enqIdx).lsrc(1), s0_enqBits(enqIdx).lsrc(0), s0_enqBits(enqIdx).imm(ImmUnion.maxLen - 1, 0))
245        enq.bits.imm.foreach(_ := Mux(isLuiAddiFusion, ImmUnion.LUI32.toImm32(luiImm), s0_enqBits(enqIdx).imm))
246      }
247      else if (params.inMemSchd && params.LduCnt > 0) {
248        // dirty code for fused_lui_load
249        val isLuiLoadFusion = SrcType.isNotReg(s0_enqBits(enqIdx).srcType(0)) && FuType.isLoad(s0_enqBits(enqIdx).fuType)
250        enq.bits.imm.foreach(_ := Mux(isLuiLoadFusion, Imm_LUI_LOAD().getLuiImm(s0_enqBits(enqIdx)), s0_enqBits(enqIdx).imm))
251      }
252      else {
253        enq.bits.imm.foreach(_ := s0_enqBits(enqIdx).imm)
254      }
255      enq.bits.payload                                          := s0_enqBits(enqIdx)
256    }
257    entriesIO.og0Resp.zipWithIndex.foreach { case (og0Resp, i) =>
258      og0Resp.valid                                             := io.og0Resp(i).valid
259      og0Resp.bits.robIdx                                       := io.og0Resp(i).bits.robIdx
260      og0Resp.bits.uopIdx.foreach(_                             := io.og0Resp(i).bits.uopIdx.get)
261      og0Resp.bits.dataInvalidSqIdx                             := io.og0Resp(i).bits.dataInvalidSqIdx
262      og0Resp.bits.respType                                     := io.og0Resp(i).bits.respType
263      og0Resp.bits.rfWen                                        := io.og0Resp(i).bits.rfWen
264      og0Resp.bits.fuType                                       := io.og0Resp(i).bits.fuType
265    }
266    entriesIO.og1Resp.zipWithIndex.foreach { case (og1Resp, i) =>
267      og1Resp.valid                                             := io.og1Resp(i).valid
268      og1Resp.bits.robIdx                                       := io.og1Resp(i).bits.robIdx
269      og1Resp.bits.uopIdx.foreach(_                             := io.og1Resp(i).bits.uopIdx.get)
270      og1Resp.bits.dataInvalidSqIdx                             := io.og1Resp(i).bits.dataInvalidSqIdx
271      og1Resp.bits.respType                                     := io.og1Resp(i).bits.respType
272      og1Resp.bits.rfWen                                        := io.og1Resp(i).bits.rfWen
273      og1Resp.bits.fuType                                       := io.og1Resp(i).bits.fuType
274    }
275    entriesIO.finalIssueResp.foreach(_.zipWithIndex.foreach { case (finalIssueResp, i) =>
276      finalIssueResp                                            := io.finalIssueResp.get(i)
277    })
278    for(deqIdx <- 0 until params.numDeq) {
279      entriesIO.deqReady(deqIdx)                                := deqBeforeDly(deqIdx).ready
280      entriesIO.deqSelOH(deqIdx).valid                          := deqSelValidVec(deqIdx)
281      entriesIO.deqSelOH(deqIdx).bits                           := deqSelOHVec(deqIdx)
282      entriesIO.enqEntryOldestSel(deqIdx)                       := enqEntryOldestSel(deqIdx)
283      entriesIO.othersEntryOldestSel(deqIdx)                    := othersEntryOldestSel(deqIdx)
284      entriesIO.subDeqRequest.foreach(_(deqIdx)                 := subDeqRequest.get)
285      entriesIO.subDeqSelOH.foreach(_(deqIdx)                   := subDeqSelOHVec.get(deqIdx))
286    }
287    entriesIO.wakeUpFromWB                                      := io.wakeupFromWB
288    entriesIO.wakeUpFromIQ                                      := io.wakeupFromIQ
289    entriesIO.og0Cancel                                         := io.og0Cancel
290    entriesIO.og1Cancel                                         := io.og1Cancel
291    entriesIO.ldCancel                                          := io.ldCancel
292    //output
293    transEntryDeqVec                                            := entriesIO.transEntryDeqVec
294    transSelVec                                                 := entriesIO.transSelVec
295    fuTypeVec                                                   := entriesIO.fuType
296    deqEntryVec                                                 := entriesIO.deqEntry
297    cancelDeqVec                                                := entriesIO.cancelDeqVec
298  }
299
300
301  s0_enqSelValidVec := s0_enqValidVec.zip(io.enq).map{ case (enqValid, enq) => enqValid && enq.ready}
302
303  protected val commonAccept: UInt = Cat(fuTypeVec.map(fuType =>
304    FuType.FuTypeOrR(fuType, commonFuCfgs.map(_.fuType))
305  ).reverse)
306
307  // if deq port can accept the uop
308  protected val canAcceptVec: Seq[UInt] = deqFuCfgs.map { fuCfgs: Seq[FuConfig] =>
309    Cat(fuTypeVec.map(fuType =>
310      FuType.FuTypeOrR(fuType, fuCfgs.map(_.fuType))
311    ).reverse)
312  }
313
314  protected val deqCanAcceptVec: Seq[IndexedSeq[Bool]] = deqFuCfgs.map { fuCfgs: Seq[FuConfig] =>
315    fuTypeVec.map(fuType =>
316      FuType.FuTypeOrR(fuType, fuCfgs.map(_.fuType)))
317  }
318
319  canIssueMergeAllBusy.zipWithIndex.foreach { case (merge, i) =>
320    val mergeFuBusy = {
321      if (fuBusyTableWrite(i).nonEmpty) canIssueVec.asUInt & (~fuBusyTableMask(i))
322      else canIssueVec.asUInt
323    }
324    val mergeIntWbBusy = {
325      if (intWbBusyTableRead(i).nonEmpty) mergeFuBusy & (~intWbBusyTableMask(i))
326      else mergeFuBusy
327    }
328    val mergeVfWbBusy = {
329      if (vfWbBusyTableRead(i).nonEmpty) mergeIntWbBusy & (~vfWbBusyTableMask(i))
330      else mergeIntWbBusy
331    }
332    merge := mergeVfWbBusy
333  }
334
335  deqCanIssue.zipWithIndex.foreach { case (req, i) =>
336    req := canIssueMergeAllBusy(i) & VecInit(deqCanAcceptVec(i)).asUInt
337  }
338  dontTouch(fuTypeVec)
339  dontTouch(canIssueMergeAllBusy)
340  dontTouch(deqCanIssue)
341
342  if (params.numDeq == 2) {
343    require(params.deqFuSame || params.deqFuDiff, "The 2 deq ports need to be identical or completely different")
344  }
345
346  if (params.numDeq == 2 && params.deqFuSame) {
347    enqEntryOldestSel := DontCare
348
349    othersEntryOldestSel(0) := AgeDetector(numEntries = params.numEntries - params.numEnq,
350      enq = VecInit(transEntryDeqVec.zip(transSelVec).map{ case (transEntry, transSel) => Fill(params.numEntries-params.numEnq, transEntry.valid) & transSel }),
351      canIssue = canIssueVec.asUInt(params.numEntries-1, params.numEnq)
352    )
353    othersEntryOldestSel(1) := DontCare
354
355    subDeqRequest.get := canIssueVec.asUInt & ~Cat(othersEntryOldestSel(0).bits, 0.U((params.numEnq).W))
356
357    val subDeqPolicy = Module(new DeqPolicy())
358    subDeqPolicy.io.request := subDeqRequest.get
359    subDeqSelValidVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => oh.valid)
360    subDeqSelOHVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => oh.bits)
361
362    deqSelValidVec(0) := othersEntryOldestSel(0).valid || subDeqSelValidVec.get(1)
363    deqSelValidVec(1) := subDeqSelValidVec.get(0)
364    deqSelOHVec(0) := Mux(othersEntryOldestSel(0).valid,
365                          Cat(othersEntryOldestSel(0).bits, 0.U((params.numEnq).W)),
366                          subDeqSelOHVec.get(1)) & canIssueMergeAllBusy(0)
367    deqSelOHVec(1) := subDeqSelOHVec.get(0) & canIssueMergeAllBusy(1)
368
369    finalDeqSelValidVec.zip(finalDeqSelOHVec).zip(deqSelValidVec).zip(deqSelOHVec).zipWithIndex.foreach { case ((((selValid, selOH), deqValid), deqOH), i) =>
370      selValid := deqValid && deqOH.orR && deqBeforeDly(i).ready
371      selOH := deqOH
372    }
373  }
374  else {
375    enqEntryOldestSel := NewAgeDetector(numEntries = params.numEnq,
376      enq = VecInit(s0_doEnqSelValidVec),
377      canIssue = VecInit(deqCanIssue.map(_(params.numEnq-1, 0)))
378    )
379
380    othersEntryOldestSel := AgeDetector(numEntries = params.numEntries - params.numEnq,
381      enq = VecInit(transEntryDeqVec.zip(transSelVec).map{ case (transEntry, transSel) => Fill(params.numEntries-params.numEnq, transEntry.valid) & transSel }),
382      canIssue = VecInit(deqCanIssue.map(_(params.numEntries-1, params.numEnq)))
383    )
384
385    deqSelValidVec.zip(deqSelOHVec).zipWithIndex.foreach { case ((selValid, selOH), i) =>
386      if (params.exuBlockParams(i).fuConfigs.contains(FuConfig.FakeHystaCfg)) {
387        selValid := false.B
388        selOH := 0.U.asTypeOf(selOH)
389      } else {
390        selValid := othersEntryOldestSel(i).valid || enqEntryOldestSel(i).valid
391        selOH := Cat(othersEntryOldestSel(i).bits, Fill(params.numEnq, enqEntryOldestSel(i).valid && !othersEntryOldestSel(i).valid) & enqEntryOldestSel(i).bits)
392      }
393    }
394
395    finalDeqSelValidVec.zip(finalDeqSelOHVec).zip(deqSelValidVec).zip(deqSelOHVec).zipWithIndex.foreach { case ((((selValid, selOH), deqValid), deqOH), i) =>
396      selValid := deqValid && deqBeforeDly(i).ready
397      selOH := deqOH
398    }
399  }
400
401  val toBusyTableDeqResp = Wire(Vec(params.numDeq, ValidIO(new IssueQueueDeqRespBundle)))
402
403  toBusyTableDeqResp.zipWithIndex.foreach { case (deqResp, i) =>
404    deqResp.valid := finalDeqSelValidVec(i)
405    deqResp.bits.respType := RSFeedbackType.issueSuccess
406    deqResp.bits.robIdx := DontCare
407    deqResp.bits.dataInvalidSqIdx := DontCare
408    deqResp.bits.rfWen := DontCare
409    deqResp.bits.fuType := deqBeforeDly(i).bits.common.fuType
410    deqResp.bits.uopIdx.foreach(_ := DontCare)
411  }
412
413  //fuBusyTable
414  fuBusyTableWrite.zip(fuBusyTableRead).zipWithIndex.foreach { case ((busyTableWrite: Option[FuBusyTableWrite], busyTableRead: Option[FuBusyTableRead]), i) =>
415    if(busyTableWrite.nonEmpty) {
416      val btwr = busyTableWrite.get
417      val btrd = busyTableRead.get
418      btwr.io.in.deqResp := toBusyTableDeqResp(i)
419      btwr.io.in.og0Resp := io.og0Resp(i)
420      btwr.io.in.og1Resp := io.og1Resp(i)
421      btrd.io.in.fuBusyTable := btwr.io.out.fuBusyTable
422      btrd.io.in.fuTypeRegVec := fuTypeVec
423      fuBusyTableMask(i) := btrd.io.out.fuBusyTableMask
424    }
425    else {
426      fuBusyTableMask(i) := 0.U(params.numEntries.W)
427    }
428  }
429
430  //wbfuBusyTable write
431  intWbBusyTableWrite.zip(intWbBusyTableOut).zip(intDeqRespSetOut).zipWithIndex.foreach { case (((busyTableWrite: Option[FuBusyTableWrite], busyTable: Option[UInt]), deqResp), i) =>
432    if(busyTableWrite.nonEmpty) {
433      val btwr = busyTableWrite.get
434      val bt = busyTable.get
435      val dq = deqResp.get
436      btwr.io.in.deqResp := toBusyTableDeqResp(i)
437      btwr.io.in.og0Resp := io.og0Resp(i)
438      btwr.io.in.og1Resp := io.og1Resp(i)
439      bt := btwr.io.out.fuBusyTable
440      dq := btwr.io.out.deqRespSet
441    }
442  }
443
444  vfWbBusyTableWrite.zip(vfWbBusyTableOut).zip(vfDeqRespSetOut).zipWithIndex.foreach { case (((busyTableWrite: Option[FuBusyTableWrite], busyTable: Option[UInt]), deqResp), i) =>
445    if (busyTableWrite.nonEmpty) {
446      val btwr = busyTableWrite.get
447      val bt = busyTable.get
448      val dq = deqResp.get
449      btwr.io.in.deqResp := toBusyTableDeqResp(i)
450      btwr.io.in.og0Resp := io.og0Resp(i)
451      btwr.io.in.og1Resp := io.og1Resp(i)
452      bt := btwr.io.out.fuBusyTable
453      dq := btwr.io.out.deqRespSet
454    }
455  }
456
457  //wbfuBusyTable read
458  intWbBusyTableRead.zip(intWbBusyTableIn).zipWithIndex.foreach { case ((busyTableRead: Option[FuBusyTableRead], busyTable: Option[UInt]), i) =>
459    if(busyTableRead.nonEmpty) {
460      val btrd = busyTableRead.get
461      val bt = busyTable.get
462      btrd.io.in.fuBusyTable := bt
463      btrd.io.in.fuTypeRegVec := fuTypeVec
464      intWbBusyTableMask(i) := btrd.io.out.fuBusyTableMask
465    }
466    else {
467      intWbBusyTableMask(i) := 0.U(params.numEntries.W)
468    }
469  }
470  vfWbBusyTableRead.zip(vfWbBusyTableIn).zipWithIndex.foreach { case ((busyTableRead: Option[FuBusyTableRead], busyTable: Option[UInt]), i) =>
471    if (busyTableRead.nonEmpty) {
472      val btrd = busyTableRead.get
473      val bt = busyTable.get
474      btrd.io.in.fuBusyTable := bt
475      btrd.io.in.fuTypeRegVec := fuTypeVec
476      vfWbBusyTableMask(i) := btrd.io.out.fuBusyTableMask
477    }
478    else {
479      vfWbBusyTableMask(i) := 0.U(params.numEntries.W)
480    }
481  }
482
483  wakeUpQueues.zipWithIndex.foreach { case (wakeUpQueueOption, i) =>
484    wakeUpQueueOption.foreach {
485      wakeUpQueue =>
486        val flush = Wire(new WakeupQueueFlush)
487        flush.redirect := io.flush
488        flush.ldCancel := io.ldCancel
489        flush.og0Fail := io.og0Resp(i).valid && RSFeedbackType.isBlocked(io.og0Resp(i).bits.respType)
490        flush.og1Fail := io.og1Resp(i).valid && RSFeedbackType.isBlocked(io.og1Resp(i).bits.respType)
491        wakeUpQueue.io.flush := flush
492        wakeUpQueue.io.enq.valid := deqBeforeDly(i).fire
493        wakeUpQueue.io.enq.bits.uop :<= deqBeforeDly(i).bits.common
494        wakeUpQueue.io.enq.bits.uop.pdestCopy.foreach(_ := 0.U)
495        wakeUpQueue.io.enq.bits.lat := getDeqLat(i, deqBeforeDly(i).bits.common.fuType)
496    }
497  }
498
499  deqBeforeDly.zipWithIndex.foreach { case (deq, i) =>
500    deq.valid                := finalDeqSelValidVec(i) && !cancelDeqVec(i)
501    deq.bits.addrOH          := finalDeqSelOHVec(i)
502    deq.bits.common.isFirstIssue := deqFirstIssueVec(i)
503    deq.bits.common.iqIdx    := OHToUInt(finalDeqSelOHVec(i))
504    deq.bits.common.fuType   := IQFuType.readFuType(deqEntryVec(i).bits.status.fuType, params.getFuCfgs.map(_.fuType)).asUInt
505    deq.bits.common.fuOpType := deqEntryVec(i).bits.payload.fuOpType
506    deq.bits.common.rfWen.foreach(_ := deqEntryVec(i).bits.payload.rfWen)
507    deq.bits.common.fpWen.foreach(_ := deqEntryVec(i).bits.payload.fpWen)
508    deq.bits.common.vecWen.foreach(_ := deqEntryVec(i).bits.payload.vecWen)
509    deq.bits.common.flushPipe.foreach(_ := deqEntryVec(i).bits.payload.flushPipe)
510    deq.bits.common.pdest := deqEntryVec(i).bits.payload.pdest
511    deq.bits.common.robIdx := deqEntryVec(i).bits.status.robIdx
512
513    require(deq.bits.common.dataSources.size <= finalDataSources(i).size)
514    deq.bits.common.dataSources.zip(finalDataSources(i)).foreach { case (sink, source) => sink := source}
515    deq.bits.common.l1ExuOH.foreach(_ := finalWakeUpL1ExuOH.get(i))
516    deq.bits.common.srcTimer.foreach(_ := finalSrcTimer.get(i))
517    deq.bits.common.loadDependency.foreach(_ := deqEntryVec(i).bits.status.mergedLoadDependency.get)
518    deq.bits.common.src := DontCare
519    deq.bits.common.preDecode.foreach(_ := deqEntryVec(i).bits.payload.preDecodeInfo)
520
521    deq.bits.rf.zip(deqEntryVec(i).bits.status.srcStatus.map(_.psrc)).zip(deqEntryVec(i).bits.status.srcStatus.map(_.srcType)).foreach { case ((rf, psrc), srcType) =>
522      // psrc in status array can be pregIdx of IntRegFile or VfRegFile
523      rf.foreach(_.addr := psrc)
524      rf.foreach(_.srcType := srcType)
525    }
526    deq.bits.srcType.zip(deqEntryVec(i).bits.status.srcStatus.map(_.srcType)).foreach { case (sink, source) =>
527      sink := source
528    }
529    deq.bits.immType := deqEntryVec(i).bits.payload.selImm
530    deq.bits.common.imm := deqEntryVec(i).bits.imm.getOrElse(0.U)
531
532    deq.bits.common.perfDebugInfo := deqEntryVec(i).bits.payload.debugInfo
533    deq.bits.common.perfDebugInfo.selectTime := GTimer()
534    deq.bits.common.perfDebugInfo.issueTime := GTimer() + 1.U
535  }
536
537  private val deqShift = WireDefault(deqBeforeDly)
538  deqShift.zip(deqBeforeDly).foreach {
539    case (shifted, original) =>
540      original.ready := shifted.ready // this will not cause combinational loop
541      shifted.bits.common.loadDependency.foreach(
542        _ := original.bits.common.loadDependency.get.map(_ << 1)
543      )
544  }
545  io.deqDelay.zip(deqShift).foreach { case (deqDly, deq) =>
546    NewPipelineConnect(
547      deq, deqDly, deqDly.valid,
548      false.B,
549      Option("Scheduler2DataPathPipe")
550    )
551  }
552  if(backendParams.debugEn) {
553    dontTouch(io.deqDelay)
554  }
555  io.wakeupToIQ.zipWithIndex.foreach { case (wakeup, i) =>
556    if (wakeUpQueues(i).nonEmpty && finalWakeUpL1ExuOH.nonEmpty) {
557      wakeup.valid := wakeUpQueues(i).get.io.deq.valid
558      wakeup.bits.fromExuInput(wakeUpQueues(i).get.io.deq.bits, finalWakeUpL1ExuOH.get(i))
559      wakeup.bits.loadDependency := wakeUpQueues(i).get.io.deq.bits.loadDependency.getOrElse(0.U.asTypeOf(wakeup.bits.loadDependency))
560      wakeup.bits.is0Lat := getDeqLat(i, wakeUpQueues(i).get.io.deq.bits.fuType) === 0.U
561    } else if (wakeUpQueues(i).nonEmpty) {
562      wakeup.valid := wakeUpQueues(i).get.io.deq.valid
563      wakeup.bits.fromExuInput(wakeUpQueues(i).get.io.deq.bits)
564      wakeup.bits.loadDependency := wakeUpQueues(i).get.io.deq.bits.loadDependency.getOrElse(0.U.asTypeOf(wakeup.bits.loadDependency))
565      wakeup.bits.is0Lat := getDeqLat(i, wakeUpQueues(i).get.io.deq.bits.fuType) === 0.U
566    } else {
567      wakeup.valid := false.B
568      wakeup.bits := 0.U.asTypeOf(wakeup.bits)
569      wakeup.bits.is0Lat :=  0.U
570    }
571    if (wakeUpQueues(i).nonEmpty) {
572      wakeup.bits.rfWen  := (if (wakeUpQueues(i).get.io.deq.bits.rfWen .nonEmpty) wakeUpQueues(i).get.io.deq.valid && wakeUpQueues(i).get.io.deq.bits.rfWen .get else false.B)
573      wakeup.bits.fpWen  := (if (wakeUpQueues(i).get.io.deq.bits.fpWen .nonEmpty) wakeUpQueues(i).get.io.deq.valid && wakeUpQueues(i).get.io.deq.bits.fpWen .get else false.B)
574      wakeup.bits.vecWen := (if (wakeUpQueues(i).get.io.deq.bits.vecWen.nonEmpty) wakeUpQueues(i).get.io.deq.valid && wakeUpQueues(i).get.io.deq.bits.vecWen.get else false.B)
575    }
576
577    if(wakeUpQueues(i).nonEmpty && wakeup.bits.pdestCopy.nonEmpty){
578      wakeup.bits.pdestCopy.get := wakeUpQueues(i).get.io.deq.bits.pdestCopy.get
579    }
580    if (wakeUpQueues(i).nonEmpty && wakeup.bits.rfWenCopy.nonEmpty) {
581      wakeup.bits.rfWenCopy.get := wakeUpQueues(i).get.io.deq.bits.rfWenCopy.get
582    }
583    if (wakeUpQueues(i).nonEmpty && wakeup.bits.fpWenCopy.nonEmpty) {
584      wakeup.bits.fpWenCopy.get := wakeUpQueues(i).get.io.deq.bits.fpWenCopy.get
585    }
586    if (wakeUpQueues(i).nonEmpty && wakeup.bits.vecWenCopy.nonEmpty) {
587      wakeup.bits.vecWenCopy.get := wakeUpQueues(i).get.io.deq.bits.vecWenCopy.get
588    }
589    if (wakeUpQueues(i).nonEmpty && wakeup.bits.loadDependencyCopy.nonEmpty) {
590      wakeup.bits.loadDependencyCopy.get := wakeUpQueues(i).get.io.deq.bits.loadDependencyCopy.get
591    }
592  }
593
594  // Todo: better counter implementation
595  private val enqHasValid = validVec.take(params.numEnq).reduce(_ | _)
596  private val enqEntryValidCnt = PopCount(validVec.take(params.numEnq))
597  private val othersValidCnt = PopCount(validVec.drop(params.numEnq))
598  io.status.leftVec(0) := validVec.drop(params.numEnq).reduce(_ & _)
599  for (i <- 0 until params.numEnq) {
600    io.status.leftVec(i + 1) := othersValidCnt === (params.numEntries - params.numEnq - (i + 1)).U
601  }
602  private val othersLeftOneCaseVec = Wire(Vec(params.numEntries - params.numEnq, UInt((params.numEntries - params.numEnq).W)))
603  othersLeftOneCaseVec.zipWithIndex.foreach { case (leftone, i) =>
604    leftone := ~(1.U((params.numEntries - params.numEnq).W) << i)
605  }
606  private val othersLeftOne = othersLeftOneCaseVec.map(_ === VecInit(validVec.drop(params.numEnq)).asUInt).reduce(_ | _)
607  private val othersCanotIn = othersLeftOne || validVec.drop(params.numEnq).reduce(_ & _)
608
609  io.enq.foreach(_.ready := !othersCanotIn || !enqHasValid)
610  io.status.empty := !Cat(validVec).orR
611  io.status.full := othersCanotIn
612  io.status.validCnt := PopCount(validVec)
613
614  protected def getDeqLat(deqPortIdx: Int, fuType: UInt) : UInt = {
615    Mux1H(fuLatencyMaps(deqPortIdx) map { case (k, v) => (fuType(k.id), v.U) })
616  }
617
618  // issue perf counter
619  // enq count
620  XSPerfAccumulate("enq_valid_cnt", PopCount(io.enq.map(_.fire)))
621  XSPerfAccumulate("enq_fire_cnt", PopCount(io.enq.map(_.fire)))
622  // valid count
623  XSPerfHistogram("enq_entry_valid_cnt", enqEntryValidCnt, true.B, 0, params.numEnq + 1)
624  XSPerfHistogram("other_entry_valid_cnt", othersValidCnt, true.B, 0, params.numEntries - params.numEnq + 1)
625  XSPerfHistogram("valid_cnt", PopCount(validVec), true.B, 0, params.numEntries + 1)
626  // only split when more than 1 func type
627  if (params.getFuCfgs.size > 0) {
628    for (t <- FuType.functionNameMap.keys) {
629      val fuName = FuType.functionNameMap(t)
630      if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _)) {
631        XSPerfHistogram(s"valid_cnt_hist_futype_${fuName}", PopCount(validVec.zip(fuTypeVec).map { case (v, fu) => v && fu === t.U }), true.B, 0, params.numEntries, 1)
632      }
633    }
634  }
635  // ready instr count
636  private val readyEntriesCnt = PopCount(validVec.zip(canIssueVec).map(x => x._1 && x._2))
637  XSPerfHistogram("ready_cnt", readyEntriesCnt, true.B, 0, params.numEntries + 1)
638  // only split when more than 1 func type
639  if (params.getFuCfgs.size > 0) {
640    for (t <- FuType.functionNameMap.keys) {
641      val fuName = FuType.functionNameMap(t)
642      if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _)) {
643        XSPerfHistogram(s"ready_cnt_hist_futype_${fuName}", PopCount(validVec.zip(canIssueVec).zip(fuTypeVec).map { case ((v, c), fu) => v && c && fu === t.U }), true.B, 0, params.numEntries, 1)
644      }
645    }
646  }
647
648  // deq instr count
649  XSPerfAccumulate("issue_instr_pre_count", PopCount(deqBeforeDly.map(_.valid)))
650  XSPerfHistogram("issue_instr_pre_count_hist", PopCount(deqBeforeDly.map(_.valid)), true.B, 0, params.numDeq + 1, 1)
651  XSPerfAccumulate("issue_instr_count", PopCount(io.deqDelay.map(_.valid)))
652  XSPerfHistogram("issue_instr_count_hist", PopCount(io.deqDelay.map(_.valid)), true.B, 0, params.numDeq + 1, 1)
653
654  // deq instr data source count
655  XSPerfAccumulate("issue_datasource_reg", deqBeforeDly.map{ deq =>
656    PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) })
657  }.reduce(_ +& _))
658  XSPerfAccumulate("issue_datasource_bypass", deqBeforeDly.map{ deq =>
659    PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) })
660  }.reduce(_ +& _))
661  XSPerfAccumulate("issue_datasource_forward", deqBeforeDly.map{ deq =>
662    PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) })
663  }.reduce(_ +& _))
664  XSPerfAccumulate("issue_datasource_noreg", deqBeforeDly.map{ deq =>
665    PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) })
666  }.reduce(_ +& _))
667
668  XSPerfHistogram("issue_datasource_reg_hist", deqBeforeDly.map{ deq =>
669    PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) })
670  }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1)
671  XSPerfHistogram("issue_datasource_bypass_hist", deqBeforeDly.map{ deq =>
672    PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) })
673  }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1)
674  XSPerfHistogram("issue_datasource_forward_hist", deqBeforeDly.map{ deq =>
675    PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) })
676  }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1)
677  XSPerfHistogram("issue_datasource_noreg_hist", deqBeforeDly.map{ deq =>
678    PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) })
679  }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1)
680
681  // deq instr data source count for each futype
682  for (t <- FuType.functionNameMap.keys) {
683    val fuName = FuType.functionNameMap(t)
684    if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _)) {
685      XSPerfAccumulate(s"issue_datasource_reg_futype_${fuName}", deqBeforeDly.map{ deq =>
686        PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U })
687      }.reduce(_ +& _))
688      XSPerfAccumulate(s"issue_datasource_bypass_futype_${fuName}", deqBeforeDly.map{ deq =>
689        PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U })
690      }.reduce(_ +& _))
691      XSPerfAccumulate(s"issue_datasource_forward_futype_${fuName}", deqBeforeDly.map{ deq =>
692        PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U })
693      }.reduce(_ +& _))
694      XSPerfAccumulate(s"issue_datasource_noreg_futype_${fuName}", deqBeforeDly.map{ deq =>
695        PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U })
696      }.reduce(_ +& _))
697
698      XSPerfHistogram(s"issue_datasource_reg_hist_futype_${fuName}", deqBeforeDly.map{ deq =>
699        PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U })
700      }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1)
701      XSPerfHistogram(s"issue_datasource_bypass_hist_futype_${fuName}", deqBeforeDly.map{ deq =>
702        PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U })
703      }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1)
704      XSPerfHistogram(s"issue_datasource_forward_hist_futype_${fuName}", deqBeforeDly.map{ deq =>
705        PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U })
706      }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1)
707      XSPerfHistogram(s"issue_datasource_noreg_hist_futype_${fuName}", deqBeforeDly.map{ deq =>
708        PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U })
709      }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1)
710    }
711  }
712
713  // cancel instr count
714  if (params.hasIQWakeUp) {
715    val cancelVec: Vec[Bool] = entries.io.cancel.get
716    XSPerfAccumulate("cancel_instr_count", PopCount(validVec.zip(cancelVec).map(x => x._1 & x._2)))
717    XSPerfHistogram("cancel_instr_hist", PopCount(validVec.zip(cancelVec).map(x => x._1 & x._2)), true.B, 0, params.numEntries, 1)
718    for (t <- FuType.functionNameMap.keys) {
719      val fuName = FuType.functionNameMap(t)
720      if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _)) {
721        XSPerfAccumulate(s"cancel_instr_count_futype_${fuName}", PopCount(validVec.zip(cancelVec).zip(fuTypeVec).map{ case ((x, y), fu) => x & y & fu === t.U }))
722        XSPerfHistogram(s"cancel_instr_hist_futype_${fuName}", PopCount(validVec.zip(cancelVec).zip(fuTypeVec).map{ case ((x, y), fu) => x & y & fu === t.U }), true.B, 0, params.numEntries, 1)
723      }
724    }
725  }
726}
727
728class IssueQueueJumpBundle extends Bundle {
729  val pc = UInt(VAddrData().dataWidth.W)
730}
731
732class IssueQueueLoadBundle(implicit p: Parameters) extends XSBundle {
733  val fastMatch = UInt(backendParams.LduCnt.W)
734  val fastImm = UInt(12.W)
735}
736
737class IssueQueueIntIO()(implicit p: Parameters, params: IssueBlockParams) extends IssueQueueIO
738
739class IssueQueueIntImp(override val wrapper: IssueQueue)(implicit p: Parameters, iqParams: IssueBlockParams)
740  extends IssueQueueImp(wrapper)
741{
742  io.suggestName("none")
743  override lazy val io = IO(new IssueQueueIntIO).suggestName("io")
744
745  deqBeforeDly.zipWithIndex.foreach{ case (deq, i) => {
746    deq.bits.common.pc.foreach(_ := deqEntryVec(i).bits.payload.pc)
747    deq.bits.common.preDecode.foreach(_ := deqEntryVec(i).bits.payload.preDecodeInfo)
748    deq.bits.common.ftqIdx.foreach(_ := deqEntryVec(i).bits.payload.ftqPtr)
749    deq.bits.common.ftqOffset.foreach(_ := deqEntryVec(i).bits.payload.ftqOffset)
750    deq.bits.common.predictInfo.foreach(x => {
751      x.target := DontCare
752      x.taken := deqEntryVec(i).bits.payload.pred_taken
753    })
754    // for std
755    deq.bits.common.sqIdx.foreach(_ := deqEntryVec(i).bits.payload.sqIdx)
756    // for i2f
757    deq.bits.common.fpu.foreach(_ := deqEntryVec(i).bits.payload.fpu)
758  }}
759}
760
761class IssueQueueVfImp(override val wrapper: IssueQueue)(implicit p: Parameters, iqParams: IssueBlockParams)
762  extends IssueQueueImp(wrapper)
763{
764  s0_enqBits.foreach{ x =>
765    x.srcType(3) := SrcType.vp // v0: mask src
766    x.srcType(4) := SrcType.vp // vl&vtype
767  }
768  deqBeforeDly.zipWithIndex.foreach{ case (deq, i) => {
769    deq.bits.common.fpu.foreach(_ := deqEntryVec(i).bits.payload.fpu)
770    deq.bits.common.vpu.foreach(_ := deqEntryVec(i).bits.payload.vpu)
771    deq.bits.common.vpu.foreach(_.vuopIdx := deqEntryVec(i).bits.payload.uopIdx)
772    deq.bits.common.vpu.foreach(_.lastUop := deqEntryVec(i).bits.payload.lastUop)
773  }}
774}
775
776class IssueQueueMemBundle(implicit p: Parameters, params: IssueBlockParams) extends Bundle {
777  val feedbackIO = Flipped(Vec(params.numDeq, new MemRSFeedbackIO))
778  val checkWait = new Bundle {
779    val stIssuePtr = Input(new SqPtr)
780    val memWaitUpdateReq = Flipped(new MemWaitUpdateReq)
781  }
782  val loadFastMatch = Output(Vec(params.LdExuCnt, new IssueQueueLoadBundle))
783  val loadWakeUp = Input(Vec(params.LdExuCnt, ValidIO(new DynInst())))
784
785  // vector
786  val sqDeqPtr = OptionWrapper(params.isVecMemIQ, Input(new SqPtr))
787  val lqDeqPtr = OptionWrapper(params.isVecMemIQ, Input(new LqPtr))
788}
789
790class IssueQueueMemIO(implicit p: Parameters, params: IssueBlockParams) extends IssueQueueIO {
791  val memIO = Some(new IssueQueueMemBundle)
792}
793
794class IssueQueueMemAddrImp(override val wrapper: IssueQueue)(implicit p: Parameters, params: IssueBlockParams)
795  extends IssueQueueImp(wrapper) with HasCircularQueuePtrHelper {
796
797  require(params.StdCnt == 0 && (params.LduCnt + params.StaCnt + params.HyuCnt + params.VlduCnt) > 0, "IssueQueueMemAddrImp can only be instance of MemAddr IQ, " +
798    s"StdCnt: ${params.StdCnt}, LduCnt: ${params.LduCnt}, StaCnt: ${params.StaCnt}, HyuCnt: ${params.HyuCnt}")
799  println(s"[IssueQueueMemAddrImp] StdCnt: ${params.StdCnt}, LduCnt: ${params.LduCnt}, StaCnt: ${params.StaCnt}, HyuCnt: ${params.HyuCnt}")
800
801  io.suggestName("none")
802  override lazy val io = IO(new IssueQueueMemIO).suggestName("io")
803  private val memIO = io.memIO.get
804
805  memIO.loadFastMatch := 0.U.asTypeOf(memIO.loadFastMatch) // TODO: is still needed?
806
807  for (i <- io.enq.indices) {
808    val blockNotReleased = isAfter(io.enq(i).bits.sqIdx, memIO.checkWait.stIssuePtr)
809    val storeAddrWaitForIsIssuing = VecInit((0 until StorePipelineWidth).map(i => {
810      memIO.checkWait.memWaitUpdateReq.robIdx(i).valid &&
811        memIO.checkWait.memWaitUpdateReq.robIdx(i).bits.value === io.enq(i).bits.waitForRobIdx.value
812    })).asUInt.orR && !io.enq(i).bits.loadWaitStrict // is waiting for store addr ready
813    s0_enqBits(i).loadWaitBit := io.enq(i).bits.loadWaitBit && !storeAddrWaitForIsIssuing && blockNotReleased
814    // when have vpu
815    if (params.VlduCnt > 0 || params.VstuCnt > 0) {
816      s0_enqBits(i).srcType(3) := SrcType.vp // v0: mask src
817      s0_enqBits(i).srcType(4) := SrcType.vp // vl&vtype
818    }
819  }
820
821  for (i <- entries.io.enq.indices) {
822    entries.io.enq(i).bits.status match { case enqData =>
823      enqData.blocked := false.B // s0_enqBits(i).loadWaitBit
824      enqData.mem.get.strictWait := s0_enqBits(i).loadWaitStrict
825      enqData.mem.get.waitForStd := false.B
826      enqData.mem.get.waitForRobIdx := s0_enqBits(i).waitForRobIdx
827      enqData.mem.get.waitForSqIdx := 0.U.asTypeOf(enqData.mem.get.waitForSqIdx) // generated by sq, will be updated later
828      enqData.mem.get.sqIdx := s0_enqBits(i).sqIdx
829    }
830  }
831  entries.io.fromMem.get.slowResp.zipWithIndex.foreach { case (slowResp, i) =>
832    slowResp.valid := memIO.feedbackIO(i).feedbackSlow.valid
833    slowResp.bits.robIdx := memIO.feedbackIO(i).feedbackSlow.bits.robIdx
834    slowResp.bits.respType := Mux(memIO.feedbackIO(i).feedbackSlow.bits.hit, RSFeedbackType.fuIdle, RSFeedbackType.feedbackInvalid)
835    slowResp.bits.dataInvalidSqIdx := memIO.feedbackIO(i).feedbackSlow.bits.dataInvalidSqIdx
836    slowResp.bits.rfWen := DontCare
837    slowResp.bits.fuType := DontCare
838  }
839
840  entries.io.fromMem.get.fastResp.zipWithIndex.foreach { case (fastResp, i) =>
841    fastResp.valid := memIO.feedbackIO(i).feedbackFast.valid
842    fastResp.bits.robIdx := memIO.feedbackIO(i).feedbackFast.bits.robIdx
843    fastResp.bits.respType := Mux(memIO.feedbackIO(i).feedbackFast.bits.hit, RSFeedbackType.fuIdle, memIO.feedbackIO(i).feedbackFast.bits.sourceType)
844    fastResp.bits.dataInvalidSqIdx := 0.U.asTypeOf(fastResp.bits.dataInvalidSqIdx)
845    fastResp.bits.rfWen := DontCare
846    fastResp.bits.fuType := DontCare
847  }
848
849  entries.io.fromMem.get.memWaitUpdateReq := memIO.checkWait.memWaitUpdateReq
850  entries.io.fromMem.get.stIssuePtr := memIO.checkWait.stIssuePtr
851
852  // load wakeup
853  val loadWakeUpIter = memIO.loadWakeUp.iterator
854  io.wakeupToIQ.zip(params.exuBlockParams).zipWithIndex.foreach { case ((wakeup, param), i) =>
855    if (param.hasLoadExu) {
856      require(wakeUpQueues(i).isEmpty)
857      val uopWire = loadWakeUpIter.next()
858      val uop = Wire(chiselTypeOf(uopWire))
859      uop.valid := RegNext(uopWire.valid)
860      uop.bits  := RegEnable(uopWire.bits, uopWire.valid)
861      wakeup.valid := uop.fire && FuType.isLoad(uop.bits.fuType)
862      wakeup.bits.fromDynInst(uop.bits)
863      wakeup.bits.loadDependency.foreach(_ := 0.U) // this is correct for load only
864    }
865  }
866  require(!loadWakeUpIter.hasNext)
867
868  deqBeforeDly.zipWithIndex.foreach { case (deq, i) =>
869    deq.bits.common.loadWaitBit.foreach(_ := deqEntryVec(i).bits.payload.loadWaitBit)
870    deq.bits.common.waitForRobIdx.foreach(_ := deqEntryVec(i).bits.payload.waitForRobIdx)
871    deq.bits.common.storeSetHit.foreach(_ := deqEntryVec(i).bits.payload.storeSetHit)
872    deq.bits.common.loadWaitStrict.foreach(_ := deqEntryVec(i).bits.payload.loadWaitStrict)
873    deq.bits.common.ssid.foreach(_ := deqEntryVec(i).bits.payload.ssid)
874    deq.bits.common.sqIdx.get := deqEntryVec(i).bits.payload.sqIdx
875    deq.bits.common.lqIdx.get := deqEntryVec(i).bits.payload.lqIdx
876    deq.bits.common.ftqIdx.foreach(_ := deqEntryVec(i).bits.payload.ftqPtr)
877    deq.bits.common.ftqOffset.foreach(_ := deqEntryVec(i).bits.payload.ftqOffset)
878    // when have vpu
879    if (params.VlduCnt > 0 || params.VstuCnt > 0) {
880      deq.bits.common.vpu.foreach(_ := deqEntryVec(i).bits.payload.vpu)
881      deq.bits.common.vpu.foreach(_.vuopIdx := deqEntryVec(i).bits.payload.uopIdx)
882    }
883  }
884}
885
886class IssueQueueVecMemImp(override val wrapper: IssueQueue)(implicit p: Parameters, params: IssueBlockParams)
887  extends IssueQueueImp(wrapper) with HasCircularQueuePtrHelper {
888
889  require((params.VstdCnt + params.VlduCnt + params.VstaCnt) > 0, "IssueQueueVecMemImp can only be instance of VecMem IQ")
890
891  io.suggestName("none")
892  override lazy val io = IO(new IssueQueueMemIO).suggestName("io")
893  private val memIO = io.memIO.get
894
895  def selectOldUop(robIdx: Seq[RobPtr], uopIdx: Seq[UInt], valid: Seq[Bool]): Vec[Bool] = {
896    val compareVec = (0 until robIdx.length).map(i => (0 until i).map(j => isAfter(robIdx(j), robIdx(i)) || (robIdx(j).value === robIdx(i).value && uopIdx(i) < uopIdx(j))))
897    val resultOnehot = VecInit((0 until robIdx.length).map(i => Cat((0 until robIdx.length).map(j =>
898      (if (j < i) !valid(j) || compareVec(i)(j)
899      else if (j == i) valid(i)
900      else !valid(j) || !compareVec(j)(i))
901    )).andR))
902    resultOnehot
903  }
904
905  val robIdxVec = entries.io.robIdx.get
906  val uopIdxVec = entries.io.uopIdx.get
907  val allEntryOldestOH = selectOldUop(robIdxVec, uopIdxVec, validVec)
908
909  finalDeqSelValidVec.head := (allEntryOldestOH.asUInt & canIssueVec.asUInt).orR
910  finalDeqSelOHVec.head := allEntryOldestOH.asUInt & canIssueVec.asUInt
911
912  if (params.isVecMemAddrIQ) {
913    s0_enqBits.foreach{ x =>
914      x.srcType(3) := SrcType.vp // v0: mask src
915      x.srcType(4) := SrcType.vp // vl&vtype
916    }
917
918    for (i <- io.enq.indices) {
919      s0_enqBits(i).loadWaitBit := false.B
920    }
921
922    for (i <- entries.io.enq.indices) {
923      entries.io.enq(i).bits.status match { case enqData =>
924        enqData.blocked := false.B // s0_enqBits(i).loadWaitBit
925        enqData.mem.get.strictWait := s0_enqBits(i).loadWaitStrict
926        enqData.mem.get.waitForStd := false.B
927        enqData.mem.get.waitForRobIdx := s0_enqBits(i).waitForRobIdx
928        enqData.mem.get.waitForSqIdx := 0.U.asTypeOf(enqData.mem.get.waitForSqIdx) // generated by sq, will be updated later
929        enqData.mem.get.sqIdx := s0_enqBits(i).sqIdx
930      }
931
932      entries.io.fromMem.get.slowResp.zipWithIndex.foreach { case (slowResp, i) =>
933        slowResp.valid                 := memIO.feedbackIO(i).feedbackSlow.valid
934        slowResp.bits.robIdx           := memIO.feedbackIO(i).feedbackSlow.bits.robIdx
935        slowResp.bits.respType         := Mux(memIO.feedbackIO(i).feedbackSlow.bits.hit, RSFeedbackType.fuIdle, RSFeedbackType.feedbackInvalid)
936        slowResp.bits.dataInvalidSqIdx := memIO.feedbackIO(i).feedbackSlow.bits.dataInvalidSqIdx
937        slowResp.bits.rfWen := DontCare
938        slowResp.bits.fuType := DontCare
939      }
940
941      entries.io.fromMem.get.fastResp.zipWithIndex.foreach { case (fastResp, i) =>
942        fastResp.valid                 := memIO.feedbackIO(i).feedbackFast.valid
943        fastResp.bits.robIdx           := memIO.feedbackIO(i).feedbackFast.bits.robIdx
944        fastResp.bits.respType         := memIO.feedbackIO(i).feedbackFast.bits.sourceType
945        fastResp.bits.dataInvalidSqIdx := 0.U.asTypeOf(fastResp.bits.dataInvalidSqIdx)
946        fastResp.bits.rfWen := DontCare
947        fastResp.bits.fuType := DontCare
948      }
949
950      entries.io.fromMem.get.memWaitUpdateReq := memIO.checkWait.memWaitUpdateReq
951      entries.io.fromMem.get.stIssuePtr := memIO.checkWait.stIssuePtr
952    }
953  }
954
955  for (i <- entries.io.enq.indices) {
956    entries.io.enq(i).bits.status.vecMem.get match {
957      case enqData =>
958        enqData.sqIdx := s0_enqBits(i).sqIdx
959        enqData.lqIdx := s0_enqBits(i).lqIdx
960        enqData.uopIdx := s0_enqBits(i).uopIdx
961    }
962  }
963
964  entries.io.vecMemIn.get.sqDeqPtr := memIO.sqDeqPtr.get
965  entries.io.vecMemIn.get.lqDeqPtr := memIO.lqDeqPtr.get
966
967  entries.io.fromMem.get.fastResp.zipWithIndex.foreach { case (resp, i) =>
968    resp.bits.uopIdx.get := 0.U // Todo
969  }
970
971  entries.io.fromMem.get.slowResp.zipWithIndex.foreach { case (resp, i) =>
972    resp.bits.uopIdx.get := 0.U // Todo
973  }
974
975  deqBeforeDly.zipWithIndex.foreach { case (deq, i) =>
976    deq.bits.common.sqIdx.foreach(_ := deqEntryVec(i).bits.payload.sqIdx)
977    deq.bits.common.lqIdx.foreach(_ := deqEntryVec(i).bits.payload.lqIdx)
978    if (params.isVecLdAddrIQ) {
979      deq.bits.common.ftqIdx.get := deqEntryVec(i).bits.payload.ftqPtr
980      deq.bits.common.ftqOffset.get := deqEntryVec(i).bits.payload.ftqOffset
981    }
982    deq.bits.common.fpu.foreach(_ := deqEntryVec(i).bits.payload.fpu)
983    deq.bits.common.vpu.foreach(_ := deqEntryVec(i).bits.payload.vpu)
984    deq.bits.common.vpu.foreach(_.vuopIdx := deqEntryVec(i).bits.payload.uopIdx)
985    deq.bits.common.vpu.foreach(_.lastUop := deqEntryVec(i).bits.payload.lastUop)
986  }
987}
988