1package xiangshan.backend.issue 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 7import utility.{GTimer, HasCircularQueuePtrHelper, SelectOne, GatedValidRegNext} 8import utils._ 9import xiangshan._ 10import xiangshan.backend.Bundles._ 11import xiangshan.backend.issue.EntryBundles._ 12import xiangshan.backend.decode.{ImmUnion, Imm_LUI_LOAD} 13import xiangshan.backend.datapath.DataConfig._ 14import xiangshan.backend.datapath.DataSource 15import xiangshan.backend.fu.{FuConfig, FuType} 16import xiangshan.mem.{MemWaitUpdateReq, SqPtr, LqPtr} 17import xiangshan.backend.rob.RobPtr 18import xiangshan.backend.datapath.NewPipelineConnect 19 20class IssueQueue(params: IssueBlockParams)(implicit p: Parameters) extends LazyModule with HasXSParameter { 21 override def shouldBeInlined: Boolean = false 22 23 implicit val iqParams = params 24 lazy val module: IssueQueueImp = iqParams.schdType match { 25 case IntScheduler() => new IssueQueueIntImp(this) 26 case VfScheduler() => new IssueQueueVfImp(this) 27 case MemScheduler() => 28 if (iqParams.StdCnt == 0 && !iqParams.isVecMemIQ) new IssueQueueMemAddrImp(this) 29 else if (iqParams.isVecMemIQ) new IssueQueueVecMemImp(this) 30 else new IssueQueueIntImp(this) 31 case _ => null 32 } 33} 34 35class IssueQueueStatusBundle(numEnq: Int, numEntries: Int) extends Bundle { 36 val empty = Output(Bool()) 37 val full = Output(Bool()) 38 val validCnt = Output(UInt(log2Ceil(numEntries).W)) 39 val leftVec = Output(Vec(numEnq + 1, Bool())) 40} 41 42class IssueQueueDeqRespBundle(implicit p:Parameters, params: IssueBlockParams) extends EntryDeqRespBundle 43 44class IssueQueueIO()(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 45 // Inputs 46 val flush = Flipped(ValidIO(new Redirect)) 47 val enq = Vec(params.numEnq, Flipped(DecoupledIO(new DynInst))) 48 49 val og0Resp = Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle))) 50 val og1Resp = Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle))) 51 val og2Resp = OptionWrapper(params.inVfSchd, Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle)))) 52 val finalIssueResp = OptionWrapper(params.LdExuCnt > 0, Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle)))) 53 val memAddrIssueResp = OptionWrapper(params.LdExuCnt > 0, Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle)))) 54 val wbBusyTableRead = Input(params.genWbFuBusyTableReadBundle()) 55 val wbBusyTableWrite = Output(params.genWbFuBusyTableWriteBundle()) 56 val wakeupFromWB: MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = Flipped(params.genWBWakeUpSinkValidBundle) 57 val wakeupFromIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(params.genIQWakeUpSinkValidBundle) 58 val og0Cancel = Input(ExuOH(backendParams.numExu)) 59 val og1Cancel = Input(ExuOH(backendParams.numExu)) 60 val ldCancel = Vec(backendParams.LduCnt + backendParams.HyuCnt, Flipped(new LoadCancelIO)) 61 62 // Outputs 63 val wakeupToIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = params.genIQWakeUpSourceValidBundle 64 val status = Output(new IssueQueueStatusBundle(params.numEnq, params.numEntries)) 65 val validCntDeqVec = Output(Vec(params.numDeq,UInt(params.numEntries.U.getWidth.W))) 66 // val statusNext = Output(new IssueQueueStatusBundle(params.numEnq)) 67 68 val deqDelay: MixedVec[DecoupledIO[IssueQueueIssueBundle]] = params.genIssueDecoupledBundle// = deq.cloneType 69 def allWakeUp = wakeupFromWB ++ wakeupFromIQ 70} 71 72class IssueQueueImp(override val wrapper: IssueQueue)(implicit p: Parameters, val params: IssueBlockParams) 73 extends LazyModuleImp(wrapper) 74 with HasXSParameter { 75 76 override def desiredName: String = s"${params.getIQName}" 77 78 println(s"[IssueQueueImp] ${params.getIQName} wakeupFromWB(${io.wakeupFromWB.size}), " + 79 s"wakeup exu in(${params.wakeUpInExuSources.size}): ${params.wakeUpInExuSources.map(_.name).mkString("{",",","}")}, " + 80 s"wakeup exu out(${params.wakeUpOutExuSources.size}): ${params.wakeUpOutExuSources.map(_.name).mkString("{",",","}")}, " + 81 s"numEntries: ${params.numEntries}, numRegSrc: ${params.numRegSrc}, " + 82 s"numEnq: ${params.numEnq}, numSimp: ${params.numSimp}, numComp: ${params.numComp}, numDeq: ${params.numDeq}, " + 83 s"isAllSimp: ${params.isAllSimp}, isAllComp: ${params.isAllComp}") 84 85 require(params.numExu <= 2, "IssueQueue has not supported more than 2 deq ports") 86 require(params.numEnq <= 2, "IssueQueue has not supported more than 2 enq ports") 87 require(params.numSimp == 0 || params.numSimp >= params.numEnq, "numSimp should be 0 or at least not less than numEnq") 88 require(params.numComp == 0 || params.numComp >= params.numEnq, "numComp should be 0 or at least not less than numEnq") 89 90 val deqFuCfgs : Seq[Seq[FuConfig]] = params.exuBlockParams.map(_.fuConfigs) 91 val allDeqFuCfgs : Seq[FuConfig] = params.exuBlockParams.flatMap(_.fuConfigs) 92 val fuCfgsCnt : Map[FuConfig, Int] = allDeqFuCfgs.groupBy(x => x).map { case (cfg, cfgSeq) => (cfg, cfgSeq.length) } 93 val commonFuCfgs : Seq[FuConfig] = fuCfgsCnt.filter(_._2 > 1).keys.toSeq 94 val wakeupFuLatencyMaps : Seq[Map[FuType.OHType, Int]] = params.exuBlockParams.map(x => x.wakeUpFuLatencyMap) 95 96 println(s"[IssueQueueImp] ${params.getIQName} fuLatencyMaps: ${wakeupFuLatencyMaps}") 97 println(s"[IssueQueueImp] ${params.getIQName} commonFuCfgs: ${commonFuCfgs.map(_.name)}") 98 lazy val io = IO(new IssueQueueIO()) 99 100 // Modules 101 val entries = Module(new Entries) 102 val fuBusyTableWrite = params.exuBlockParams.map { case x => OptionWrapper(x.latencyValMax > 0, Module(new FuBusyTableWrite(x.fuLatencyMap))) } 103 val fuBusyTableRead = params.exuBlockParams.map { case x => OptionWrapper(x.latencyValMax > 0, Module(new FuBusyTableRead(x.fuLatencyMap))) } 104 val intWbBusyTableWrite = params.exuBlockParams.map { case x => OptionWrapper(x.intLatencyCertain, Module(new FuBusyTableWrite(x.intFuLatencyMap))) } 105 val intWbBusyTableRead = params.exuBlockParams.map { case x => OptionWrapper(x.intLatencyCertain, Module(new FuBusyTableRead(x.intFuLatencyMap))) } 106 val vfWbBusyTableWrite = params.exuBlockParams.map { case x => OptionWrapper(x.vfLatencyCertain, Module(new FuBusyTableWrite(x.vfFuLatencyMap))) } 107 val vfWbBusyTableRead = params.exuBlockParams.map { case x => OptionWrapper(x.vfLatencyCertain, Module(new FuBusyTableRead(x.vfFuLatencyMap))) } 108 109 class WakeupQueueFlush extends Bundle { 110 val redirect = ValidIO(new Redirect) 111 val ldCancel = Vec(backendParams.LduCnt + backendParams.HyuCnt, new LoadCancelIO) 112 val og0Fail = Output(Bool()) 113 val og1Fail = Output(Bool()) 114 } 115 116 private def flushFunc(exuInput: ExuInput, flush: WakeupQueueFlush, stage: Int): Bool = { 117 val redirectFlush = exuInput.robIdx.needFlush(flush.redirect) 118 val loadDependencyFlush = LoadShouldCancel(exuInput.loadDependency, flush.ldCancel) 119 val ogFailFlush = stage match { 120 case 1 => flush.og0Fail 121 case 2 => flush.og1Fail 122 case _ => false.B 123 } 124 redirectFlush || loadDependencyFlush || ogFailFlush 125 } 126 127 private def modificationFunc(exuInput: ExuInput): ExuInput = { 128 val newExuInput = WireDefault(exuInput) 129 newExuInput.loadDependency match { 130 case Some(deps) => deps.zip(exuInput.loadDependency.get).foreach(x => x._1 := x._2 << 1) 131 case None => 132 } 133 newExuInput 134 } 135 136 private def lastConnectFunc(exuInput: ExuInput, newInput: ExuInput): ExuInput = { 137 val lastExuInput = WireDefault(exuInput) 138 val newExuInput = WireDefault(newInput) 139 newExuInput.elements.foreach { case (name, data) => 140 if (lastExuInput.elements.contains(name)) { 141 data := lastExuInput.elements(name) 142 } 143 } 144 if (newExuInput.pdestCopy.nonEmpty && !lastExuInput.pdestCopy.nonEmpty) { 145 newExuInput.pdestCopy.get.foreach(_ := lastExuInput.pdest) 146 } 147 if (newExuInput.rfWenCopy.nonEmpty && !lastExuInput.rfWenCopy.nonEmpty) { 148 newExuInput.rfWenCopy.get.foreach(_ := lastExuInput.rfWen.get) 149 } 150 if (newExuInput.fpWenCopy.nonEmpty && !lastExuInput.fpWenCopy.nonEmpty) { 151 newExuInput.fpWenCopy.get.foreach(_ := lastExuInput.fpWen.get) 152 } 153 if (newExuInput.vecWenCopy.nonEmpty && !lastExuInput.vecWenCopy.nonEmpty) { 154 newExuInput.vecWenCopy.get.foreach(_ := lastExuInput.rfWen.get) 155 } 156 if (newExuInput.loadDependencyCopy.nonEmpty && !lastExuInput.loadDependencyCopy.nonEmpty) { 157 newExuInput.loadDependencyCopy.get.foreach(_ := lastExuInput.loadDependency.get) 158 } 159 newExuInput 160 } 161 162 val wakeUpQueues: Seq[Option[MultiWakeupQueue[ExuInput, WakeupQueueFlush]]] = params.exuBlockParams.map { x => OptionWrapper(x.isIQWakeUpSource && !x.hasLoadExu, Module( 163 new MultiWakeupQueue(new ExuInput(x), new ExuInput(x, x.copyWakeupOut, x.copyNum), new WakeupQueueFlush, x.wakeUpFuLatancySet, flushFunc, modificationFunc, lastConnectFunc) 164 ))} 165 val deqBeforeDly = Wire(params.genIssueDecoupledBundle) 166 167 val intWbBusyTableIn = io.wbBusyTableRead.map(_.intWbBusyTable) 168 val vfWbBusyTableIn = io.wbBusyTableRead.map(_.vfWbBusyTable) 169 val intWbBusyTableOut = io.wbBusyTableWrite.map(_.intWbBusyTable) 170 val vfWbBusyTableOut = io.wbBusyTableWrite.map(_.vfWbBusyTable) 171 val intDeqRespSetOut = io.wbBusyTableWrite.map(_.intDeqRespSet) 172 val vfDeqRespSetOut = io.wbBusyTableWrite.map(_.vfDeqRespSet) 173 val fuBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 174 val intWbBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 175 val vfWbBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 176 val s0_enqValidVec = io.enq.map(_.valid) 177 val s0_enqSelValidVec = Wire(Vec(params.numEnq, Bool())) 178 val s0_enqNotFlush = !io.flush.valid 179 val s0_enqBits = WireInit(VecInit(io.enq.map(_.bits))) 180 val s0_doEnqSelValidVec = s0_enqSelValidVec.map(_ && s0_enqNotFlush) //enqValid && notFlush && enqReady 181 182 183 val finalDeqSelValidVec = Wire(Vec(params.numDeq, Bool())) 184 val finalDeqSelOHVec = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 185 186 val validVec = VecInit(entries.io.valid.asBools) 187 val canIssueVec = VecInit(entries.io.canIssue.asBools) 188 dontTouch(canIssueVec) 189 val deqFirstIssueVec = entries.io.isFirstIssue 190 191 val dataSources: Vec[Vec[DataSource]] = entries.io.dataSources 192 val finalDataSources: Vec[Vec[DataSource]] = VecInit(finalDeqSelOHVec.map(oh => Mux1H(oh, dataSources))) 193 val loadDependency: Vec[Vec[UInt]] = entries.io.loadDependency 194 val finalLoadDependency: IndexedSeq[Vec[UInt]] = VecInit(finalDeqSelOHVec.map(oh => Mux1H(oh, loadDependency))) 195 // (entryIdx)(srcIdx)(exuIdx) 196 val wakeUpL1ExuOH: Option[Vec[Vec[UInt]]] = entries.io.srcWakeUpL1ExuOH 197 // (deqIdx)(srcIdx)(exuIdx) 198 val finalWakeUpL1ExuOH: Option[Vec[Vec[UInt]]] = wakeUpL1ExuOH.map(x => VecInit(finalDeqSelOHVec.map(oh => Mux1H(oh, x)))) 199 200 val fuTypeVec = Wire(Vec(params.numEntries, FuType())) 201 val deqEntryVec = Wire(Vec(params.numDeq, ValidIO(new EntryBundle))) 202 val canIssueMergeAllBusy = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 203 val deqCanIssue = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 204 205 //deq 206 val enqEntryOldestSel = Wire(Vec(params.numDeq, ValidIO(UInt(params.numEnq.W)))) 207 val simpEntryOldestSel = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numDeq + params.numEnq, ValidIO(UInt(params.numSimp.W))))) 208 val compEntryOldestSel = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numDeq, ValidIO(UInt(params.numComp.W))))) 209 val othersEntryOldestSel = Wire(Vec(params.numDeq, ValidIO(UInt((params.numEntries - params.numEnq).W)))) 210 val deqSelValidVec = Wire(Vec(params.numDeq, Bool())) 211 val deqSelOHVec = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 212 val cancelDeqVec = Wire(Vec(params.numDeq, Bool())) 213 214 val subDeqSelValidVec = OptionWrapper(params.deqFuSame, Wire(Vec(params.numDeq, Bool()))) 215 val subDeqSelOHVec = OptionWrapper(params.deqFuSame, Wire(Vec(params.numDeq, UInt(params.numEntries.W)))) 216 val subDeqRequest = OptionWrapper(params.deqFuSame, Wire(UInt(params.numEntries.W))) 217 218 //trans 219 val simpEntryEnqSelVec = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numEnq, UInt(params.numSimp.W)))) 220 val compEntryEnqSelVec = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numEnq, UInt(params.numComp.W)))) 221 val othersEntryEnqSelVec = OptionWrapper(params.isAllComp || params.isAllSimp, Wire(Vec(params.numEnq, UInt((params.numEntries - params.numEnq).W)))) 222 val simpAgeDetectRequest = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numDeq + params.numEnq, UInt(params.numSimp.W)))) 223 simpAgeDetectRequest.foreach(_ := 0.U.asTypeOf(simpAgeDetectRequest.get)) 224 225 /** 226 * Connection of [[entries]] 227 */ 228 entries.io match { case entriesIO: EntriesIO => 229 entriesIO.flush := io.flush 230 entriesIO.enq.zipWithIndex.foreach { case (enq, enqIdx) => 231 enq.valid := s0_doEnqSelValidVec(enqIdx) 232 enq.bits.status.robIdx := s0_enqBits(enqIdx).robIdx 233 enq.bits.status.fuType := IQFuType.readFuType(VecInit(s0_enqBits(enqIdx).fuType.asBools), params.getFuCfgs.map(_.fuType)) 234 val numLsrc = s0_enqBits(enqIdx).srcType.size.min(enq.bits.status.srcStatus.map(_.srcType).size) 235 for(j <- 0 until numLsrc) { 236 enq.bits.status.srcStatus(j).psrc := s0_enqBits(enqIdx).psrc(j) 237 enq.bits.status.srcStatus(j).srcType := s0_enqBits(enqIdx).srcType(j) 238 enq.bits.status.srcStatus(j).srcState := s0_enqBits(enqIdx).srcState(j) & !LoadShouldCancel(Some(s0_enqBits(enqIdx).srcLoadDependency(j)), io.ldCancel) 239 enq.bits.status.srcStatus(j).dataSources.value := Mux( 240 SrcType.isXp(s0_enqBits(enqIdx).srcType(j)) && (s0_enqBits(enqIdx).psrc(j) === 0.U), 241 DataSource.zero, 242 Mux(SrcType.isNotReg(s0_enqBits(enqIdx).srcType(j)), DataSource.imm, DataSource.reg) 243 ) 244 enq.bits.status.srcStatus(j).srcLoadDependency := VecInit(s0_enqBits(enqIdx).srcLoadDependency(j).map(x => x(x.getWidth - 2, 0) << 1)) 245 if(params.hasIQWakeUp) { 246 enq.bits.status.srcStatus(j).srcWakeUpL1ExuOH.get := 0.U.asTypeOf(ExuVec()) 247 } 248 } 249 enq.bits.status.blocked := false.B 250 enq.bits.status.issued := false.B 251 enq.bits.status.firstIssue := false.B 252 enq.bits.status.issueTimer := "b11".U 253 enq.bits.status.deqPortIdx := 0.U 254 enq.bits.imm.foreach(_ := s0_enqBits(enqIdx).imm) 255 enq.bits.payload := s0_enqBits(enqIdx) 256 } 257 entriesIO.og0Resp.zipWithIndex.foreach { case (og0Resp, i) => 258 og0Resp := io.og0Resp(i) 259 } 260 entriesIO.og1Resp.zipWithIndex.foreach { case (og1Resp, i) => 261 og1Resp := io.og1Resp(i) 262 } 263 if (params.inVfSchd) { 264 entriesIO.og2Resp.get.zipWithIndex.foreach { case (og2Resp, i) => 265 og2Resp := io.og2Resp.get(i) 266 } 267 } 268 if (params.isLdAddrIQ || params.isHyAddrIQ) { 269 entriesIO.fromLoad.get.finalIssueResp.zipWithIndex.foreach { case (finalIssueResp, i) => 270 finalIssueResp := io.finalIssueResp.get(i) 271 } 272 entriesIO.fromLoad.get.memAddrIssueResp.zipWithIndex.foreach { case (memAddrIssueResp, i) => 273 memAddrIssueResp := io.memAddrIssueResp.get(i) 274 } 275 } 276 for(deqIdx <- 0 until params.numDeq) { 277 entriesIO.deqReady(deqIdx) := deqBeforeDly(deqIdx).ready 278 entriesIO.deqSelOH(deqIdx).valid := deqSelValidVec(deqIdx) 279 entriesIO.deqSelOH(deqIdx).bits := deqSelOHVec(deqIdx) 280 entriesIO.enqEntryOldestSel(deqIdx) := enqEntryOldestSel(deqIdx) 281 entriesIO.simpEntryOldestSel.foreach(_(deqIdx) := simpEntryOldestSel.get(deqIdx)) 282 entriesIO.compEntryOldestSel.foreach(_(deqIdx) := compEntryOldestSel.get(deqIdx)) 283 entriesIO.othersEntryOldestSel.foreach(_(deqIdx) := othersEntryOldestSel(deqIdx)) 284 entriesIO.subDeqRequest.foreach(_(deqIdx) := subDeqRequest.get) 285 entriesIO.subDeqSelOH.foreach(_(deqIdx) := subDeqSelOHVec.get(deqIdx)) 286 } 287 entriesIO.wakeUpFromWB := io.wakeupFromWB 288 entriesIO.wakeUpFromIQ := io.wakeupFromIQ 289 entriesIO.og0Cancel := io.og0Cancel 290 entriesIO.og1Cancel := io.og1Cancel 291 entriesIO.ldCancel := io.ldCancel 292 entriesIO.simpEntryDeqSelVec.foreach(_ := VecInit(simpEntryOldestSel.get.takeRight(params.numEnq).map(_.bits))) 293 //output 294 fuTypeVec := entriesIO.fuType 295 deqEntryVec := entriesIO.deqEntry 296 cancelDeqVec := entriesIO.cancelDeqVec 297 simpEntryEnqSelVec.foreach(_ := entriesIO.simpEntryEnqSelVec.get) 298 compEntryEnqSelVec.foreach(_ := entriesIO.compEntryEnqSelVec.get) 299 othersEntryEnqSelVec.foreach(_ := entriesIO.othersEntryEnqSelVec.get) 300 } 301 302 303 s0_enqSelValidVec := s0_enqValidVec.zip(io.enq).map{ case (enqValid, enq) => enqValid && enq.ready} 304 305 protected val commonAccept: UInt = Cat(fuTypeVec.map(fuType => 306 FuType.FuTypeOrR(fuType, commonFuCfgs.map(_.fuType)) 307 ).reverse) 308 309 // if deq port can accept the uop 310 protected val canAcceptVec: Seq[UInt] = deqFuCfgs.map { fuCfgs: Seq[FuConfig] => 311 Cat(fuTypeVec.map(fuType => 312 FuType.FuTypeOrR(fuType, fuCfgs.map(_.fuType)) 313 ).reverse) 314 } 315 316 protected val deqCanAcceptVec: Seq[IndexedSeq[Bool]] = deqFuCfgs.map { fuCfgs: Seq[FuConfig] => 317 fuTypeVec.map(fuType => 318 FuType.FuTypeOrR(fuType, fuCfgs.map(_.fuType))) 319 } 320 321 canIssueMergeAllBusy.zipWithIndex.foreach { case (merge, i) => 322 val mergeFuBusy = { 323 if (fuBusyTableWrite(i).nonEmpty) canIssueVec.asUInt & (~fuBusyTableMask(i)) 324 else canIssueVec.asUInt 325 } 326 val mergeIntWbBusy = { 327 if (intWbBusyTableRead(i).nonEmpty) mergeFuBusy & (~intWbBusyTableMask(i)) 328 else mergeFuBusy 329 } 330 val mergeVfWbBusy = { 331 if (vfWbBusyTableRead(i).nonEmpty) mergeIntWbBusy & (~vfWbBusyTableMask(i)) 332 else mergeIntWbBusy 333 } 334 merge := mergeVfWbBusy 335 } 336 337 deqCanIssue.zipWithIndex.foreach { case (req, i) => 338 req := canIssueMergeAllBusy(i) & VecInit(deqCanAcceptVec(i)).asUInt 339 } 340 dontTouch(fuTypeVec) 341 dontTouch(canIssueMergeAllBusy) 342 dontTouch(deqCanIssue) 343 344 if (params.numDeq == 2) { 345 require(params.deqFuSame || params.deqFuDiff, "The 2 deq ports need to be identical or completely different") 346 } 347 348 if (params.numDeq == 2 && params.deqFuSame) { 349 val subDeqPolicy = Module(new DeqPolicy()) 350 351 enqEntryOldestSel := DontCare 352 353 if (params.isAllComp || params.isAllSimp) { 354 othersEntryOldestSel(0) := AgeDetector(numEntries = params.numEntries - params.numEnq, 355 enq = othersEntryEnqSelVec.get, 356 canIssue = canIssueVec.asUInt(params.numEntries-1, params.numEnq) 357 ) 358 othersEntryOldestSel(1) := DontCare 359 360 subDeqPolicy.io.request := subDeqRequest.get 361 subDeqSelValidVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => oh.valid) 362 subDeqSelOHVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => oh.bits) 363 } 364 else { 365 simpAgeDetectRequest.get(0) := canIssueVec.asUInt(params.numEnq + params.numSimp - 1, params.numEnq) 366 simpAgeDetectRequest.get(1) := DontCare 367 simpAgeDetectRequest.get(params.numDeq) := VecInit(validVec.drop(params.numEnq).take(params.numSimp)).asUInt 368 if (params.numEnq == 2) { 369 simpAgeDetectRequest.get(params.numDeq + 1) := VecInit(validVec.drop(params.numEnq).take(params.numSimp)).asUInt & ~simpEntryOldestSel.get(params.numDeq).bits 370 } 371 372 simpEntryOldestSel.get := AgeDetector(numEntries = params.numSimp, 373 enq = simpEntryEnqSelVec.get, 374 canIssue = simpAgeDetectRequest.get 375 ) 376 377 compEntryOldestSel.get(0) := AgeDetector(numEntries = params.numComp, 378 enq = compEntryEnqSelVec.get, 379 canIssue = canIssueVec.asUInt(params.numEntries - 1, params.numEnq + params.numSimp) 380 ) 381 compEntryOldestSel.get(1) := DontCare 382 383 othersEntryOldestSel(0).valid := compEntryOldestSel.get(0).valid || simpEntryOldestSel.get(0).valid 384 othersEntryOldestSel(0).bits := Cat( 385 compEntryOldestSel.get(0).bits, 386 Fill(params.numSimp, !compEntryOldestSel.get(0).valid) & simpEntryOldestSel.get(0).bits, 387 ) 388 othersEntryOldestSel(1) := DontCare 389 390 subDeqPolicy.io.request := Reverse(subDeqRequest.get) 391 subDeqSelValidVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => oh.valid) 392 subDeqSelOHVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => Reverse(oh.bits)) 393 } 394 395 subDeqRequest.get := canIssueVec.asUInt & ~Cat(othersEntryOldestSel(0).bits, 0.U((params.numEnq).W)) 396 397 deqSelValidVec(0) := othersEntryOldestSel(0).valid || subDeqSelValidVec.get(1) 398 deqSelValidVec(1) := subDeqSelValidVec.get(0) 399 deqSelOHVec(0) := Mux(othersEntryOldestSel(0).valid, 400 Cat(othersEntryOldestSel(0).bits, 0.U((params.numEnq).W)), 401 subDeqSelOHVec.get(1)) & canIssueMergeAllBusy(0) 402 deqSelOHVec(1) := subDeqSelOHVec.get(0) & canIssueMergeAllBusy(1) 403 404 finalDeqSelValidVec.zip(finalDeqSelOHVec).zip(deqSelValidVec).zip(deqSelOHVec).zipWithIndex.foreach { case ((((selValid, selOH), deqValid), deqOH), i) => 405 selValid := deqValid && deqOH.orR && deqBeforeDly(i).ready 406 selOH := deqOH 407 } 408 } 409 else { 410 enqEntryOldestSel := NewAgeDetector(numEntries = params.numEnq, 411 enq = VecInit(s0_doEnqSelValidVec), 412 canIssue = VecInit(deqCanIssue.map(_(params.numEnq - 1, 0))) 413 ) 414 415 if (params.isAllComp || params.isAllSimp) { 416 othersEntryOldestSel := AgeDetector(numEntries = params.numEntries - params.numEnq, 417 enq = othersEntryEnqSelVec.get, 418 canIssue = VecInit(deqCanIssue.map(_(params.numEntries - 1, params.numEnq))) 419 ) 420 421 deqSelValidVec.zip(deqSelOHVec).zipWithIndex.foreach { case ((selValid, selOH), i) => 422 if (params.exuBlockParams(i).fuConfigs.contains(FuConfig.FakeHystaCfg)) { 423 selValid := false.B 424 selOH := 0.U.asTypeOf(selOH) 425 } else { 426 selValid := othersEntryOldestSel(i).valid || enqEntryOldestSel(i).valid 427 selOH := Cat(othersEntryOldestSel(i).bits, Fill(params.numEnq, !othersEntryOldestSel(i).valid) & enqEntryOldestSel(i).bits) 428 } 429 } 430 } 431 else { 432 othersEntryOldestSel := DontCare 433 434 deqCanIssue.zipWithIndex.foreach { case (req, i) => 435 simpAgeDetectRequest.get(i) := req(params.numEnq + params.numSimp - 1, params.numEnq) 436 } 437 simpAgeDetectRequest.get(params.numDeq) := VecInit(validVec.drop(params.numEnq).take(params.numSimp)).asUInt 438 if (params.numEnq == 2) { 439 simpAgeDetectRequest.get(params.numDeq + 1) := VecInit(validVec.drop(params.numEnq).take(params.numSimp)).asUInt & ~simpEntryOldestSel.get(params.numDeq).bits 440 } 441 442 simpEntryOldestSel.get := AgeDetector(numEntries = params.numSimp, 443 enq = simpEntryEnqSelVec.get, 444 canIssue = simpAgeDetectRequest.get 445 ) 446 447 compEntryOldestSel.get := AgeDetector(numEntries = params.numComp, 448 enq = compEntryEnqSelVec.get, 449 canIssue = VecInit(deqCanIssue.map(_(params.numEntries - 1, params.numEnq + params.numSimp))) 450 ) 451 452 deqSelValidVec.zip(deqSelOHVec).zipWithIndex.foreach { case ((selValid, selOH), i) => 453 if (params.exuBlockParams(i).fuConfigs.contains(FuConfig.FakeHystaCfg)) { 454 selValid := false.B 455 selOH := 0.U.asTypeOf(selOH) 456 } else { 457 selValid := compEntryOldestSel.get(i).valid || simpEntryOldestSel.get(i).valid || enqEntryOldestSel(i).valid 458 selOH := Cat( 459 compEntryOldestSel.get(i).bits, 460 Fill(params.numSimp, !compEntryOldestSel.get(i).valid) & simpEntryOldestSel.get(i).bits, 461 Fill(params.numEnq, !compEntryOldestSel.get(i).valid && !simpEntryOldestSel.get(i).valid) & enqEntryOldestSel(i).bits 462 ) 463 } 464 } 465 } 466 467 finalDeqSelValidVec.zip(finalDeqSelOHVec).zip(deqSelValidVec).zip(deqSelOHVec).zipWithIndex.foreach { case ((((selValid, selOH), deqValid), deqOH), i) => 468 selValid := deqValid && deqBeforeDly(i).ready 469 selOH := deqOH 470 } 471 } 472 473 val toBusyTableDeqResp = Wire(Vec(params.numDeq, ValidIO(new IssueQueueDeqRespBundle))) 474 475 toBusyTableDeqResp.zipWithIndex.foreach { case (deqResp, i) => 476 deqResp.valid := finalDeqSelValidVec(i) 477 deqResp.bits.resp := RespType.success 478 deqResp.bits.robIdx := DontCare 479 deqResp.bits.fuType := deqBeforeDly(i).bits.common.fuType 480 deqResp.bits.uopIdx.foreach(_ := DontCare) 481 } 482 483 //fuBusyTable 484 fuBusyTableWrite.zip(fuBusyTableRead).zipWithIndex.foreach { case ((busyTableWrite: Option[FuBusyTableWrite], busyTableRead: Option[FuBusyTableRead]), i) => 485 if(busyTableWrite.nonEmpty) { 486 val btwr = busyTableWrite.get 487 val btrd = busyTableRead.get 488 btwr.io.in.deqResp := toBusyTableDeqResp(i) 489 btwr.io.in.og0Resp := io.og0Resp(i) 490 btwr.io.in.og1Resp := io.og1Resp(i) 491 btrd.io.in.fuBusyTable := btwr.io.out.fuBusyTable 492 btrd.io.in.fuTypeRegVec := fuTypeVec 493 fuBusyTableMask(i) := btrd.io.out.fuBusyTableMask 494 } 495 else { 496 fuBusyTableMask(i) := 0.U(params.numEntries.W) 497 } 498 } 499 500 //wbfuBusyTable write 501 intWbBusyTableWrite.zip(intWbBusyTableOut).zip(intDeqRespSetOut).zipWithIndex.foreach { case (((busyTableWrite: Option[FuBusyTableWrite], busyTable: Option[UInt]), deqResp), i) => 502 if(busyTableWrite.nonEmpty) { 503 val btwr = busyTableWrite.get 504 val bt = busyTable.get 505 val dq = deqResp.get 506 btwr.io.in.deqResp := toBusyTableDeqResp(i) 507 btwr.io.in.og0Resp := io.og0Resp(i) 508 btwr.io.in.og1Resp := io.og1Resp(i) 509 bt := btwr.io.out.fuBusyTable 510 dq := btwr.io.out.deqRespSet 511 } 512 } 513 514 vfWbBusyTableWrite.zip(vfWbBusyTableOut).zip(vfDeqRespSetOut).zipWithIndex.foreach { case (((busyTableWrite: Option[FuBusyTableWrite], busyTable: Option[UInt]), deqResp), i) => 515 if (busyTableWrite.nonEmpty) { 516 val btwr = busyTableWrite.get 517 val bt = busyTable.get 518 val dq = deqResp.get 519 btwr.io.in.deqResp := toBusyTableDeqResp(i) 520 btwr.io.in.og0Resp := io.og0Resp(i) 521 btwr.io.in.og1Resp := io.og1Resp(i) 522 bt := btwr.io.out.fuBusyTable 523 dq := btwr.io.out.deqRespSet 524 } 525 } 526 527 //wbfuBusyTable read 528 intWbBusyTableRead.zip(intWbBusyTableIn).zipWithIndex.foreach { case ((busyTableRead: Option[FuBusyTableRead], busyTable: Option[UInt]), i) => 529 if(busyTableRead.nonEmpty) { 530 val btrd = busyTableRead.get 531 val bt = busyTable.get 532 btrd.io.in.fuBusyTable := bt 533 btrd.io.in.fuTypeRegVec := fuTypeVec 534 intWbBusyTableMask(i) := btrd.io.out.fuBusyTableMask 535 } 536 else { 537 intWbBusyTableMask(i) := 0.U(params.numEntries.W) 538 } 539 } 540 vfWbBusyTableRead.zip(vfWbBusyTableIn).zipWithIndex.foreach { case ((busyTableRead: Option[FuBusyTableRead], busyTable: Option[UInt]), i) => 541 if (busyTableRead.nonEmpty) { 542 val btrd = busyTableRead.get 543 val bt = busyTable.get 544 btrd.io.in.fuBusyTable := bt 545 btrd.io.in.fuTypeRegVec := fuTypeVec 546 vfWbBusyTableMask(i) := btrd.io.out.fuBusyTableMask 547 } 548 else { 549 vfWbBusyTableMask(i) := 0.U(params.numEntries.W) 550 } 551 } 552 553 wakeUpQueues.zipWithIndex.foreach { case (wakeUpQueueOption, i) => 554 wakeUpQueueOption.foreach { 555 wakeUpQueue => 556 val flush = Wire(new WakeupQueueFlush) 557 flush.redirect := io.flush 558 flush.ldCancel := io.ldCancel 559 flush.og0Fail := io.og0Resp(i).valid && RespType.isBlocked(io.og0Resp(i).bits.resp) 560 flush.og1Fail := io.og1Resp(i).valid && RespType.isBlocked(io.og1Resp(i).bits.resp) 561 wakeUpQueue.io.flush := flush 562 wakeUpQueue.io.enq.valid := deqBeforeDly(i).valid 563 wakeUpQueue.io.enq.bits.uop :<= deqBeforeDly(i).bits.common 564 wakeUpQueue.io.enq.bits.uop.pdestCopy.foreach(_ := 0.U) 565 wakeUpQueue.io.enq.bits.lat := getDeqLat(i, deqBeforeDly(i).bits.common.fuType) 566 } 567 } 568 569 deqBeforeDly.zipWithIndex.foreach { case (deq, i) => 570 deq.valid := finalDeqSelValidVec(i) && !cancelDeqVec(i) 571 deq.bits.addrOH := finalDeqSelOHVec(i) 572 deq.bits.common.isFirstIssue := deqFirstIssueVec(i) 573 deq.bits.common.iqIdx := OHToUInt(finalDeqSelOHVec(i)) 574 deq.bits.common.fuType := IQFuType.readFuType(deqEntryVec(i).bits.status.fuType, params.getFuCfgs.map(_.fuType)).asUInt 575 deq.bits.common.fuOpType := deqEntryVec(i).bits.payload.fuOpType 576 deq.bits.common.rfWen.foreach(_ := deqEntryVec(i).bits.payload.rfWen) 577 deq.bits.common.fpWen.foreach(_ := deqEntryVec(i).bits.payload.fpWen) 578 deq.bits.common.vecWen.foreach(_ := deqEntryVec(i).bits.payload.vecWen) 579 deq.bits.common.flushPipe.foreach(_ := deqEntryVec(i).bits.payload.flushPipe) 580 deq.bits.common.pdest := deqEntryVec(i).bits.payload.pdest 581 deq.bits.common.robIdx := deqEntryVec(i).bits.status.robIdx 582 583 require(deq.bits.common.dataSources.size <= finalDataSources(i).size) 584 deq.bits.common.dataSources.zip(finalDataSources(i)).foreach { case (sink, source) => sink := source} 585 deq.bits.common.l1ExuOH.foreach(_ := finalWakeUpL1ExuOH.get(i)) 586 deq.bits.common.srcTimer.foreach(_ := DontCare) 587 deq.bits.common.loadDependency.foreach(_ := finalLoadDependency(i)) 588 deq.bits.common.src := DontCare 589 deq.bits.common.preDecode.foreach(_ := deqEntryVec(i).bits.payload.preDecodeInfo) 590 591 deq.bits.rf.zip(deqEntryVec(i).bits.status.srcStatus.map(_.psrc)).zip(deqEntryVec(i).bits.status.srcStatus.map(_.srcType)).foreach { case ((rf, psrc), srcType) => 592 // psrc in status array can be pregIdx of IntRegFile or VfRegFile 593 rf.foreach(_.addr := psrc) 594 rf.foreach(_.srcType := srcType) 595 } 596 deq.bits.srcType.zip(deqEntryVec(i).bits.status.srcStatus.map(_.srcType)).foreach { case (sink, source) => 597 sink := source 598 } 599 deq.bits.immType := deqEntryVec(i).bits.payload.selImm 600 deq.bits.common.imm := deqEntryVec(i).bits.imm.getOrElse(0.U) 601 602 deq.bits.common.perfDebugInfo := deqEntryVec(i).bits.payload.debugInfo 603 deq.bits.common.perfDebugInfo.selectTime := GTimer() 604 deq.bits.common.perfDebugInfo.issueTime := GTimer() + 1.U 605 } 606 607 private val deqShift = WireDefault(deqBeforeDly) 608 deqShift.zip(deqBeforeDly).foreach { 609 case (shifted, original) => 610 original.ready := shifted.ready // this will not cause combinational loop 611 shifted.bits.common.loadDependency.foreach( 612 _ := original.bits.common.loadDependency.get.map(_ << 1) 613 ) 614 } 615 io.deqDelay.zip(deqShift).foreach { case (deqDly, deq) => 616 NewPipelineConnect( 617 deq, deqDly, deqDly.valid, 618 false.B, 619 Option("Scheduler2DataPathPipe") 620 ) 621 } 622 if(backendParams.debugEn) { 623 dontTouch(io.deqDelay) 624 } 625 io.wakeupToIQ.zipWithIndex.foreach { case (wakeup, i) => 626 if (wakeUpQueues(i).nonEmpty && finalWakeUpL1ExuOH.nonEmpty) { 627 wakeup.valid := wakeUpQueues(i).get.io.deq.valid 628 wakeup.bits.fromExuInput(wakeUpQueues(i).get.io.deq.bits, finalWakeUpL1ExuOH.get(i)) 629 wakeup.bits.loadDependency := wakeUpQueues(i).get.io.deq.bits.loadDependency.getOrElse(0.U.asTypeOf(wakeup.bits.loadDependency)) 630 wakeup.bits.is0Lat := getDeqLat(i, wakeUpQueues(i).get.io.deq.bits.fuType) === 0.U 631 } else if (wakeUpQueues(i).nonEmpty) { 632 wakeup.valid := wakeUpQueues(i).get.io.deq.valid 633 wakeup.bits.fromExuInput(wakeUpQueues(i).get.io.deq.bits) 634 wakeup.bits.loadDependency := wakeUpQueues(i).get.io.deq.bits.loadDependency.getOrElse(0.U.asTypeOf(wakeup.bits.loadDependency)) 635 wakeup.bits.is0Lat := getDeqLat(i, wakeUpQueues(i).get.io.deq.bits.fuType) === 0.U 636 } else { 637 wakeup.valid := false.B 638 wakeup.bits := 0.U.asTypeOf(wakeup.bits) 639 wakeup.bits.is0Lat := 0.U 640 } 641 if (wakeUpQueues(i).nonEmpty) { 642 wakeup.bits.rfWen := (if (wakeUpQueues(i).get.io.deq.bits.rfWen .nonEmpty) wakeUpQueues(i).get.io.deq.valid && wakeUpQueues(i).get.io.deq.bits.rfWen .get else false.B) 643 wakeup.bits.fpWen := (if (wakeUpQueues(i).get.io.deq.bits.fpWen .nonEmpty) wakeUpQueues(i).get.io.deq.valid && wakeUpQueues(i).get.io.deq.bits.fpWen .get else false.B) 644 wakeup.bits.vecWen := (if (wakeUpQueues(i).get.io.deq.bits.vecWen.nonEmpty) wakeUpQueues(i).get.io.deq.valid && wakeUpQueues(i).get.io.deq.bits.vecWen.get else false.B) 645 } 646 647 if(wakeUpQueues(i).nonEmpty && wakeup.bits.pdestCopy.nonEmpty){ 648 wakeup.bits.pdestCopy.get := wakeUpQueues(i).get.io.deq.bits.pdestCopy.get 649 } 650 if (wakeUpQueues(i).nonEmpty && wakeup.bits.rfWenCopy.nonEmpty) { 651 wakeup.bits.rfWenCopy.get := wakeUpQueues(i).get.io.deq.bits.rfWenCopy.get 652 } 653 if (wakeUpQueues(i).nonEmpty && wakeup.bits.fpWenCopy.nonEmpty) { 654 wakeup.bits.fpWenCopy.get := wakeUpQueues(i).get.io.deq.bits.fpWenCopy.get 655 } 656 if (wakeUpQueues(i).nonEmpty && wakeup.bits.vecWenCopy.nonEmpty) { 657 wakeup.bits.vecWenCopy.get := wakeUpQueues(i).get.io.deq.bits.vecWenCopy.get 658 } 659 if (wakeUpQueues(i).nonEmpty && wakeup.bits.loadDependencyCopy.nonEmpty) { 660 wakeup.bits.loadDependencyCopy.get := wakeUpQueues(i).get.io.deq.bits.loadDependencyCopy.get 661 } 662 } 663 664 // Todo: better counter implementation 665 private val enqHasValid = validVec.take(params.numEnq).reduce(_ | _) 666 private val enqEntryValidCnt = PopCount(validVec.take(params.numEnq)) 667 private val othersValidCnt = PopCount(validVec.drop(params.numEnq)) 668 private val enqEntryValidCntDeq0 = PopCount( 669 validVec.take(params.numEnq).zip(deqCanAcceptVec(0).take(params.numEnq)).map { case (a, b) => a && b } 670 ) 671 private val othersValidCntDeq0 = PopCount( 672 validVec.drop(params.numEnq).zip(deqCanAcceptVec(0).drop(params.numEnq)).map { case (a, b) => a && b } 673 ) 674 private val enqEntryValidCntDeq1 = PopCount( 675 validVec.take(params.numEnq).zip(deqCanAcceptVec.last.take(params.numEnq)).map { case (a, b) => a && b } 676 ) 677 private val othersValidCntDeq1 = PopCount( 678 validVec.drop(params.numEnq).zip(deqCanAcceptVec.last.drop(params.numEnq)).map { case (a, b) => a && b } 679 ) 680 protected val deqCanAcceptVecEnq: Seq[IndexedSeq[Bool]] = deqFuCfgs.map { fuCfgs: Seq[FuConfig] => 681 io.enq.map(_.bits.fuType).map(fuType => 682 FuType.FuTypeOrR(fuType, fuCfgs.map(_.fuType))) 683 } 684 protected val enqValidCntDeq0 = PopCount(io.enq.map(_.fire).zip(deqCanAcceptVecEnq(0)).map { case (a, b) => a && b }) 685 protected val enqValidCntDeq1 = PopCount(io.enq.map(_.fire).zip(deqCanAcceptVecEnq.last).map { case (a, b) => a && b }) 686 io.validCntDeqVec.head := RegNext(enqEntryValidCntDeq0 +& othersValidCntDeq0 - io.deqDelay.head.fire) // validCntDeqVec(0) 687 io.validCntDeqVec.last := RegNext(enqEntryValidCntDeq1 +& othersValidCntDeq1 - io.deqDelay.last.fire) // validCntDeqVec(1) 688 io.status.leftVec(0) := validVec.drop(params.numEnq).reduce(_ & _) 689 for (i <- 0 until params.numEnq) { 690 io.status.leftVec(i + 1) := othersValidCnt === (params.numEntries - params.numEnq - (i + 1)).U 691 } 692 private val othersLeftOneCaseVec = Wire(Vec(params.numEntries - params.numEnq, UInt((params.numEntries - params.numEnq).W))) 693 othersLeftOneCaseVec.zipWithIndex.foreach { case (leftone, i) => 694 leftone := ~(1.U((params.numEntries - params.numEnq).W) << i) 695 } 696 private val othersLeftOne = othersLeftOneCaseVec.map(_ === VecInit(validVec.drop(params.numEnq)).asUInt).reduce(_ | _) 697 private val othersCanotIn = othersLeftOne || validVec.drop(params.numEnq).reduce(_ & _) 698 699 io.enq.foreach(_.ready := !othersCanotIn || !enqHasValid) 700 io.status.empty := !Cat(validVec).orR 701 io.status.full := othersCanotIn 702 io.status.validCnt := PopCount(validVec) 703 704 protected def getDeqLat(deqPortIdx: Int, fuType: UInt) : UInt = { 705 Mux1H(wakeupFuLatencyMaps(deqPortIdx) map { case (k, v) => (fuType(k.id), v.U) }) 706 } 707 708 // issue perf counter 709 // enq count 710 XSPerfAccumulate("enq_valid_cnt", PopCount(io.enq.map(_.fire))) 711 XSPerfAccumulate("enq_fire_cnt", PopCount(io.enq.map(_.fire))) 712 XSPerfAccumulate("enq_alu_fire_cnt", PopCount(io.enq.map { case enq => enq.fire && FuType.isAlu(enq.bits.fuType) })) 713 XSPerfAccumulate("enq_brh_fire_cnt", PopCount(io.enq.map { case enq => enq.fire && FuType.isBrh(enq.bits.fuType) })) 714 XSPerfAccumulate("deqDelay0_fire_cnt", PopCount(io.deqDelay.head.fire)) 715 XSPerfAccumulate("deqDelay1_fire_cnt", PopCount(io.deqDelay.last.fire)) 716 // valid count 717 XSPerfHistogram("enq_entry_valid_cnt", enqEntryValidCnt, true.B, 0, params.numEnq + 1) 718 XSPerfHistogram("other_entry_valid_cnt", othersValidCnt, true.B, 0, params.numEntries - params.numEnq + 1) 719 XSPerfHistogram("valid_cnt", PopCount(validVec), true.B, 0, params.numEntries + 1) 720 // only split when more than 1 func type 721 if (params.getFuCfgs.size > 0) { 722 for (t <- FuType.functionNameMap.keys) { 723 val fuName = FuType.functionNameMap(t) 724 if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _)) { 725 XSPerfHistogram(s"valid_cnt_hist_futype_${fuName}", PopCount(validVec.zip(fuTypeVec).map { case (v, fu) => v && fu === t.U }), true.B, 0, params.numEntries, 1) 726 } 727 } 728 } 729 // ready instr count 730 private val readyEntriesCnt = PopCount(validVec.zip(canIssueVec).map(x => x._1 && x._2)) 731 XSPerfHistogram("ready_cnt", readyEntriesCnt, true.B, 0, params.numEntries + 1) 732 // only split when more than 1 func type 733 if (params.getFuCfgs.size > 0) { 734 for (t <- FuType.functionNameMap.keys) { 735 val fuName = FuType.functionNameMap(t) 736 if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _)) { 737 XSPerfHistogram(s"ready_cnt_hist_futype_${fuName}", PopCount(validVec.zip(canIssueVec).zip(fuTypeVec).map { case ((v, c), fu) => v && c && fu === t.U }), true.B, 0, params.numEntries, 1) 738 } 739 } 740 } 741 742 // deq instr count 743 XSPerfAccumulate("issue_instr_pre_count", PopCount(deqBeforeDly.map(_.valid))) 744 XSPerfHistogram("issue_instr_pre_count_hist", PopCount(deqBeforeDly.map(_.valid)), true.B, 0, params.numDeq + 1, 1) 745 XSPerfAccumulate("issue_instr_count", PopCount(io.deqDelay.map(_.valid))) 746 XSPerfHistogram("issue_instr_count_hist", PopCount(io.deqDelay.map(_.valid)), true.B, 0, params.numDeq + 1, 1) 747 748 // deq instr data source count 749 XSPerfAccumulate("issue_datasource_reg", deqBeforeDly.map{ deq => 750 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) }) 751 }.reduce(_ +& _)) 752 XSPerfAccumulate("issue_datasource_bypass", deqBeforeDly.map{ deq => 753 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) }) 754 }.reduce(_ +& _)) 755 XSPerfAccumulate("issue_datasource_forward", deqBeforeDly.map{ deq => 756 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) }) 757 }.reduce(_ +& _)) 758 XSPerfAccumulate("issue_datasource_noreg", deqBeforeDly.map{ deq => 759 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) }) 760 }.reduce(_ +& _)) 761 762 XSPerfHistogram("issue_datasource_reg_hist", deqBeforeDly.map{ deq => 763 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) }) 764 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 765 XSPerfHistogram("issue_datasource_bypass_hist", deqBeforeDly.map{ deq => 766 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) }) 767 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 768 XSPerfHistogram("issue_datasource_forward_hist", deqBeforeDly.map{ deq => 769 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) }) 770 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 771 XSPerfHistogram("issue_datasource_noreg_hist", deqBeforeDly.map{ deq => 772 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) }) 773 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 774 775 // deq instr data source count for each futype 776 for (t <- FuType.functionNameMap.keys) { 777 val fuName = FuType.functionNameMap(t) 778 if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _)) { 779 XSPerfAccumulate(s"issue_datasource_reg_futype_${fuName}", deqBeforeDly.map{ deq => 780 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 781 }.reduce(_ +& _)) 782 XSPerfAccumulate(s"issue_datasource_bypass_futype_${fuName}", deqBeforeDly.map{ deq => 783 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 784 }.reduce(_ +& _)) 785 XSPerfAccumulate(s"issue_datasource_forward_futype_${fuName}", deqBeforeDly.map{ deq => 786 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 787 }.reduce(_ +& _)) 788 XSPerfAccumulate(s"issue_datasource_noreg_futype_${fuName}", deqBeforeDly.map{ deq => 789 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 790 }.reduce(_ +& _)) 791 792 XSPerfHistogram(s"issue_datasource_reg_hist_futype_${fuName}", deqBeforeDly.map{ deq => 793 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 794 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 795 XSPerfHistogram(s"issue_datasource_bypass_hist_futype_${fuName}", deqBeforeDly.map{ deq => 796 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 797 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 798 XSPerfHistogram(s"issue_datasource_forward_hist_futype_${fuName}", deqBeforeDly.map{ deq => 799 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 800 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 801 XSPerfHistogram(s"issue_datasource_noreg_hist_futype_${fuName}", deqBeforeDly.map{ deq => 802 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 803 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 804 } 805 } 806} 807 808class IssueQueueLoadBundle(implicit p: Parameters) extends XSBundle { 809 val fastMatch = UInt(backendParams.LduCnt.W) 810 val fastImm = UInt(12.W) 811} 812 813class IssueQueueIntIO()(implicit p: Parameters, params: IssueBlockParams) extends IssueQueueIO 814 815class IssueQueueIntImp(override val wrapper: IssueQueue)(implicit p: Parameters, iqParams: IssueBlockParams) 816 extends IssueQueueImp(wrapper) 817{ 818 io.suggestName("none") 819 override lazy val io = IO(new IssueQueueIntIO).suggestName("io") 820 821 deqBeforeDly.zipWithIndex.foreach{ case (deq, i) => { 822 deq.bits.common.pc.foreach(_ := DontCare) 823 deq.bits.common.preDecode.foreach(_ := deqEntryVec(i).bits.payload.preDecodeInfo) 824 deq.bits.common.ftqIdx.foreach(_ := deqEntryVec(i).bits.payload.ftqPtr) 825 deq.bits.common.ftqOffset.foreach(_ := deqEntryVec(i).bits.payload.ftqOffset) 826 deq.bits.common.predictInfo.foreach(x => { 827 x.target := DontCare 828 x.taken := deqEntryVec(i).bits.payload.pred_taken 829 }) 830 // for std 831 deq.bits.common.sqIdx.foreach(_ := deqEntryVec(i).bits.payload.sqIdx) 832 // for i2f 833 deq.bits.common.fpu.foreach(_ := deqEntryVec(i).bits.payload.fpu) 834 }} 835} 836 837class IssueQueueVfImp(override val wrapper: IssueQueue)(implicit p: Parameters, iqParams: IssueBlockParams) 838 extends IssueQueueImp(wrapper) 839{ 840 deqBeforeDly.zipWithIndex.foreach{ case (deq, i) => { 841 deq.bits.common.fpu.foreach(_ := deqEntryVec(i).bits.payload.fpu) 842 deq.bits.common.vpu.foreach(_ := deqEntryVec(i).bits.payload.vpu) 843 deq.bits.common.vpu.foreach(_.vuopIdx := deqEntryVec(i).bits.payload.uopIdx) 844 deq.bits.common.vpu.foreach(_.lastUop := deqEntryVec(i).bits.payload.lastUop) 845 }} 846} 847 848class IssueQueueMemBundle(implicit p: Parameters, params: IssueBlockParams) extends Bundle { 849 val feedbackIO = Flipped(Vec(params.numDeq, new MemRSFeedbackIO)) 850 851 // TODO: is still needed? 852 val checkWait = new Bundle { 853 val stIssuePtr = Input(new SqPtr) 854 val memWaitUpdateReq = Flipped(new MemWaitUpdateReq) 855 } 856 val loadFastMatch = Output(Vec(params.LdExuCnt, new IssueQueueLoadBundle)) 857 858 // load wakeup 859 val loadWakeUp = Input(Vec(params.LdExuCnt, ValidIO(new DynInst()))) 860 861 // vector 862 val sqDeqPtr = OptionWrapper(params.isVecMemIQ, Input(new SqPtr)) 863 val lqDeqPtr = OptionWrapper(params.isVecMemIQ, Input(new LqPtr)) 864} 865 866class IssueQueueMemIO(implicit p: Parameters, params: IssueBlockParams) extends IssueQueueIO { 867 val memIO = Some(new IssueQueueMemBundle) 868} 869 870class IssueQueueMemAddrImp(override val wrapper: IssueQueue)(implicit p: Parameters, params: IssueBlockParams) 871 extends IssueQueueImp(wrapper) with HasCircularQueuePtrHelper { 872 873 require(params.StdCnt == 0 && (params.LduCnt + params.StaCnt + params.HyuCnt) > 0, "IssueQueueMemAddrImp can only be instance of MemAddr IQ, " + 874 s"StdCnt: ${params.StdCnt}, LduCnt: ${params.LduCnt}, StaCnt: ${params.StaCnt}, HyuCnt: ${params.HyuCnt}") 875 println(s"[IssueQueueMemAddrImp] StdCnt: ${params.StdCnt}, LduCnt: ${params.LduCnt}, StaCnt: ${params.StaCnt}, HyuCnt: ${params.HyuCnt}") 876 877 io.suggestName("none") 878 override lazy val io = IO(new IssueQueueMemIO).suggestName("io") 879 private val memIO = io.memIO.get 880 881 memIO.loadFastMatch := 0.U.asTypeOf(memIO.loadFastMatch) // TODO: is still needed? 882 883 entries.io.fromMem.get.slowResp.zipWithIndex.foreach { case (slowResp, i) => 884 slowResp.valid := memIO.feedbackIO(i).feedbackSlow.valid 885 slowResp.bits.robIdx := memIO.feedbackIO(i).feedbackSlow.bits.robIdx 886 slowResp.bits.resp := Mux(memIO.feedbackIO(i).feedbackSlow.bits.hit, RespType.success, RespType.block) 887 slowResp.bits.fuType := DontCare 888 } 889 890 entries.io.fromMem.get.fastResp.zipWithIndex.foreach { case (fastResp, i) => 891 fastResp.valid := memIO.feedbackIO(i).feedbackFast.valid 892 fastResp.bits.robIdx := memIO.feedbackIO(i).feedbackFast.bits.robIdx 893 fastResp.bits.resp := Mux(memIO.feedbackIO(i).feedbackFast.bits.hit, RespType.success, RespType.block) 894 fastResp.bits.fuType := DontCare 895 } 896 897 // load wakeup 898 val loadWakeUpIter = memIO.loadWakeUp.iterator 899 io.wakeupToIQ.zip(params.exuBlockParams).zipWithIndex.foreach { case ((wakeup, param), i) => 900 if (param.hasLoadExu) { 901 require(wakeUpQueues(i).isEmpty) 902 val uop = loadWakeUpIter.next() 903 904 wakeup.valid := GatedValidRegNext(uop.fire) 905 wakeup.bits.rfWen := GatedValidRegNext(uop.bits.rfWen && uop.fire) 906 wakeup.bits.fpWen := GatedValidRegNext(uop.bits.fpWen && uop.fire) 907 wakeup.bits.vecWen := GatedValidRegNext(uop.bits.vecWen && uop.fire) 908 wakeup.bits.pdest := RegEnable(uop.bits.pdest, uop.fire) 909 wakeup.bits.loadDependency.foreach(_ := 0.U) // this is correct for load only 910 911 wakeup.bits.rfWenCopy .foreach(_.foreach(_ := GatedValidRegNext(uop.bits.rfWen && uop.fire))) 912 wakeup.bits.fpWenCopy .foreach(_.foreach(_ := GatedValidRegNext(uop.bits.fpWen && uop.fire))) 913 wakeup.bits.vecWenCopy.foreach(_.foreach(_ := GatedValidRegNext(uop.bits.vecWen && uop.fire))) 914 wakeup.bits.pdestCopy .foreach(_.foreach(_ := RegEnable(uop.bits.pdest, uop.fire))) 915 wakeup.bits.loadDependencyCopy.foreach(x => x := 0.U.asTypeOf(x)) // this is correct for load only 916 917 wakeup.bits.is0Lat := 0.U 918 } 919 } 920 require(!loadWakeUpIter.hasNext) 921 922 deqBeforeDly.zipWithIndex.foreach { case (deq, i) => 923 deq.bits.common.loadWaitBit.foreach(_ := deqEntryVec(i).bits.payload.loadWaitBit) 924 deq.bits.common.waitForRobIdx.foreach(_ := deqEntryVec(i).bits.payload.waitForRobIdx) 925 deq.bits.common.storeSetHit.foreach(_ := deqEntryVec(i).bits.payload.storeSetHit) 926 deq.bits.common.loadWaitStrict.foreach(_ := deqEntryVec(i).bits.payload.loadWaitStrict) 927 deq.bits.common.ssid.foreach(_ := deqEntryVec(i).bits.payload.ssid) 928 deq.bits.common.sqIdx.get := deqEntryVec(i).bits.payload.sqIdx 929 deq.bits.common.lqIdx.get := deqEntryVec(i).bits.payload.lqIdx 930 deq.bits.common.ftqIdx.foreach(_ := deqEntryVec(i).bits.payload.ftqPtr) 931 deq.bits.common.ftqOffset.foreach(_ := deqEntryVec(i).bits.payload.ftqOffset) 932 } 933} 934 935class IssueQueueVecMemImp(override val wrapper: IssueQueue)(implicit p: Parameters, params: IssueBlockParams) 936 extends IssueQueueImp(wrapper) with HasCircularQueuePtrHelper { 937 938 require((params.VlduCnt + params.VstuCnt) > 0, "IssueQueueVecMemImp can only be instance of VecMem IQ") 939 println(s"[IssueQueueVecMemImp] VlduCnt: ${params.VlduCnt}, VstuCnt: ${params.VstuCnt}") 940 941 io.suggestName("none") 942 override lazy val io = IO(new IssueQueueMemIO).suggestName("io") 943 private val memIO = io.memIO.get 944 945 require(params.numExu == 1, "VecMem IssueQueue has not supported more than 1 deq ports") 946 947 def selectOldUop(robIdx: Seq[RobPtr], uopIdx: Seq[UInt], valid: Seq[Bool]): Vec[Bool] = { 948 val compareVec = (0 until robIdx.length).map(i => (0 until i).map(j => isAfter(robIdx(j), robIdx(i)) || (robIdx(j).value === robIdx(i).value && uopIdx(i) < uopIdx(j)))) 949 val resultOnehot = VecInit((0 until robIdx.length).map(i => Cat((0 until robIdx.length).map(j => 950 (if (j < i) !valid(j) || compareVec(i)(j) 951 else if (j == i) valid(i) 952 else !valid(j) || !compareVec(j)(i)) 953 )).andR)) 954 resultOnehot 955 } 956 957 val robIdxVec = entries.io.robIdx.get 958 val uopIdxVec = entries.io.uopIdx.get 959 val allEntryOldestOH = selectOldUop(robIdxVec, uopIdxVec, validVec) 960 961 deqSelValidVec.head := (allEntryOldestOH.asUInt & canIssueVec.asUInt).orR 962 deqSelOHVec.head := allEntryOldestOH.asUInt & canIssueVec.asUInt 963 finalDeqSelValidVec.head := (allEntryOldestOH.asUInt & canIssueVec.asUInt).orR && deqBeforeDly.head.ready 964 finalDeqSelOHVec.head := deqSelOHVec.head 965 966 for (i <- entries.io.enq.indices) { 967 entries.io.enq(i).bits.status match { case enqData => 968 enqData.vecMem.get.sqIdx := s0_enqBits(i).sqIdx 969 enqData.vecMem.get.lqIdx := s0_enqBits(i).lqIdx 970 971 // update blocked 972 val isLsqHead = { 973 s0_enqBits(i).lqIdx <= memIO.lqDeqPtr.get && 974 s0_enqBits(i).sqIdx <= memIO.sqDeqPtr.get 975 } 976 enqData.blocked := !isLsqHead 977 } 978 } 979 980 entries.io.fromMem.get.slowResp.zipWithIndex.foreach { case (slowResp, i) => 981 slowResp.valid := memIO.feedbackIO(i).feedbackSlow.valid 982 slowResp.bits.robIdx := memIO.feedbackIO(i).feedbackSlow.bits.robIdx 983 slowResp.bits.resp := Mux(memIO.feedbackIO(i).feedbackSlow.bits.hit, RespType.success, RespType.block) 984 slowResp.bits.fuType := DontCare 985 slowResp.bits.uopIdx.get := 0.U // Todo 986 } 987 988 entries.io.fromMem.get.fastResp.zipWithIndex.foreach { case (fastResp, i) => 989 fastResp.valid := memIO.feedbackIO(i).feedbackFast.valid 990 fastResp.bits.robIdx := memIO.feedbackIO(i).feedbackFast.bits.robIdx 991 fastResp.bits.resp := Mux(memIO.feedbackIO(i).feedbackFast.bits.hit, RespType.success, RespType.block) 992 fastResp.bits.fuType := DontCare 993 fastResp.bits.uopIdx.get := 0.U // Todo 994 } 995 996 entries.io.vecMemIn.get.sqDeqPtr := memIO.sqDeqPtr.get 997 entries.io.vecMemIn.get.lqDeqPtr := memIO.lqDeqPtr.get 998 999 1000 deqBeforeDly.zipWithIndex.foreach { case (deq, i) => 1001 deq.bits.common.sqIdx.foreach(_ := deqEntryVec(i).bits.status.vecMem.get.sqIdx) 1002 deq.bits.common.lqIdx.foreach(_ := deqEntryVec(i).bits.status.vecMem.get.lqIdx) 1003 if (params.isVecLduIQ) { 1004 deq.bits.common.ftqIdx.get := deqEntryVec(i).bits.payload.ftqPtr 1005 deq.bits.common.ftqOffset.get := deqEntryVec(i).bits.payload.ftqOffset 1006 } 1007 deq.bits.common.fpu.foreach(_ := deqEntryVec(i).bits.payload.fpu) 1008 deq.bits.common.vpu.foreach(_ := deqEntryVec(i).bits.payload.vpu) 1009 deq.bits.common.vpu.foreach(_.vuopIdx := deqEntryVec(i).bits.payload.uopIdx) 1010 deq.bits.common.vpu.foreach(_.lastUop := deqEntryVec(i).bits.payload.lastUop) 1011 } 1012} 1013