xref: /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala (revision 543f3ac74265a43b022517636afe32a8f55416fa) 
1package xiangshan.backend.issue
2
3import org.chipsalliance.cde.config.Parameters
4import chisel3._
5import chisel3.util._
6import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
7import utility.{GTimer, HasCircularQueuePtrHelper, SelectOne}
8import utils._
9import xiangshan._
10import xiangshan.backend.Bundles._
11import xiangshan.backend.decode.{ImmUnion, Imm_LUI_LOAD}
12import xiangshan.backend.datapath.DataConfig._
13import xiangshan.backend.datapath.DataSource
14import xiangshan.backend.fu.{FuConfig, FuType}
15import xiangshan.mem.{MemWaitUpdateReq, SqPtr, LqPtr}
16import xiangshan.backend.rob.RobPtr
17import xiangshan.backend.datapath.NewPipelineConnect
18
19class IssueQueue(params: IssueBlockParams)(implicit p: Parameters) extends LazyModule with HasXSParameter {
20  override def shouldBeInlined: Boolean = false
21
22  implicit val iqParams = params
23  lazy val module: IssueQueueImp = iqParams.schdType match {
24    case IntScheduler() => new IssueQueueIntImp(this)
25    case VfScheduler() => new IssueQueueVfImp(this)
26    case MemScheduler() =>
27      if (iqParams.StdCnt == 0 && !iqParams.isVecMemIQ) new IssueQueueMemAddrImp(this)
28      else if (iqParams.isVecMemIQ) new IssueQueueVecMemImp(this)
29      else new IssueQueueIntImp(this)
30    case _ => null
31  }
32}
33
34class IssueQueueStatusBundle(numEnq: Int, numEntries: Int) extends Bundle {
35  val empty = Output(Bool())
36  val full = Output(Bool())
37  val validCnt = Output(UInt(log2Ceil(numEntries).W))
38  val leftVec = Output(Vec(numEnq + 1, Bool()))
39}
40
41class IssueQueueDeqRespBundle(implicit p:Parameters, params: IssueBlockParams) extends EntryDeqRespBundle
42
43class IssueQueueIO()(implicit p: Parameters, params: IssueBlockParams) extends XSBundle {
44  // Inputs
45  val flush = Flipped(ValidIO(new Redirect))
46  val enq = Vec(params.numEnq, Flipped(DecoupledIO(new DynInst)))
47
48  val og0Resp = Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle)))
49  val og1Resp = Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle)))
50  val finalIssueResp = OptionWrapper(params.LdExuCnt > 0, Vec(params.LdExuCnt, Flipped(ValidIO(new IssueQueueDeqRespBundle))))
51  val memAddrIssueResp = OptionWrapper(params.LdExuCnt > 0, Vec(params.LdExuCnt, Flipped(ValidIO(new IssueQueueDeqRespBundle))))
52  val wbBusyTableRead = Input(params.genWbFuBusyTableReadBundle())
53  val wbBusyTableWrite = Output(params.genWbFuBusyTableWriteBundle())
54  val wakeupFromWB: MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = Flipped(params.genWBWakeUpSinkValidBundle)
55  val wakeupFromIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(params.genIQWakeUpSinkValidBundle)
56  val og0Cancel = Input(ExuOH(backendParams.numExu))
57  val og1Cancel = Input(ExuOH(backendParams.numExu))
58  val ldCancel = Vec(backendParams.LduCnt + backendParams.HyuCnt, Flipped(new LoadCancelIO))
59  val finalBlock = Vec(params.numExu, Input(Bool()))
60
61  // Outputs
62  val wakeupToIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = params.genIQWakeUpSourceValidBundle
63  val status = Output(new IssueQueueStatusBundle(params.numEnq, params.numEntries))
64  // val statusNext = Output(new IssueQueueStatusBundle(params.numEnq))
65
66  val deqDelay: MixedVec[DecoupledIO[IssueQueueIssueBundle]] = params.genIssueDecoupledBundle// = deq.cloneType
67  def allWakeUp = wakeupFromWB ++ wakeupFromIQ
68}
69
70class IssueQueueImp(override val wrapper: IssueQueue)(implicit p: Parameters, val params: IssueBlockParams)
71  extends LazyModuleImp(wrapper)
72  with HasXSParameter {
73
74  println(s"[IssueQueueImp] ${params.getIQName} wakeupFromWB(${io.wakeupFromWB.size}), " +
75    s"wakeup exu in(${params.wakeUpInExuSources.size}): ${params.wakeUpInExuSources.map(_.name).mkString("{",",","}")}, " +
76    s"wakeup exu out(${params.wakeUpOutExuSources.size}): ${params.wakeUpOutExuSources.map(_.name).mkString("{",",","}")}, " +
77    s"numEntries: ${params.numEntries}, numRegSrc: ${params.numRegSrc}")
78
79  require(params.numExu <= 2, "IssueQueue has not supported more than 2 deq ports")
80  val deqFuCfgs     : Seq[Seq[FuConfig]] = params.exuBlockParams.map(_.fuConfigs)
81  val allDeqFuCfgs  : Seq[FuConfig] = params.exuBlockParams.flatMap(_.fuConfigs)
82  val fuCfgsCnt     : Map[FuConfig, Int] = allDeqFuCfgs.groupBy(x => x).map { case (cfg, cfgSeq) => (cfg, cfgSeq.length) }
83  val commonFuCfgs  : Seq[FuConfig] = fuCfgsCnt.filter(_._2 > 1).keys.toSeq
84  val fuLatencyMaps : Seq[Map[FuType.OHType, Int]] = params.exuBlockParams.map(x => x.fuLatencyMap)
85
86  println(s"[IssueQueueImp] ${params.getIQName} fuLatencyMaps: ${fuLatencyMaps}")
87  println(s"[IssueQueueImp] ${params.getIQName} commonFuCfgs: ${commonFuCfgs.map(_.name)}")
88  lazy val io = IO(new IssueQueueIO())
89  // Modules
90
91  val entries = Module(new Entries)
92  val fuBusyTableWrite = params.exuBlockParams.map { case x => OptionWrapper(x.latencyValMax > 0, Module(new FuBusyTableWrite(x.fuLatencyMap))) }
93  val fuBusyTableRead = params.exuBlockParams.map { case x => OptionWrapper(x.latencyValMax > 0, Module(new FuBusyTableRead(x.fuLatencyMap))) }
94  val intWbBusyTableWrite = params.exuBlockParams.map { case x => OptionWrapper(x.intLatencyCertain, Module(new FuBusyTableWrite(x.intFuLatencyMap))) }
95  val intWbBusyTableRead = params.exuBlockParams.map { case x => OptionWrapper(x.intLatencyCertain, Module(new FuBusyTableRead(x.intFuLatencyMap))) }
96  val vfWbBusyTableWrite = params.exuBlockParams.map { case x => OptionWrapper(x.vfLatencyCertain, Module(new FuBusyTableWrite(x.vfFuLatencyMap))) }
97  val vfWbBusyTableRead = params.exuBlockParams.map { case x => OptionWrapper(x.vfLatencyCertain, Module(new FuBusyTableRead(x.vfFuLatencyMap))) }
98
99  class WakeupQueueFlush extends Bundle {
100    val redirect = ValidIO(new Redirect)
101    val ldCancel = Vec(backendParams.LduCnt + backendParams.HyuCnt, new LoadCancelIO)
102    val og0Fail = Output(Bool())
103    val og1Fail = Output(Bool())
104    val finalFail = Output(Bool())
105  }
106
107  private def flushFunc(exuInput: ExuInput, flush: WakeupQueueFlush, stage: Int): Bool = {
108    val redirectFlush = exuInput.robIdx.needFlush(flush.redirect)
109    val loadDependencyFlush = LoadShouldCancel(exuInput.loadDependency, flush.ldCancel)
110    val ogFailFlush = stage match {
111      case 1 => flush.og0Fail
112      case 2 => flush.og1Fail
113      case 3 => flush.finalFail
114      case _ => false.B
115    }
116    redirectFlush || loadDependencyFlush || ogFailFlush
117  }
118
119  private def modificationFunc(exuInput: ExuInput): ExuInput = {
120    val newExuInput = WireDefault(exuInput)
121    newExuInput.loadDependency match {
122      case Some(deps) => deps.zip(exuInput.loadDependency.get).foreach(x => x._1 := x._2 << 1)
123      case None =>
124    }
125    newExuInput
126  }
127
128  private def lastConnectFunc(exuInput: ExuInput, newInput: ExuInput): ExuInput = {
129    val lastExuInput = WireDefault(exuInput)
130    val newExuInput = WireDefault(newInput)
131    newExuInput.elements.foreach { case (name, data) =>
132      if (lastExuInput.elements.contains(name)) {
133        data := lastExuInput.elements(name)
134      }
135    }
136    if (newExuInput.pdestCopy.nonEmpty && !lastExuInput.pdestCopy.nonEmpty) {
137      newExuInput.pdestCopy.get.foreach(_ := lastExuInput.pdest)
138    }
139    newExuInput
140  }
141
142  val wakeUpQueues: Seq[Option[MultiWakeupQueue[ExuInput, WakeupQueueFlush]]] = params.exuBlockParams.map { x => OptionWrapper(x.isIQWakeUpSource, Module(
143    new MultiWakeupQueue(new ExuInput(x), new ExuInput(x, x.copyPdest, x.iqWakeUpSourcePairs.size / x.copyDistance), new WakeupQueueFlush, x.fuLatancySet, flushFunc, modificationFunc, lastConnectFunc)
144  ))}
145  val deqBeforeDly = Wire(params.genIssueDecoupledBundle)
146
147  val intWbBusyTableIn = io.wbBusyTableRead.map(_.intWbBusyTable)
148  val vfWbBusyTableIn = io.wbBusyTableRead.map(_.vfWbBusyTable)
149  val intWbBusyTableOut = io.wbBusyTableWrite.map(_.intWbBusyTable)
150  val vfWbBusyTableOut = io.wbBusyTableWrite.map(_.vfWbBusyTable)
151  val intDeqRespSetOut = io.wbBusyTableWrite.map(_.intDeqRespSet)
152  val vfDeqRespSetOut = io.wbBusyTableWrite.map(_.vfDeqRespSet)
153  val fuBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W)))
154  val intWbBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W)))
155  val vfWbBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W)))
156  val s0_enqValidVec = io.enq.map(_.valid)
157  val s0_enqSelValidVec = Wire(Vec(params.numEnq, Bool()))
158  val s0_enqNotFlush = !io.flush.valid
159  val s0_enqBits = WireInit(VecInit(io.enq.map(_.bits)))
160  val s0_doEnqSelValidVec = s0_enqSelValidVec.map(_ && s0_enqNotFlush) //enqValid && notFlush && enqReady
161
162
163  val finalDeqSelValidVec = Wire(Vec(params.numDeq, Bool()))
164  val finalDeqSelOHVec    = Wire(Vec(params.numDeq, UInt(params.numEntries.W)))
165
166  val validVec = VecInit(entries.io.valid.asBools)
167  val canIssueVec = VecInit(entries.io.canIssue.asBools)
168  val clearVec = VecInit(entries.io.clear.asBools)
169  val deqFirstIssueVec = VecInit(entries.io.deq.map(_.isFirstIssue))
170
171  val dataSources: Vec[Vec[DataSource]] = entries.io.dataSources
172  val finalDataSources: Vec[Vec[DataSource]] = VecInit(finalDeqSelOHVec.map(oh => Mux1H(oh, dataSources)))
173  // (entryIdx)(srcIdx)(exuIdx)
174  val wakeUpL1ExuOH: Option[Vec[Vec[UInt]]] = entries.io.srcWakeUpL1ExuOH
175  val srcTimer: Option[Vec[Vec[UInt]]] = entries.io.srcTimer
176
177  // (deqIdx)(srcIdx)(exuIdx)
178  val finalWakeUpL1ExuOH: Option[Vec[Vec[UInt]]] = wakeUpL1ExuOH.map(x => VecInit(finalDeqSelOHVec.map(oh => Mux1H(oh, x))))
179  val finalSrcTimer = srcTimer.map(x => VecInit(finalDeqSelOHVec.map(oh => Mux1H(oh, x))))
180
181  val fuTypeVec = Wire(Vec(params.numEntries, FuType()))
182  val transEntryDeqVec = Wire(Vec(params.numEnq, ValidIO(new EntryBundle)))
183  val deqEntryVec = Wire(Vec(params.numDeq, ValidIO(new EntryBundle)))
184  val transSelVec = Wire(Vec(params.numEnq, UInt((params.numEntries-params.numEnq).W)))
185  val canIssueMergeAllBusy = Wire(Vec(params.numDeq, UInt(params.numEntries.W)))
186  val deqCanIssue = Wire(Vec(params.numDeq, UInt(params.numEntries.W)))
187
188  val enqEntryOldestSel = Wire(Vec(params.numDeq, ValidIO(UInt(params.numEnq.W))))
189  val othersEntryOldestSel = Wire(Vec(params.numDeq, ValidIO(UInt((params.numEntries - params.numEnq).W))))
190  val deqSelValidVec = Wire(Vec(params.numDeq, Bool()))
191  val deqSelOHVec    = Wire(Vec(params.numDeq, UInt(params.numEntries.W)))
192  val cancelDeqVec = Wire(Vec(params.numDeq, Bool()))
193
194  val subDeqSelValidVec = OptionWrapper(params.deqFuSame, Wire(Vec(params.numDeq, Bool())))
195  val subDeqSelOHVec = OptionWrapper(params.deqFuSame, Wire(Vec(params.numDeq, UInt(params.numEntries.W))))
196  val subDeqRequest = OptionWrapper(params.deqFuSame, Wire(UInt(params.numEntries.W)))
197
198  /**
199    * Connection of [[entries]]
200    */
201  entries.io match { case entriesIO: EntriesIO =>
202    entriesIO.flush <> io.flush
203    entriesIO.wakeUpFromWB := io.wakeupFromWB
204    entriesIO.wakeUpFromIQ := io.wakeupFromIQ
205    entriesIO.og0Cancel := io.og0Cancel
206    entriesIO.og1Cancel := io.og1Cancel
207    entriesIO.ldCancel := io.ldCancel
208    entriesIO.enq.zipWithIndex.foreach { case (enq: ValidIO[EntryBundle], i) =>
209      enq.valid := s0_doEnqSelValidVec(i)
210      val numLsrc = s0_enqBits(i).srcType.size.min(enq.bits.status.srcType.size)
211      for (j <- 0 until numLsrc) {
212        enq.bits.status.srcState(j) := s0_enqBits(i).srcState(j) & !LoadShouldCancel(Some(s0_enqBits(i).srcLoadDependency(j)), io.ldCancel)
213        enq.bits.status.psrc(j) := s0_enqBits(i).psrc(j)
214        enq.bits.status.srcType(j) := s0_enqBits(i).srcType(j)
215        enq.bits.status.dataSources(j).value := DataSource.reg
216        enq.bits.payload.debugInfo.enqRsTime := GTimer()
217      }
218      enq.bits.status.fuType := IQFuType.readFuType(VecInit(s0_enqBits(i).fuType.asBools), params.getFuCfgs.map(_.fuType))
219      enq.bits.status.robIdx := s0_enqBits(i).robIdx
220      enq.bits.status.uopIdx.foreach(_ := s0_enqBits(i).uopIdx)
221      enq.bits.status.issueTimer := "b10".U
222      enq.bits.status.deqPortIdx := 0.U
223      enq.bits.status.issued := false.B
224      enq.bits.status.firstIssue := false.B
225      enq.bits.status.blocked := false.B
226
227      if (params.hasIQWakeUp) {
228        enq.bits.status.srcWakeUpL1ExuOH.get := 0.U.asTypeOf(enq.bits.status.srcWakeUpL1ExuOH.get)
229        enq.bits.status.srcTimer.get := 0.U.asTypeOf(enq.bits.status.srcTimer.get)
230        enq.bits.status.srcLoadDependency.foreach(_.zipWithIndex.foreach {
231          case (dep, srcIdx) =>
232            dep := VecInit(s0_enqBits(i).srcLoadDependency(srcIdx).map(x => x(x.getWidth - 2, 0) << 1))
233        })
234      }
235      if (params.inIntSchd && params.AluCnt > 0) {
236        // dirty code for lui+addi(w) fusion
237        val isLuiAddiFusion = s0_enqBits(i).isLUI32
238        val luiImm = Cat(s0_enqBits(i).lsrc(1), s0_enqBits(i).lsrc(0), s0_enqBits(i).imm(ImmUnion.maxLen - 1, 0))
239        enq.bits.imm.foreach(_ := Mux(isLuiAddiFusion, ImmUnion.LUI32.toImm32(luiImm), s0_enqBits(i).imm))
240      }
241      else if (params.inMemSchd && params.LduCnt > 0) {
242        // dirty code for fused_lui_load
243        val isLuiLoadFusion = SrcType.isNotReg(s0_enqBits(i).srcType(0)) && FuType.isLoad(s0_enqBits(i).fuType)
244        enq.bits.imm.foreach(_ := Mux(isLuiLoadFusion, Imm_LUI_LOAD().getLuiImm(s0_enqBits(i)), s0_enqBits(i).imm))
245      }
246      else {
247        enq.bits.imm.foreach(_ := s0_enqBits(i).imm)
248      }
249      enq.bits.payload := s0_enqBits(i)
250    }
251    entriesIO.deq.zipWithIndex.foreach { case (deq, i) =>
252      deq.enqEntryOldestSel := enqEntryOldestSel(i)
253      deq.othersEntryOldestSel := othersEntryOldestSel(i)
254      deq.subDeqRequest.foreach(_ := subDeqRequest.get)
255      deq.subDeqSelOH.foreach(_ := subDeqSelOHVec.get(i))
256      deq.deqReady := deqBeforeDly(i).ready
257      deq.deqSelOH.valid := deqSelValidVec(i)
258      deq.deqSelOH.bits := deqSelOHVec(i)
259    }
260    entriesIO.og0Resp.zipWithIndex.foreach { case (og0Resp, i) =>
261      og0Resp.valid := io.og0Resp(i).valid
262      og0Resp.bits.robIdx := io.og0Resp(i).bits.robIdx
263      og0Resp.bits.uopIdx := io.og0Resp(i).bits.uopIdx
264      og0Resp.bits.dataInvalidSqIdx := io.og0Resp(i).bits.dataInvalidSqIdx
265      og0Resp.bits.respType := io.og0Resp(i).bits.respType
266      og0Resp.bits.rfWen := io.og0Resp(i).bits.rfWen
267      og0Resp.bits.fuType := io.og0Resp(i).bits.fuType
268    }
269    entriesIO.og1Resp.zipWithIndex.foreach { case (og1Resp, i) =>
270      og1Resp.valid := io.og1Resp(i).valid
271      og1Resp.bits.robIdx := io.og1Resp(i).bits.robIdx
272      og1Resp.bits.uopIdx := io.og1Resp(i).bits.uopIdx
273      og1Resp.bits.dataInvalidSqIdx := io.og1Resp(i).bits.dataInvalidSqIdx
274      og1Resp.bits.respType := io.og1Resp(i).bits.respType
275      og1Resp.bits.rfWen := io.og1Resp(i).bits.rfWen
276      og1Resp.bits.fuType := io.og1Resp(i).bits.fuType
277    }
278    entriesIO.finalIssueResp.foreach(_.zipWithIndex.foreach { case (finalIssueResp, i) =>
279      finalIssueResp := io.finalIssueResp.get(i)
280    })
281    entriesIO.memAddrIssueResp.foreach(_.zipWithIndex.foreach { case (memAddrIssueResp, i) =>
282      memAddrIssueResp := io.memAddrIssueResp.get(i)
283    })
284    transEntryDeqVec := entriesIO.transEntryDeqVec
285    deqEntryVec := entriesIO.deq.map(_.deqEntry)
286    fuTypeVec := entriesIO.fuType
287    cancelDeqVec := entriesIO.cancelDeqVec
288    transSelVec := entriesIO.transSelVec
289  }
290
291
292  s0_enqSelValidVec := s0_enqValidVec.zip(io.enq).map{ case (enqValid, enq) => enqValid && enq.ready}
293
294  protected val commonAccept: UInt = Cat(fuTypeVec.map(fuType =>
295    FuType.FuTypeOrR(fuType, commonFuCfgs.map(_.fuType))
296  ).reverse)
297
298  // if deq port can accept the uop
299  protected val canAcceptVec: Seq[UInt] = deqFuCfgs.map { fuCfgs: Seq[FuConfig] =>
300    Cat(fuTypeVec.map(fuType =>
301      FuType.FuTypeOrR(fuType, fuCfgs.map(_.fuType))
302    ).reverse)
303  }
304
305  protected val deqCanAcceptVec: Seq[IndexedSeq[Bool]] = deqFuCfgs.map { fuCfgs: Seq[FuConfig] =>
306    fuTypeVec.map(fuType =>
307      FuType.FuTypeOrR(fuType, fuCfgs.map(_.fuType)))
308  }
309
310  canIssueMergeAllBusy.zipWithIndex.foreach { case (merge, i) =>
311    val mergeFuBusy = {
312      if (fuBusyTableWrite(i).nonEmpty) canIssueVec.asUInt & (~fuBusyTableMask(i))
313      else canIssueVec.asUInt
314    }
315    val mergeIntWbBusy = {
316      if (intWbBusyTableRead(i).nonEmpty) mergeFuBusy & (~intWbBusyTableMask(i))
317      else mergeFuBusy
318    }
319    val mergeVfWbBusy = {
320      if (vfWbBusyTableRead(i).nonEmpty) mergeIntWbBusy & (~vfWbBusyTableMask(i))
321      else mergeIntWbBusy
322    }
323    merge := mergeVfWbBusy
324  }
325
326  deqCanIssue.zipWithIndex.foreach { case (req, i) =>
327    req := canIssueMergeAllBusy(i) & VecInit(deqCanAcceptVec(i)).asUInt
328  }
329
330  if (params.numDeq == 2) {
331    require(params.deqFuSame || params.deqFuDiff, "The 2 deq ports need to be identical or completely different")
332  }
333
334  if (params.numDeq == 2 && params.deqFuSame) {
335    enqEntryOldestSel := DontCare
336
337    othersEntryOldestSel(0) := AgeDetector(numEntries = params.numEntries - params.numEnq,
338      enq = VecInit(transEntryDeqVec.zip(transSelVec).map{ case (transEntry, transSel) => Fill(params.numEntries-params.numEnq, transEntry.valid) & transSel }),
339      canIssue = canIssueVec.asUInt(params.numEntries-1, params.numEnq)
340    )
341    othersEntryOldestSel(1) := DontCare
342
343    subDeqRequest.get := canIssueVec.asUInt & ~Cat(othersEntryOldestSel(0).bits, 0.U((params.numEnq).W))
344
345    val subDeqPolicy = Module(new DeqPolicy())
346    subDeqPolicy.io.request := subDeqRequest.get
347    subDeqSelValidVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => oh.valid)
348    subDeqSelOHVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => oh.bits)
349
350    deqSelValidVec(0) := othersEntryOldestSel(0).valid || subDeqSelValidVec.get(1)
351    deqSelValidVec(1) := subDeqSelValidVec.get(0)
352    deqSelOHVec(0) := Mux(othersEntryOldestSel(0).valid,
353                          Cat(othersEntryOldestSel(0).bits, 0.U((params.numEnq).W)),
354                          subDeqSelOHVec.get(1)) & canIssueMergeAllBusy(0)
355    deqSelOHVec(1) := subDeqSelOHVec.get(0) & canIssueMergeAllBusy(1)
356
357    finalDeqSelValidVec.zip(finalDeqSelOHVec).zip(deqSelValidVec).zip(deqSelOHVec).zipWithIndex.foreach { case ((((selValid, selOH), deqValid), deqOH), i) =>
358      selValid := deqValid && deqOH.orR && deqBeforeDly(i).ready
359      selOH := deqOH
360    }
361  }
362  else {
363    enqEntryOldestSel := NewAgeDetector(numEntries = params.numEnq,
364      enq = VecInit(s0_doEnqSelValidVec),
365      canIssue = VecInit(deqCanIssue.map(_(params.numEnq-1, 0)))
366    )
367
368    othersEntryOldestSel := AgeDetector(numEntries = params.numEntries - params.numEnq,
369      enq = VecInit(transEntryDeqVec.zip(transSelVec).map{ case (transEntry, transSel) => Fill(params.numEntries-params.numEnq, transEntry.valid) & transSel }),
370      canIssue = VecInit(deqCanIssue.map(_(params.numEntries-1, params.numEnq)))
371    )
372
373    deqSelValidVec.zip(deqSelOHVec).zipWithIndex.foreach { case ((selValid, selOH), i) =>
374      if (params.exuBlockParams(i).fuConfigs.contains(FuConfig.FakeHystaCfg)) {
375        selValid := false.B
376        selOH := 0.U.asTypeOf(selOH)
377      } else {
378        selValid := othersEntryOldestSel(i).valid || enqEntryOldestSel(i).valid
379        selOH := Cat(othersEntryOldestSel(i).bits, Fill(params.numEnq, enqEntryOldestSel(i).valid && !othersEntryOldestSel(i).valid) & enqEntryOldestSel(i).bits)
380      }
381    }
382
383    finalDeqSelValidVec.zip(finalDeqSelOHVec).zip(deqSelValidVec).zip(deqSelOHVec).zipWithIndex.foreach { case ((((selValid, selOH), deqValid), deqOH), i) =>
384      selValid := deqValid && deqBeforeDly(i).ready
385      selOH := deqOH
386    }
387  }
388
389  val toBusyTableDeqResp = Wire(Vec(params.numDeq, ValidIO(new IssueQueueDeqRespBundle)))
390
391  toBusyTableDeqResp.zipWithIndex.foreach { case (deqResp, i) =>
392    deqResp.valid := finalDeqSelValidVec(i)
393    deqResp.bits.respType := RSFeedbackType.issueSuccess
394    deqResp.bits.robIdx := DontCare
395    deqResp.bits.dataInvalidSqIdx := DontCare
396    deqResp.bits.rfWen := DontCare
397    deqResp.bits.fuType := deqBeforeDly(i).bits.common.fuType
398    deqResp.bits.uopIdx := DontCare
399  }
400
401  //fuBusyTable
402  fuBusyTableWrite.zip(fuBusyTableRead).zipWithIndex.foreach { case ((busyTableWrite: Option[FuBusyTableWrite], busyTableRead: Option[FuBusyTableRead]), i) =>
403    if(busyTableWrite.nonEmpty) {
404      val btwr = busyTableWrite.get
405      val btrd = busyTableRead.get
406      btwr.io.in.deqResp := toBusyTableDeqResp(i)
407      btwr.io.in.og0Resp := io.og0Resp(i)
408      btwr.io.in.og1Resp := io.og1Resp(i)
409      btrd.io.in.fuBusyTable := btwr.io.out.fuBusyTable
410      btrd.io.in.fuTypeRegVec := fuTypeVec
411      fuBusyTableMask(i) := btrd.io.out.fuBusyTableMask
412    }
413    else {
414      fuBusyTableMask(i) := 0.U(params.numEntries.W)
415    }
416  }
417
418  //wbfuBusyTable write
419  intWbBusyTableWrite.zip(intWbBusyTableOut).zip(intDeqRespSetOut).zipWithIndex.foreach { case (((busyTableWrite: Option[FuBusyTableWrite], busyTable: Option[UInt]), deqResp), i) =>
420    if(busyTableWrite.nonEmpty) {
421      val btwr = busyTableWrite.get
422      val bt = busyTable.get
423      val dq = deqResp.get
424      btwr.io.in.deqResp := toBusyTableDeqResp(i)
425      btwr.io.in.og0Resp := io.og0Resp(i)
426      btwr.io.in.og1Resp := io.og1Resp(i)
427      bt := btwr.io.out.fuBusyTable
428      dq := btwr.io.out.deqRespSet
429    }
430  }
431
432  vfWbBusyTableWrite.zip(vfWbBusyTableOut).zip(vfDeqRespSetOut).zipWithIndex.foreach { case (((busyTableWrite: Option[FuBusyTableWrite], busyTable: Option[UInt]), deqResp), i) =>
433    if (busyTableWrite.nonEmpty) {
434      val btwr = busyTableWrite.get
435      val bt = busyTable.get
436      val dq = deqResp.get
437      btwr.io.in.deqResp := toBusyTableDeqResp(i)
438      btwr.io.in.og0Resp := io.og0Resp(i)
439      btwr.io.in.og1Resp := io.og1Resp(i)
440      bt := btwr.io.out.fuBusyTable
441      dq := btwr.io.out.deqRespSet
442    }
443  }
444
445  //wbfuBusyTable read
446  intWbBusyTableRead.zip(intWbBusyTableIn).zipWithIndex.foreach { case ((busyTableRead: Option[FuBusyTableRead], busyTable: Option[UInt]), i) =>
447    if(busyTableRead.nonEmpty) {
448      val btrd = busyTableRead.get
449      val bt = busyTable.get
450      btrd.io.in.fuBusyTable := bt
451      btrd.io.in.fuTypeRegVec := fuTypeVec
452      intWbBusyTableMask(i) := btrd.io.out.fuBusyTableMask
453    }
454    else {
455      intWbBusyTableMask(i) := 0.U(params.numEntries.W)
456    }
457  }
458  vfWbBusyTableRead.zip(vfWbBusyTableIn).zipWithIndex.foreach { case ((busyTableRead: Option[FuBusyTableRead], busyTable: Option[UInt]), i) =>
459    if (busyTableRead.nonEmpty) {
460      val btrd = busyTableRead.get
461      val bt = busyTable.get
462      btrd.io.in.fuBusyTable := bt
463      btrd.io.in.fuTypeRegVec := fuTypeVec
464      vfWbBusyTableMask(i) := btrd.io.out.fuBusyTableMask
465    }
466    else {
467      vfWbBusyTableMask(i) := 0.U(params.numEntries.W)
468    }
469  }
470
471  wakeUpQueues.zipWithIndex.foreach { case (wakeUpQueueOption, i) =>
472    wakeUpQueueOption.foreach {
473      wakeUpQueue =>
474        val flush = Wire(new WakeupQueueFlush)
475        flush.redirect := io.flush
476        flush.ldCancel := io.ldCancel
477        flush.og0Fail := io.og0Resp(i).valid && RSFeedbackType.isBlocked(io.og0Resp(i).bits.respType)
478        flush.og1Fail := io.og1Resp(i).valid && RSFeedbackType.isBlocked(io.og1Resp(i).bits.respType)
479        flush.finalFail := io.finalBlock(i)
480        wakeUpQueue.io.flush := flush
481        wakeUpQueue.io.enq.valid := deqBeforeDly(i).fire
482        wakeUpQueue.io.enq.bits.uop :<= deqBeforeDly(i).bits.common
483        wakeUpQueue.io.enq.bits.uop.pdestCopy.foreach(_ := 0.U)
484        wakeUpQueue.io.enq.bits.lat := getDeqLat(i, deqBeforeDly(i).bits.common.fuType)
485    }
486  }
487
488  deqBeforeDly.zipWithIndex.foreach { case (deq, i) =>
489    deq.valid                := finalDeqSelValidVec(i) && !cancelDeqVec(i)
490    deq.bits.addrOH          := finalDeqSelOHVec(i)
491    deq.bits.common.isFirstIssue := deqFirstIssueVec(i)
492    deq.bits.common.iqIdx    := OHToUInt(finalDeqSelOHVec(i))
493    deq.bits.common.fuType   := IQFuType.readFuType(deqEntryVec(i).bits.status.fuType, params.getFuCfgs.map(_.fuType)).asUInt
494    deq.bits.common.fuOpType := deqEntryVec(i).bits.payload.fuOpType
495    deq.bits.common.rfWen.foreach(_ := deqEntryVec(i).bits.payload.rfWen)
496    deq.bits.common.fpWen.foreach(_ := deqEntryVec(i).bits.payload.fpWen)
497    deq.bits.common.vecWen.foreach(_ := deqEntryVec(i).bits.payload.vecWen)
498    deq.bits.common.flushPipe.foreach(_ := deqEntryVec(i).bits.payload.flushPipe)
499    deq.bits.common.pdest := deqEntryVec(i).bits.payload.pdest
500    deq.bits.common.robIdx := deqEntryVec(i).bits.status.robIdx
501
502    require(deq.bits.common.dataSources.size <= finalDataSources(i).size)
503    deq.bits.common.dataSources.zip(finalDataSources(i)).foreach { case (sink, source) => sink := source}
504    deq.bits.common.l1ExuOH.foreach(_ := finalWakeUpL1ExuOH.get(i))
505    deq.bits.common.srcTimer.foreach(_ := finalSrcTimer.get(i))
506    deq.bits.common.loadDependency.foreach(_ := deqEntryVec(i).bits.status.mergedLoadDependency.get)
507    deq.bits.common.deqLdExuIdx.foreach(_ := params.backendParam.getLdExuIdx(deq.bits.exuParams).U)
508    deq.bits.common.src := DontCare
509    deq.bits.common.preDecode.foreach(_ := deqEntryVec(i).bits.payload.preDecodeInfo)
510
511    deq.bits.rf.zip(deqEntryVec(i).bits.status.psrc).zip(deqEntryVec(i).bits.status.srcType).foreach { case ((rf, psrc), srcType) =>
512      // psrc in status array can be pregIdx of IntRegFile or VfRegFile
513      rf.foreach(_.addr := psrc)
514      rf.foreach(_.srcType := srcType)
515    }
516    deq.bits.srcType.zip(deqEntryVec(i).bits.status.srcType).foreach { case (sink, source) =>
517      sink := source
518    }
519    deq.bits.immType := deqEntryVec(i).bits.payload.selImm
520    deq.bits.common.imm := deqEntryVec(i).bits.imm.getOrElse(0.U)
521
522    deq.bits.common.perfDebugInfo := deqEntryVec(i).bits.payload.debugInfo
523    deq.bits.common.perfDebugInfo.selectTime := GTimer()
524    deq.bits.common.perfDebugInfo.issueTime := GTimer() + 1.U
525  }
526
527  private val deqShift = WireDefault(deqBeforeDly)
528  deqShift.zip(deqBeforeDly).foreach {
529    case (shifted, original) =>
530      original.ready := shifted.ready // this will not cause combinational loop
531      shifted.bits.common.loadDependency.foreach(
532        _ := original.bits.common.loadDependency.get.map(_ << 1)
533      )
534  }
535  io.deqDelay.zip(deqShift).foreach { case (deqDly, deq) =>
536    NewPipelineConnect(
537      deq, deqDly, deqDly.valid,
538      false.B,
539      Option("Scheduler2DataPathPipe")
540    )
541  }
542  if(backendParams.debugEn) {
543    dontTouch(io.deqDelay)
544  }
545  io.wakeupToIQ.zipWithIndex.foreach { case (wakeup, i) =>
546    if (wakeUpQueues(i).nonEmpty && finalWakeUpL1ExuOH.nonEmpty) {
547      wakeup.valid := wakeUpQueues(i).get.io.deq.valid
548      wakeup.bits.fromExuInput(wakeUpQueues(i).get.io.deq.bits, finalWakeUpL1ExuOH.get(i))
549      wakeup.bits.loadDependency := wakeUpQueues(i).get.io.deq.bits.loadDependency.getOrElse(0.U.asTypeOf(wakeup.bits.loadDependency))
550      wakeup.bits.is0Lat := getDeqLat(i, wakeUpQueues(i).get.io.deq.bits.fuType) === 0.U
551    } else if (wakeUpQueues(i).nonEmpty) {
552      wakeup.valid := wakeUpQueues(i).get.io.deq.valid
553      wakeup.bits.fromExuInput(wakeUpQueues(i).get.io.deq.bits)
554      wakeup.bits.loadDependency := wakeUpQueues(i).get.io.deq.bits.loadDependency.getOrElse(0.U.asTypeOf(wakeup.bits.loadDependency))
555      wakeup.bits.is0Lat := getDeqLat(i, wakeUpQueues(i).get.io.deq.bits.fuType) === 0.U
556    } else {
557      wakeup.valid := false.B
558      wakeup.bits := 0.U.asTypeOf(wakeup.bits)
559      wakeup.bits.is0Lat :=  0.U
560    }
561    if(wakeup.bits.pdestCopy.nonEmpty){
562      wakeup.bits.pdestCopy.get := wakeUpQueues(i).get.io.deq.bits.pdestCopy.get
563    }
564  }
565
566  // Todo: better counter implementation
567  private val enqHasValid = validVec.take(params.numEnq).reduce(_ | _)
568  private val enqEntryValidCnt = PopCount(validVec.take(params.numEnq))
569  private val othersValidCnt = PopCount(validVec.drop(params.numEnq))
570  io.status.leftVec(0) := validVec.drop(params.numEnq).reduce(_ & _)
571  for (i <- 0 until params.numEnq) {
572    io.status.leftVec(i + 1) := othersValidCnt === (params.numEntries - params.numEnq - (i + 1)).U
573  }
574  private val othersLeftOneCaseVec = Wire(Vec(params.numEntries - params.numEnq, UInt((params.numEntries - params.numEnq).W)))
575  othersLeftOneCaseVec.zipWithIndex.foreach { case (leftone, i) =>
576    leftone := ~(1.U((params.numEntries - params.numEnq).W) << i)
577  }
578  private val othersLeftOne = othersLeftOneCaseVec.map(_ === VecInit(validVec.drop(params.numEnq)).asUInt).reduce(_ | _)
579  private val othersCanotIn = othersLeftOne || validVec.drop(params.numEnq).reduce(_ & _)
580
581  io.enq.foreach(_.ready := !othersCanotIn || !enqHasValid)
582  io.status.empty := !Cat(validVec).orR
583  io.status.full := othersCanotIn
584  io.status.validCnt := PopCount(validVec)
585
586  protected def getDeqLat(deqPortIdx: Int, fuType: UInt) : UInt = {
587    Mux1H(fuLatencyMaps(deqPortIdx) map { case (k, v) => (fuType(k.id), v.U) })
588  }
589
590  // issue perf counter
591  // enq count
592  XSPerfAccumulate("enq_valid_cnt", PopCount(io.enq.map(_.fire)))
593  XSPerfAccumulate("enq_fire_cnt", PopCount(io.enq.map(_.fire)))
594  // valid count
595  XSPerfHistogram("enq_entry_valid_cnt", enqEntryValidCnt, true.B, 0, params.numEnq + 1)
596  XSPerfHistogram("other_entry_valid_cnt", othersValidCnt, true.B, 0, params.numEntries - params.numEnq + 1)
597  XSPerfHistogram("valid_cnt", PopCount(validVec), true.B, 0, params.numEntries + 1)
598  // only split when more than 1 func type
599  if (params.getFuCfgs.size > 0) {
600    for (t <- FuType.functionNameMap.keys) {
601      val fuName = FuType.functionNameMap(t)
602      if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _)) {
603        XSPerfHistogram(s"valid_cnt_hist_futype_${fuName}", PopCount(validVec.zip(fuTypeVec).map { case (v, fu) => v && fu === t.U }), true.B, 0, params.numEntries, 1)
604      }
605    }
606  }
607  // ready instr count
608  private val readyEntriesCnt = PopCount(validVec.zip(canIssueVec).map(x => x._1 && x._2))
609  XSPerfHistogram("ready_cnt", readyEntriesCnt, true.B, 0, params.numEntries + 1)
610  // only split when more than 1 func type
611  if (params.getFuCfgs.size > 0) {
612    for (t <- FuType.functionNameMap.keys) {
613      val fuName = FuType.functionNameMap(t)
614      if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _)) {
615        XSPerfHistogram(s"ready_cnt_hist_futype_${fuName}", PopCount(validVec.zip(canIssueVec).zip(fuTypeVec).map { case ((v, c), fu) => v && c && fu === t.U }), true.B, 0, params.numEntries, 1)
616      }
617    }
618  }
619
620  // deq instr count
621  XSPerfAccumulate("issue_instr_pre_count", PopCount(deqBeforeDly.map(_.valid)))
622  XSPerfHistogram("issue_instr_pre_count_hist", PopCount(deqBeforeDly.map(_.valid)), true.B, 0, params.numDeq + 1, 1)
623  XSPerfAccumulate("issue_instr_count", PopCount(io.deqDelay.map(_.valid)))
624  XSPerfHistogram("issue_instr_count_hist", PopCount(io.deqDelay.map(_.valid)), true.B, 0, params.numDeq + 1, 1)
625
626  // deq instr data source count
627  XSPerfAccumulate("issue_datasource_reg", deqBeforeDly.map{ deq =>
628    PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) })
629  }.reduce(_ +& _))
630  XSPerfAccumulate("issue_datasource_bypass", deqBeforeDly.map{ deq =>
631    PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) })
632  }.reduce(_ +& _))
633  XSPerfAccumulate("issue_datasource_forward", deqBeforeDly.map{ deq =>
634    PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) })
635  }.reduce(_ +& _))
636  XSPerfAccumulate("issue_datasource_noreg", deqBeforeDly.map{ deq =>
637    PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) })
638  }.reduce(_ +& _))
639
640  XSPerfHistogram("issue_datasource_reg_hist", deqBeforeDly.map{ deq =>
641    PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) })
642  }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1)
643  XSPerfHistogram("issue_datasource_bypass_hist", deqBeforeDly.map{ deq =>
644    PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) })
645  }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1)
646  XSPerfHistogram("issue_datasource_forward_hist", deqBeforeDly.map{ deq =>
647    PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) })
648  }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1)
649  XSPerfHistogram("issue_datasource_noreg_hist", deqBeforeDly.map{ deq =>
650    PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) })
651  }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1)
652
653  // deq instr data source count for each futype
654  for (t <- FuType.functionNameMap.keys) {
655    val fuName = FuType.functionNameMap(t)
656    if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _)) {
657      XSPerfAccumulate(s"issue_datasource_reg_futype_${fuName}", deqBeforeDly.map{ deq =>
658        PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U })
659      }.reduce(_ +& _))
660      XSPerfAccumulate(s"issue_datasource_bypass_futype_${fuName}", deqBeforeDly.map{ deq =>
661        PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U })
662      }.reduce(_ +& _))
663      XSPerfAccumulate(s"issue_datasource_forward_futype_${fuName}", deqBeforeDly.map{ deq =>
664        PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U })
665      }.reduce(_ +& _))
666      XSPerfAccumulate(s"issue_datasource_noreg_futype_${fuName}", deqBeforeDly.map{ deq =>
667        PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U })
668      }.reduce(_ +& _))
669
670      XSPerfHistogram(s"issue_datasource_reg_hist_futype_${fuName}", deqBeforeDly.map{ deq =>
671        PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U })
672      }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1)
673      XSPerfHistogram(s"issue_datasource_bypass_hist_futype_${fuName}", deqBeforeDly.map{ deq =>
674        PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U })
675      }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1)
676      XSPerfHistogram(s"issue_datasource_forward_hist_futype_${fuName}", deqBeforeDly.map{ deq =>
677        PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U })
678      }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1)
679      XSPerfHistogram(s"issue_datasource_noreg_hist_futype_${fuName}", deqBeforeDly.map{ deq =>
680        PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U })
681      }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1)
682    }
683  }
684
685  // cancel instr count
686  if (params.hasIQWakeUp) {
687    val cancelVec: Vec[Bool] = entries.io.cancel.get
688    XSPerfAccumulate("cancel_instr_count", PopCount(validVec.zip(cancelVec).map(x => x._1 & x._2)))
689    XSPerfHistogram("cancel_instr_hist", PopCount(validVec.zip(cancelVec).map(x => x._1 & x._2)), true.B, 0, params.numEntries, 1)
690    for (t <- FuType.functionNameMap.keys) {
691      val fuName = FuType.functionNameMap(t)
692      if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _)) {
693        XSPerfAccumulate(s"cancel_instr_count_futype_${fuName}", PopCount(validVec.zip(cancelVec).zip(fuTypeVec).map{ case ((x, y), fu) => x & y & fu === t.U }))
694        XSPerfHistogram(s"cancel_instr_hist_futype_${fuName}", PopCount(validVec.zip(cancelVec).zip(fuTypeVec).map{ case ((x, y), fu) => x & y & fu === t.U }), true.B, 0, params.numEntries, 1)
695      }
696    }
697  }
698}
699
700class IssueQueueJumpBundle extends Bundle {
701  val pc = UInt(VAddrData().dataWidth.W)
702}
703
704class IssueQueueLoadBundle(implicit p: Parameters) extends XSBundle {
705  val fastMatch = UInt(backendParams.LduCnt.W)
706  val fastImm = UInt(12.W)
707}
708
709class IssueQueueIntIO()(implicit p: Parameters, params: IssueBlockParams) extends IssueQueueIO
710
711class IssueQueueIntImp(override val wrapper: IssueQueue)(implicit p: Parameters, iqParams: IssueBlockParams)
712  extends IssueQueueImp(wrapper)
713{
714  io.suggestName("none")
715  override lazy val io = IO(new IssueQueueIntIO).suggestName("io")
716
717  deqBeforeDly.zipWithIndex.foreach{ case (deq, i) => {
718    deq.bits.common.pc.foreach(_ := deqEntryVec(i).bits.payload.pc)
719    deq.bits.common.preDecode.foreach(_ := deqEntryVec(i).bits.payload.preDecodeInfo)
720    deq.bits.common.ftqIdx.foreach(_ := deqEntryVec(i).bits.payload.ftqPtr)
721    deq.bits.common.ftqOffset.foreach(_ := deqEntryVec(i).bits.payload.ftqOffset)
722    deq.bits.common.predictInfo.foreach(x => {
723      x.target := DontCare
724      x.taken := deqEntryVec(i).bits.payload.pred_taken
725    })
726    // for std
727    deq.bits.common.sqIdx.foreach(_ := deqEntryVec(i).bits.payload.sqIdx)
728    // for i2f
729    deq.bits.common.fpu.foreach(_ := deqEntryVec(i).bits.payload.fpu)
730  }}
731}
732
733class IssueQueueVfImp(override val wrapper: IssueQueue)(implicit p: Parameters, iqParams: IssueBlockParams)
734  extends IssueQueueImp(wrapper)
735{
736  s0_enqBits.foreach{ x =>
737    x.srcType(3) := SrcType.vp // v0: mask src
738    x.srcType(4) := SrcType.vp // vl&vtype
739  }
740  deqBeforeDly.zipWithIndex.foreach{ case (deq, i) => {
741    deq.bits.common.fpu.foreach(_ := deqEntryVec(i).bits.payload.fpu)
742    deq.bits.common.vpu.foreach(_ := deqEntryVec(i).bits.payload.vpu)
743    deq.bits.common.vpu.foreach(_.vuopIdx := deqEntryVec(i).bits.payload.uopIdx)
744    deq.bits.common.vpu.foreach(_.lastUop := deqEntryVec(i).bits.payload.lastUop)
745  }}
746}
747
748class IssueQueueMemBundle(implicit p: Parameters, params: IssueBlockParams) extends Bundle {
749  val feedbackIO = Flipped(Vec(params.numDeq, new MemRSFeedbackIO))
750  val checkWait = new Bundle {
751    val stIssuePtr = Input(new SqPtr)
752    val memWaitUpdateReq = Flipped(new MemWaitUpdateReq)
753  }
754  val loadFastMatch = Output(Vec(params.LduCnt, new IssueQueueLoadBundle))
755
756  // vector
757  val sqDeqPtr = OptionWrapper(params.isVecMemIQ, Input(new SqPtr))
758  val lqDeqPtr = OptionWrapper(params.isVecMemIQ, Input(new LqPtr))
759}
760
761class IssueQueueMemIO(implicit p: Parameters, params: IssueBlockParams) extends IssueQueueIO {
762  val memIO = Some(new IssueQueueMemBundle)
763}
764
765class IssueQueueMemAddrImp(override val wrapper: IssueQueue)(implicit p: Parameters, params: IssueBlockParams)
766  extends IssueQueueImp(wrapper) with HasCircularQueuePtrHelper {
767
768  require(params.StdCnt == 0 && (params.LduCnt + params.StaCnt + params.HyuCnt + params.VlduCnt) > 0, "IssueQueueMemAddrImp can only be instance of MemAddr IQ, " +
769    s"StdCnt: ${params.StdCnt}, LduCnt: ${params.LduCnt}, StaCnt: ${params.StaCnt}, HyuCnt: ${params.HyuCnt}")
770  println(s"[IssueQueueMemAddrImp] StdCnt: ${params.StdCnt}, LduCnt: ${params.LduCnt}, StaCnt: ${params.StaCnt}, HyuCnt: ${params.HyuCnt}")
771
772  io.suggestName("none")
773  override lazy val io = IO(new IssueQueueMemIO).suggestName("io")
774  private val memIO = io.memIO.get
775
776  memIO.loadFastMatch := 0.U.asTypeOf(memIO.loadFastMatch) // TODO: is still needed?
777
778  for (i <- io.enq.indices) {
779    val blockNotReleased = isAfter(io.enq(i).bits.sqIdx, memIO.checkWait.stIssuePtr)
780    val storeAddrWaitForIsIssuing = VecInit((0 until StorePipelineWidth).map(i => {
781      memIO.checkWait.memWaitUpdateReq.robIdx(i).valid &&
782        memIO.checkWait.memWaitUpdateReq.robIdx(i).bits.value === io.enq(i).bits.waitForRobIdx.value
783    })).asUInt.orR && !io.enq(i).bits.loadWaitStrict // is waiting for store addr ready
784    s0_enqBits(i).loadWaitBit := io.enq(i).bits.loadWaitBit && !storeAddrWaitForIsIssuing && blockNotReleased
785    // when have vpu
786    if (params.VlduCnt > 0 || params.VstuCnt > 0) {
787      s0_enqBits(i).srcType(3) := SrcType.vp // v0: mask src
788      s0_enqBits(i).srcType(4) := SrcType.vp // vl&vtype
789    }
790  }
791
792  for (i <- entries.io.enq.indices) {
793    entries.io.enq(i).bits.status match { case enqData =>
794      enqData.blocked := false.B // s0_enqBits(i).loadWaitBit
795      enqData.mem.get.strictWait := s0_enqBits(i).loadWaitStrict
796      enqData.mem.get.waitForStd := false.B
797      enqData.mem.get.waitForRobIdx := s0_enqBits(i).waitForRobIdx
798      enqData.mem.get.waitForSqIdx := 0.U.asTypeOf(enqData.mem.get.waitForSqIdx) // generated by sq, will be updated later
799      enqData.mem.get.sqIdx := s0_enqBits(i).sqIdx
800    }
801
802    entries.io.fromMem.get.slowResp.zipWithIndex.foreach { case (slowResp, i) =>
803      slowResp.valid                 := memIO.feedbackIO(i).feedbackSlow.valid
804      slowResp.bits.robIdx           := memIO.feedbackIO(i).feedbackSlow.bits.robIdx
805      slowResp.bits.uopIdx           := DontCare
806      slowResp.bits.respType         := Mux(memIO.feedbackIO(i).feedbackSlow.bits.hit, RSFeedbackType.fuIdle, RSFeedbackType.feedbackInvalid)
807      slowResp.bits.dataInvalidSqIdx := memIO.feedbackIO(i).feedbackSlow.bits.dataInvalidSqIdx
808      slowResp.bits.rfWen := DontCare
809      slowResp.bits.fuType := DontCare
810    }
811
812    entries.io.fromMem.get.fastResp.zipWithIndex.foreach { case (fastResp, i) =>
813      fastResp.valid                 := memIO.feedbackIO(i).feedbackFast.valid
814      fastResp.bits.robIdx           := memIO.feedbackIO(i).feedbackFast.bits.robIdx
815      fastResp.bits.uopIdx           := DontCare
816      fastResp.bits.respType         := Mux(memIO.feedbackIO(i).feedbackFast.bits.hit, RSFeedbackType.fuIdle, memIO.feedbackIO(i).feedbackFast.bits.sourceType)
817      fastResp.bits.dataInvalidSqIdx := 0.U.asTypeOf(fastResp.bits.dataInvalidSqIdx)
818      fastResp.bits.rfWen := DontCare
819      fastResp.bits.fuType := DontCare
820    }
821
822    entries.io.fromMem.get.memWaitUpdateReq := memIO.checkWait.memWaitUpdateReq
823    entries.io.fromMem.get.stIssuePtr := memIO.checkWait.stIssuePtr
824  }
825
826  deqBeforeDly.zipWithIndex.foreach { case (deq, i) =>
827    deq.bits.common.loadWaitBit.foreach(_ := deqEntryVec(i).bits.payload.loadWaitBit)
828    deq.bits.common.waitForRobIdx.foreach(_ := deqEntryVec(i).bits.payload.waitForRobIdx)
829    deq.bits.common.storeSetHit.foreach(_ := deqEntryVec(i).bits.payload.storeSetHit)
830    deq.bits.common.loadWaitStrict.foreach(_ := deqEntryVec(i).bits.payload.loadWaitStrict)
831    deq.bits.common.ssid.foreach(_ := deqEntryVec(i).bits.payload.ssid)
832    deq.bits.common.sqIdx.get := deqEntryVec(i).bits.payload.sqIdx
833    deq.bits.common.lqIdx.get := deqEntryVec(i).bits.payload.lqIdx
834    deq.bits.common.ftqIdx.foreach(_ := deqEntryVec(i).bits.payload.ftqPtr)
835    deq.bits.common.ftqOffset.foreach(_ := deqEntryVec(i).bits.payload.ftqOffset)
836    // when have vpu
837    if (params.VlduCnt > 0 || params.VstuCnt > 0) {
838      deq.bits.common.vpu.foreach(_ := deqEntryVec(i).bits.payload.vpu)
839      deq.bits.common.vpu.foreach(_.vuopIdx := deqEntryVec(i).bits.payload.uopIdx)
840    }
841  }
842}
843
844class IssueQueueVecMemImp(override val wrapper: IssueQueue)(implicit p: Parameters, params: IssueBlockParams)
845  extends IssueQueueImp(wrapper) with HasCircularQueuePtrHelper {
846
847  require((params.VstdCnt + params.VlduCnt + params.VstaCnt) > 0, "IssueQueueVecMemImp can only be instance of VecMem IQ")
848
849  io.suggestName("none")
850  override lazy val io = IO(new IssueQueueMemIO).suggestName("io")
851  private val memIO = io.memIO.get
852
853  def selectOldUop(robIdx: Seq[RobPtr], uopIdx: Seq[UInt], valid: Seq[Bool]): Vec[Bool] = {
854    val compareVec = (0 until robIdx.length).map(i => (0 until i).map(j => isAfter(robIdx(j), robIdx(i)) || (robIdx(j).value === robIdx(i).value && uopIdx(i) < uopIdx(j))))
855    val resultOnehot = VecInit((0 until robIdx.length).map(i => Cat((0 until robIdx.length).map(j =>
856      (if (j < i) !valid(j) || compareVec(i)(j)
857      else if (j == i) valid(i)
858      else !valid(j) || !compareVec(j)(i))
859    )).andR))
860    resultOnehot
861  }
862
863  val robIdxVec = entries.io.robIdx.get
864  val uopIdxVec = entries.io.uopIdx.get
865  val allEntryOldestOH = selectOldUop(robIdxVec, uopIdxVec, validVec)
866
867  finalDeqSelValidVec.head := (allEntryOldestOH.asUInt & canIssueVec.asUInt).orR
868  finalDeqSelOHVec.head := allEntryOldestOH.asUInt & canIssueVec.asUInt
869
870  if (params.isVecMemAddrIQ) {
871    s0_enqBits.foreach{ x =>
872      x.srcType(3) := SrcType.vp // v0: mask src
873      x.srcType(4) := SrcType.vp // vl&vtype
874    }
875
876    for (i <- io.enq.indices) {
877      s0_enqBits(i).loadWaitBit := false.B
878    }
879
880    for (i <- entries.io.enq.indices) {
881      entries.io.enq(i).bits.status match { case enqData =>
882        enqData.blocked := false.B // s0_enqBits(i).loadWaitBit
883        enqData.mem.get.strictWait := s0_enqBits(i).loadWaitStrict
884        enqData.mem.get.waitForStd := false.B
885        enqData.mem.get.waitForRobIdx := s0_enqBits(i).waitForRobIdx
886        enqData.mem.get.waitForSqIdx := 0.U.asTypeOf(enqData.mem.get.waitForSqIdx) // generated by sq, will be updated later
887        enqData.mem.get.sqIdx := s0_enqBits(i).sqIdx
888      }
889
890      entries.io.fromMem.get.slowResp.zipWithIndex.foreach { case (slowResp, i) =>
891        slowResp.valid                 := memIO.feedbackIO(i).feedbackSlow.valid
892        slowResp.bits.robIdx           := memIO.feedbackIO(i).feedbackSlow.bits.robIdx
893        slowResp.bits.uopIdx           := DontCare
894        slowResp.bits.respType         := Mux(memIO.feedbackIO(i).feedbackSlow.bits.hit, RSFeedbackType.fuIdle, RSFeedbackType.feedbackInvalid)
895        slowResp.bits.dataInvalidSqIdx := memIO.feedbackIO(i).feedbackSlow.bits.dataInvalidSqIdx
896        slowResp.bits.rfWen := DontCare
897        slowResp.bits.fuType := DontCare
898      }
899
900      entries.io.fromMem.get.fastResp.zipWithIndex.foreach { case (fastResp, i) =>
901        fastResp.valid                 := memIO.feedbackIO(i).feedbackFast.valid
902        fastResp.bits.robIdx           := memIO.feedbackIO(i).feedbackFast.bits.robIdx
903        fastResp.bits.uopIdx           := DontCare
904        fastResp.bits.respType         := memIO.feedbackIO(i).feedbackFast.bits.sourceType
905        fastResp.bits.dataInvalidSqIdx := 0.U.asTypeOf(fastResp.bits.dataInvalidSqIdx)
906        fastResp.bits.rfWen := DontCare
907        fastResp.bits.fuType := DontCare
908      }
909
910      entries.io.fromMem.get.memWaitUpdateReq := memIO.checkWait.memWaitUpdateReq
911      entries.io.fromMem.get.stIssuePtr := memIO.checkWait.stIssuePtr
912    }
913  }
914
915  for (i <- entries.io.enq.indices) {
916    entries.io.enq(i).bits.status match { case enqData =>
917      enqData.vecMem.get.sqIdx := s0_enqBits(i).sqIdx
918      enqData.vecMem.get.lqIdx := s0_enqBits(i).lqIdx
919    }
920  }
921
922  entries.io.fromLsq.get.sqDeqPtr := memIO.sqDeqPtr.get
923  entries.io.fromLsq.get.lqDeqPtr := memIO.lqDeqPtr.get
924
925  deqBeforeDly.zipWithIndex.foreach { case (deq, i) =>
926    deq.bits.common.sqIdx.foreach(_ := deqEntryVec(i).bits.payload.sqIdx)
927    deq.bits.common.lqIdx.foreach(_ := deqEntryVec(i).bits.payload.lqIdx)
928    if (params.isVecLdAddrIQ) {
929      deq.bits.common.ftqIdx.get := deqEntryVec(i).bits.payload.ftqPtr
930      deq.bits.common.ftqOffset.get := deqEntryVec(i).bits.payload.ftqOffset
931    }
932    deq.bits.common.fpu.foreach(_ := deqEntryVec(i).bits.payload.fpu)
933    deq.bits.common.vpu.foreach(_ := deqEntryVec(i).bits.payload.vpu)
934    deq.bits.common.vpu.foreach(_.vuopIdx := deqEntryVec(i).bits.payload.uopIdx)
935    deq.bits.common.vpu.foreach(_.lastUop := deqEntryVec(i).bits.payload.lastUop)
936  }
937}
938