xref: /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala (revision 4daa5bf3c3f27e7fd090866d52405b21e107eb8d) 
1package xiangshan.backend.issue
2
3import org.chipsalliance.cde.config.Parameters
4import chisel3._
5import chisel3.util._
6import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
7import utility.{GTimer, HasCircularQueuePtrHelper, SelectOne, GatedValidRegNext}
8import utils._
9import xiangshan._
10import xiangshan.backend.Bundles._
11import xiangshan.backend.issue.EntryBundles._
12import xiangshan.backend.decode.{ImmUnion, Imm_LUI_LOAD}
13import xiangshan.backend.datapath.DataConfig._
14import xiangshan.backend.datapath.DataSource
15import xiangshan.backend.fu.{FuConfig, FuType}
16import xiangshan.mem.{MemWaitUpdateReq, SqPtr, LqPtr}
17import xiangshan.backend.rob.RobPtr
18import xiangshan.backend.datapath.NewPipelineConnect
19
20class IssueQueue(params: IssueBlockParams)(implicit p: Parameters) extends LazyModule with HasXSParameter {
21  override def shouldBeInlined: Boolean = false
22
23  implicit val iqParams = params
24  lazy val module: IssueQueueImp = iqParams.schdType match {
25    case IntScheduler() => new IssueQueueIntImp(this)
26    case FpScheduler() => new IssueQueueFpImp(this)
27    case VfScheduler() => new IssueQueueVfImp(this)
28    case MemScheduler() =>
29      if (iqParams.StdCnt == 0 && !iqParams.isVecMemIQ) new IssueQueueMemAddrImp(this)
30      else if (iqParams.isVecMemIQ) new IssueQueueVecMemImp(this)
31      else new IssueQueueIntImp(this)
32    case _ => null
33  }
34}
35
36class IssueQueueStatusBundle(numEnq: Int, numEntries: Int) extends Bundle {
37  val empty = Output(Bool())
38  val full = Output(Bool())
39  val validCnt = Output(UInt(log2Ceil(numEntries).W))
40  val leftVec = Output(Vec(numEnq + 1, Bool()))
41}
42
43class IssueQueueDeqRespBundle(implicit p:Parameters, params: IssueBlockParams) extends EntryDeqRespBundle
44
45class IssueQueueIO()(implicit p: Parameters, params: IssueBlockParams) extends XSBundle {
46  // Inputs
47  val flush = Flipped(ValidIO(new Redirect))
48  val enq = Vec(params.numEnq, Flipped(DecoupledIO(new DynInst)))
49
50  val og0Resp = Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle)))
51  val og1Resp = Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle)))
52  val og2Resp = OptionWrapper(params.inVfSchd, Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle))))
53  val finalIssueResp = OptionWrapper(params.LdExuCnt > 0, Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle))))
54  val memAddrIssueResp = OptionWrapper(params.LdExuCnt > 0, Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle))))
55  val wbBusyTableRead = Input(params.genWbFuBusyTableReadBundle())
56  val wbBusyTableWrite = Output(params.genWbFuBusyTableWriteBundle())
57  val wakeupFromWB: MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = Flipped(params.genWBWakeUpSinkValidBundle)
58  val wakeupFromIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(params.genIQWakeUpSinkValidBundle)
59  val og0Cancel = Input(ExuOH(backendParams.numExu))
60  val og1Cancel = Input(ExuOH(backendParams.numExu))
61  val ldCancel = Vec(backendParams.LduCnt + backendParams.HyuCnt, Flipped(new LoadCancelIO))
62
63  // Outputs
64  val wakeupToIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = params.genIQWakeUpSourceValidBundle
65  val status = Output(new IssueQueueStatusBundle(params.numEnq, params.numEntries))
66  val validCntDeqVec = Output(Vec(params.numDeq,UInt(params.numEntries.U.getWidth.W)))
67  // val statusNext = Output(new IssueQueueStatusBundle(params.numEnq))
68
69  val deqDelay: MixedVec[DecoupledIO[IssueQueueIssueBundle]] = params.genIssueDecoupledBundle// = deq.cloneType
70  def allWakeUp = wakeupFromWB ++ wakeupFromIQ
71}
72
73class IssueQueueImp(override val wrapper: IssueQueue)(implicit p: Parameters, val params: IssueBlockParams)
74  extends LazyModuleImp(wrapper)
75  with HasXSParameter {
76
77  override def desiredName: String = s"${params.getIQName}"
78
79  println(s"[IssueQueueImp] ${params.getIQName} wakeupFromWB(${io.wakeupFromWB.size}), " +
80    s"wakeup exu in(${params.wakeUpInExuSources.size}): ${params.wakeUpInExuSources.map(_.name).mkString("{",",","}")}, " +
81    s"wakeup exu out(${params.wakeUpOutExuSources.size}): ${params.wakeUpOutExuSources.map(_.name).mkString("{",",","}")}, " +
82    s"numEntries: ${params.numEntries}, numRegSrc: ${params.numRegSrc}, " +
83    s"numEnq: ${params.numEnq}, numSimp: ${params.numSimp}, numComp: ${params.numComp}, numDeq: ${params.numDeq}, " +
84    s"isAllSimp: ${params.isAllSimp}, isAllComp: ${params.isAllComp}")
85
86  require(params.numExu <= 2, "IssueQueue has not supported more than 2 deq ports")
87  require(params.numEnq <= 2, "IssueQueue has not supported more than 2 enq ports")
88  require(params.numSimp == 0 || params.numSimp >= params.numEnq, "numSimp should be 0 or at least not less than numEnq")
89  require(params.numComp == 0 || params.numComp >= params.numEnq, "numComp should be 0 or at least not less than numEnq")
90
91  val deqFuCfgs     : Seq[Seq[FuConfig]] = params.exuBlockParams.map(_.fuConfigs)
92  val allDeqFuCfgs  : Seq[FuConfig] = params.exuBlockParams.flatMap(_.fuConfigs)
93  val fuCfgsCnt     : Map[FuConfig, Int] = allDeqFuCfgs.groupBy(x => x).map { case (cfg, cfgSeq) => (cfg, cfgSeq.length) }
94  val commonFuCfgs  : Seq[FuConfig] = fuCfgsCnt.filter(_._2 > 1).keys.toSeq
95  val wakeupFuLatencyMaps : Seq[Map[FuType.OHType, Int]] = params.exuBlockParams.map(x => x.wakeUpFuLatencyMap)
96
97  println(s"[IssueQueueImp] ${params.getIQName} fuLatencyMaps: ${wakeupFuLatencyMaps}")
98  println(s"[IssueQueueImp] ${params.getIQName} commonFuCfgs: ${commonFuCfgs.map(_.name)}")
99  lazy val io = IO(new IssueQueueIO())
100
101  // Modules
102  val entries = Module(new Entries)
103  val fuBusyTableWrite = params.exuBlockParams.map { case x => OptionWrapper(x.latencyValMax > 0, Module(new FuBusyTableWrite(x.fuLatencyMap))) }
104  val fuBusyTableRead = params.exuBlockParams.map { case x => OptionWrapper(x.latencyValMax > 0, Module(new FuBusyTableRead(x.fuLatencyMap))) }
105  val intWbBusyTableWrite = params.exuBlockParams.map { case x => OptionWrapper(x.intLatencyCertain, Module(new FuBusyTableWrite(x.intFuLatencyMap))) }
106  val intWbBusyTableRead = params.exuBlockParams.map { case x => OptionWrapper(x.intLatencyCertain, Module(new FuBusyTableRead(x.intFuLatencyMap))) }
107  val fpWbBusyTableWrite = params.exuBlockParams.map { case x => OptionWrapper(x.fpLatencyCertain, Module(new FuBusyTableWrite(x.fpFuLatencyMap))) }
108  val fpWbBusyTableRead = params.exuBlockParams.map { case x => OptionWrapper(x.fpLatencyCertain, Module(new FuBusyTableRead(x.fpFuLatencyMap))) }
109  val vfWbBusyTableWrite = params.exuBlockParams.map { case x => OptionWrapper(x.vfLatencyCertain, Module(new FuBusyTableWrite(x.vfFuLatencyMap))) }
110  val vfWbBusyTableRead = params.exuBlockParams.map { case x => OptionWrapper(x.vfLatencyCertain, Module(new FuBusyTableRead(x.vfFuLatencyMap))) }
111
112  class WakeupQueueFlush extends Bundle {
113    val redirect = ValidIO(new Redirect)
114    val ldCancel = Vec(backendParams.LduCnt + backendParams.HyuCnt, new LoadCancelIO)
115    val og0Fail = Output(Bool())
116    val og1Fail = Output(Bool())
117  }
118
119  private def flushFunc(exuInput: ExuInput, flush: WakeupQueueFlush, stage: Int): Bool = {
120    val redirectFlush = exuInput.robIdx.needFlush(flush.redirect)
121    val loadDependencyFlush = LoadShouldCancel(exuInput.loadDependency, flush.ldCancel)
122    val ogFailFlush = stage match {
123      case 1 => flush.og0Fail
124      case 2 => flush.og1Fail
125      case _ => false.B
126    }
127    redirectFlush || loadDependencyFlush || ogFailFlush
128  }
129
130  private def modificationFunc(exuInput: ExuInput): ExuInput = {
131    val newExuInput = WireDefault(exuInput)
132    newExuInput.loadDependency match {
133      case Some(deps) => deps.zip(exuInput.loadDependency.get).foreach(x => x._1 := x._2 << 1)
134      case None =>
135    }
136    newExuInput
137  }
138
139  private def lastConnectFunc(exuInput: ExuInput, newInput: ExuInput): ExuInput = {
140    val lastExuInput = WireDefault(exuInput)
141    val newExuInput = WireDefault(newInput)
142    newExuInput.elements.foreach { case (name, data) =>
143      if (lastExuInput.elements.contains(name)) {
144        data := lastExuInput.elements(name)
145      }
146    }
147    if (newExuInput.pdestCopy.nonEmpty && !lastExuInput.pdestCopy.nonEmpty) {
148      newExuInput.pdestCopy.get.foreach(_ := lastExuInput.pdest)
149    }
150    if (newExuInput.rfWenCopy.nonEmpty && !lastExuInput.rfWenCopy.nonEmpty) {
151      newExuInput.rfWenCopy.get.foreach(_ := lastExuInput.rfWen.get)
152    }
153    if (newExuInput.fpWenCopy.nonEmpty && !lastExuInput.fpWenCopy.nonEmpty) {
154      newExuInput.fpWenCopy.get.foreach(_ := lastExuInput.fpWen.get)
155    }
156    if (newExuInput.vecWenCopy.nonEmpty && !lastExuInput.vecWenCopy.nonEmpty) {
157      newExuInput.vecWenCopy.get.foreach(_ := lastExuInput.rfWen.get)
158    }
159    if (newExuInput.loadDependencyCopy.nonEmpty && !lastExuInput.loadDependencyCopy.nonEmpty) {
160      newExuInput.loadDependencyCopy.get.foreach(_ := lastExuInput.loadDependency.get)
161    }
162    newExuInput
163  }
164
165  val wakeUpQueues: Seq[Option[MultiWakeupQueue[ExuInput, WakeupQueueFlush]]] = params.exuBlockParams.map { x => OptionWrapper(x.isIQWakeUpSource && !x.hasLoadExu, Module(
166    new MultiWakeupQueue(new ExuInput(x), new ExuInput(x, x.copyWakeupOut, x.copyNum), new WakeupQueueFlush, x.wakeUpFuLatancySet, flushFunc, modificationFunc, lastConnectFunc)
167  ))}
168  val deqBeforeDly = Wire(params.genIssueDecoupledBundle)
169
170  val intWbBusyTableIn = io.wbBusyTableRead.map(_.intWbBusyTable)
171  val fpWbBusyTableIn = io.wbBusyTableRead.map(_.fpWbBusyTable)
172  val vfWbBusyTableIn = io.wbBusyTableRead.map(_.vfWbBusyTable)
173  val intWbBusyTableOut = io.wbBusyTableWrite.map(_.intWbBusyTable)
174  val fpWbBusyTableOut = io.wbBusyTableWrite.map(_.fpWbBusyTable)
175  val vfWbBusyTableOut = io.wbBusyTableWrite.map(_.vfWbBusyTable)
176  val intDeqRespSetOut = io.wbBusyTableWrite.map(_.intDeqRespSet)
177  val fpDeqRespSetOut = io.wbBusyTableWrite.map(_.fpDeqRespSet)
178  val vfDeqRespSetOut = io.wbBusyTableWrite.map(_.vfDeqRespSet)
179  val fuBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W)))
180  val intWbBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W)))
181  val fpWbBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W)))
182  val vfWbBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W)))
183  val s0_enqValidVec = io.enq.map(_.valid)
184  val s0_enqSelValidVec = Wire(Vec(params.numEnq, Bool()))
185  val s0_enqNotFlush = !io.flush.valid
186  val s0_enqBits = WireInit(VecInit(io.enq.map(_.bits)))
187  val s0_doEnqSelValidVec = s0_enqSelValidVec.map(_ && s0_enqNotFlush) //enqValid && notFlush && enqReady
188
189
190  val finalDeqSelValidVec = Wire(Vec(params.numDeq, Bool()))
191  val finalDeqSelOHVec    = Wire(Vec(params.numDeq, UInt(params.numEntries.W)))
192
193  val validVec = VecInit(entries.io.valid.asBools)
194  val canIssueVec = VecInit(entries.io.canIssue.asBools)
195  dontTouch(canIssueVec)
196  val deqFirstIssueVec = entries.io.isFirstIssue
197
198  val dataSources: Vec[Vec[DataSource]] = entries.io.dataSources
199  val finalDataSources: Vec[Vec[DataSource]] = VecInit(finalDeqSelOHVec.map(oh => Mux1H(oh, dataSources)))
200  val loadDependency: Vec[Vec[UInt]] = entries.io.loadDependency
201  val finalLoadDependency: IndexedSeq[Vec[UInt]] = VecInit(finalDeqSelOHVec.map(oh => Mux1H(oh, loadDependency)))
202  // (entryIdx)(srcIdx)(exuIdx)
203  val wakeUpL1ExuOH: Option[Vec[Vec[UInt]]] = entries.io.srcWakeUpL1ExuOH
204  // (deqIdx)(srcIdx)(exuIdx)
205  val finalWakeUpL1ExuOH: Option[Vec[Vec[UInt]]] = wakeUpL1ExuOH.map(x => VecInit(finalDeqSelOHVec.map(oh => Mux1H(oh, x))))
206
207  val fuTypeVec = Wire(Vec(params.numEntries, FuType()))
208  val deqEntryVec = Wire(Vec(params.numDeq, ValidIO(new EntryBundle)))
209  val canIssueMergeAllBusy = Wire(Vec(params.numDeq, UInt(params.numEntries.W)))
210  val deqCanIssue = Wire(Vec(params.numDeq, UInt(params.numEntries.W)))
211
212  //deq
213  val enqEntryOldestSel = Wire(Vec(params.numDeq, ValidIO(UInt(params.numEnq.W))))
214  val simpEntryOldestSel = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numDeq + params.numEnq, ValidIO(UInt(params.numSimp.W)))))
215  val compEntryOldestSel = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numDeq, ValidIO(UInt(params.numComp.W)))))
216  val othersEntryOldestSel = Wire(Vec(params.numDeq, ValidIO(UInt((params.numEntries - params.numEnq).W))))
217  val deqSelValidVec = Wire(Vec(params.numDeq, Bool()))
218  val deqSelOHVec    = Wire(Vec(params.numDeq, UInt(params.numEntries.W)))
219  val cancelDeqVec = Wire(Vec(params.numDeq, Bool()))
220
221  val subDeqSelValidVec = OptionWrapper(params.deqFuSame, Wire(Vec(params.numDeq, Bool())))
222  val subDeqSelOHVec = OptionWrapper(params.deqFuSame, Wire(Vec(params.numDeq, UInt(params.numEntries.W))))
223  val subDeqRequest = OptionWrapper(params.deqFuSame, Wire(UInt(params.numEntries.W)))
224
225  //trans
226  val simpEntryEnqSelVec = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numEnq, UInt(params.numSimp.W))))
227  val compEntryEnqSelVec = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numEnq, UInt(params.numComp.W))))
228  val othersEntryEnqSelVec = OptionWrapper(params.isAllComp || params.isAllSimp, Wire(Vec(params.numEnq, UInt((params.numEntries - params.numEnq).W))))
229  val simpAgeDetectRequest = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numDeq + params.numEnq, UInt(params.numSimp.W))))
230  simpAgeDetectRequest.foreach(_ := 0.U.asTypeOf(simpAgeDetectRequest.get))
231
232  // when vf exu (with og2) wake up int/mem iq (without og2), the wakeup signals should delay 1 cycle
233  // as vf exu's min latency is 1, we do not need consider og0cancel
234  val wakeupFromIQ = Wire(chiselTypeOf(io.wakeupFromIQ))
235  wakeupFromIQ.zip(io.wakeupFromIQ).foreach { case (w, w_src) =>
236    if (!params.inVfSchd && params.readVfRf && params.hasWakeupFromVf && w_src.bits.params.isVfExeUnit) {
237      val noCancel = !LoadShouldCancel(Some(w_src.bits.loadDependency), io.ldCancel)
238      w := RegNext(Mux(noCancel, w_src, 0.U.asTypeOf(w)))
239      w.bits.loadDependency.zip(w_src.bits.loadDependency).foreach{ case (ld, ld_src) => ld := RegNext(Mux(noCancel, ld_src << 1, 0.U.asTypeOf(ld))) }
240    } else {
241      w := w_src
242    }
243  }
244
245  /**
246    * Connection of [[entries]]
247    */
248  entries.io match { case entriesIO: EntriesIO =>
249    entriesIO.flush                                             := io.flush
250    entriesIO.enq.zipWithIndex.foreach { case (enq, enqIdx) =>
251      enq.valid                                                 := s0_doEnqSelValidVec(enqIdx)
252      enq.bits.status.robIdx                                    := s0_enqBits(enqIdx).robIdx
253      enq.bits.status.fuType                                    := IQFuType.readFuType(VecInit(s0_enqBits(enqIdx).fuType.asBools), params.getFuCfgs.map(_.fuType))
254      val numLsrc = s0_enqBits(enqIdx).srcType.size.min(enq.bits.status.srcStatus.map(_.srcType).size)
255      for(j <- 0 until numLsrc) {
256        enq.bits.status.srcStatus(j).psrc                       := s0_enqBits(enqIdx).psrc(j)
257        enq.bits.status.srcStatus(j).srcType                    := s0_enqBits(enqIdx).srcType(j)
258        enq.bits.status.srcStatus(j).srcState                   := s0_enqBits(enqIdx).srcState(j) & !LoadShouldCancel(Some(s0_enqBits(enqIdx).srcLoadDependency(j)), io.ldCancel)
259        enq.bits.status.srcStatus(j).dataSources.value          := Mux(
260          SrcType.isXp(s0_enqBits(enqIdx).srcType(j)) && (s0_enqBits(enqIdx).psrc(j) === 0.U),
261          DataSource.zero,
262          Mux(SrcType.isNotReg(s0_enqBits(enqIdx).srcType(j)), DataSource.imm, DataSource.reg)
263        )
264        enq.bits.status.srcStatus(j).srcLoadDependency          := VecInit(s0_enqBits(enqIdx).srcLoadDependency(j).map(x => x << 1))
265        if(params.hasIQWakeUp) {
266          enq.bits.status.srcStatus(j).srcWakeUpL1ExuOH.get     := 0.U.asTypeOf(ExuVec())
267        }
268      }
269      enq.bits.status.blocked                                   := false.B
270      enq.bits.status.issued                                    := false.B
271      enq.bits.status.firstIssue                                := false.B
272      enq.bits.status.issueTimer                                := "b11".U
273      enq.bits.status.deqPortIdx                                := 0.U
274      enq.bits.imm.foreach(_                                    := s0_enqBits(enqIdx).imm)
275      enq.bits.payload                                          := s0_enqBits(enqIdx)
276    }
277    entriesIO.og0Resp.zipWithIndex.foreach { case (og0Resp, i) =>
278      og0Resp                                                   := io.og0Resp(i)
279    }
280    entriesIO.og1Resp.zipWithIndex.foreach { case (og1Resp, i) =>
281      og1Resp                                                   := io.og1Resp(i)
282    }
283    if (params.inVfSchd) {
284      entriesIO.og2Resp.get.zipWithIndex.foreach { case (og2Resp, i) =>
285        og2Resp                                                 := io.og2Resp.get(i)
286      }
287    }
288    if (params.isLdAddrIQ || params.isHyAddrIQ) {
289      entriesIO.fromLoad.get.finalIssueResp.zipWithIndex.foreach { case (finalIssueResp, i) =>
290        finalIssueResp                                          := io.finalIssueResp.get(i)
291      }
292      entriesIO.fromLoad.get.memAddrIssueResp.zipWithIndex.foreach { case (memAddrIssueResp, i) =>
293        memAddrIssueResp                                        := io.memAddrIssueResp.get(i)
294      }
295    }
296    for(deqIdx <- 0 until params.numDeq) {
297      entriesIO.deqReady(deqIdx)                                := deqBeforeDly(deqIdx).ready
298      entriesIO.deqSelOH(deqIdx).valid                          := deqSelValidVec(deqIdx)
299      entriesIO.deqSelOH(deqIdx).bits                           := deqSelOHVec(deqIdx)
300      entriesIO.enqEntryOldestSel(deqIdx)                       := enqEntryOldestSel(deqIdx)
301      entriesIO.simpEntryOldestSel.foreach(_(deqIdx)            := simpEntryOldestSel.get(deqIdx))
302      entriesIO.compEntryOldestSel.foreach(_(deqIdx)            := compEntryOldestSel.get(deqIdx))
303      entriesIO.othersEntryOldestSel.foreach(_(deqIdx)          := othersEntryOldestSel(deqIdx))
304      entriesIO.subDeqRequest.foreach(_(deqIdx)                 := subDeqRequest.get)
305      entriesIO.subDeqSelOH.foreach(_(deqIdx)                   := subDeqSelOHVec.get(deqIdx))
306    }
307    entriesIO.wakeUpFromWB                                      := io.wakeupFromWB
308    entriesIO.wakeUpFromIQ                                      := wakeupFromIQ
309    entriesIO.og0Cancel                                         := io.og0Cancel
310    entriesIO.og1Cancel                                         := io.og1Cancel
311    entriesIO.ldCancel                                          := io.ldCancel
312    entriesIO.simpEntryDeqSelVec.foreach(_                      := VecInit(simpEntryOldestSel.get.takeRight(params.numEnq).map(_.bits)))
313    //output
314    fuTypeVec                                                   := entriesIO.fuType
315    deqEntryVec                                                 := entriesIO.deqEntry
316    cancelDeqVec                                                := entriesIO.cancelDeqVec
317    simpEntryEnqSelVec.foreach(_                                := entriesIO.simpEntryEnqSelVec.get)
318    compEntryEnqSelVec.foreach(_                                := entriesIO.compEntryEnqSelVec.get)
319    othersEntryEnqSelVec.foreach(_                              := entriesIO.othersEntryEnqSelVec.get)
320  }
321
322
323  s0_enqSelValidVec := s0_enqValidVec.zip(io.enq).map{ case (enqValid, enq) => enqValid && enq.ready}
324
325  protected val commonAccept: UInt = Cat(fuTypeVec.map(fuType =>
326    FuType.FuTypeOrR(fuType, commonFuCfgs.map(_.fuType))
327  ).reverse)
328
329  // if deq port can accept the uop
330  protected val canAcceptVec: Seq[UInt] = deqFuCfgs.map { fuCfgs: Seq[FuConfig] =>
331    Cat(fuTypeVec.map(fuType =>
332      FuType.FuTypeOrR(fuType, fuCfgs.map(_.fuType))
333    ).reverse)
334  }
335
336  protected val deqCanAcceptVec: Seq[IndexedSeq[Bool]] = deqFuCfgs.map { fuCfgs: Seq[FuConfig] =>
337    fuTypeVec.map(fuType =>
338      FuType.FuTypeOrR(fuType, fuCfgs.map(_.fuType)))
339  }
340
341  canIssueMergeAllBusy.zipWithIndex.foreach { case (merge, i) =>
342    val mergeFuBusy = {
343      if (fuBusyTableWrite(i).nonEmpty) canIssueVec.asUInt & (~fuBusyTableMask(i))
344      else canIssueVec.asUInt
345    }
346    val mergeIntWbBusy = {
347      if (intWbBusyTableRead(i).nonEmpty) mergeFuBusy & (~intWbBusyTableMask(i))
348      else mergeFuBusy
349    }
350    val mergefpWbBusy = {
351      if (fpWbBusyTableRead(i).nonEmpty) mergeIntWbBusy & (~fpWbBusyTableMask(i))
352      else mergeIntWbBusy
353    }
354    val mergeVfWbBusy = {
355      if (vfWbBusyTableRead(i).nonEmpty) mergefpWbBusy & (~vfWbBusyTableMask(i))
356      else mergefpWbBusy
357    }
358    merge := mergeVfWbBusy
359  }
360
361  deqCanIssue.zipWithIndex.foreach { case (req, i) =>
362    req := canIssueMergeAllBusy(i) & VecInit(deqCanAcceptVec(i)).asUInt
363  }
364  dontTouch(fuTypeVec)
365  dontTouch(canIssueMergeAllBusy)
366  dontTouch(deqCanIssue)
367
368  if (params.numDeq == 2) {
369    require(params.deqFuSame || params.deqFuDiff, "The 2 deq ports need to be identical or completely different")
370  }
371
372  if (params.numDeq == 2 && params.deqFuSame) {
373    val subDeqPolicy = Module(new DeqPolicy())
374
375    enqEntryOldestSel := DontCare
376
377    if (params.isAllComp || params.isAllSimp) {
378      othersEntryOldestSel(0) := AgeDetector(numEntries = params.numEntries - params.numEnq,
379        enq = othersEntryEnqSelVec.get,
380        canIssue = canIssueVec.asUInt(params.numEntries-1, params.numEnq)
381      )
382      othersEntryOldestSel(1) := DontCare
383
384      subDeqPolicy.io.request := subDeqRequest.get
385      subDeqSelValidVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => oh.valid)
386      subDeqSelOHVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => oh.bits)
387    }
388    else {
389      simpAgeDetectRequest.get(0) := canIssueVec.asUInt(params.numEnq + params.numSimp - 1, params.numEnq)
390      simpAgeDetectRequest.get(1) := DontCare
391      simpAgeDetectRequest.get(params.numDeq) := VecInit(validVec.drop(params.numEnq).take(params.numSimp)).asUInt
392      if (params.numEnq == 2) {
393        simpAgeDetectRequest.get(params.numDeq + 1) := VecInit(validVec.drop(params.numEnq).take(params.numSimp)).asUInt & ~simpEntryOldestSel.get(params.numDeq).bits
394      }
395
396      simpEntryOldestSel.get := AgeDetector(numEntries = params.numSimp,
397        enq = simpEntryEnqSelVec.get,
398        canIssue = simpAgeDetectRequest.get
399      )
400
401      compEntryOldestSel.get(0) := AgeDetector(numEntries = params.numComp,
402        enq = compEntryEnqSelVec.get,
403        canIssue = canIssueVec.asUInt(params.numEntries - 1, params.numEnq + params.numSimp)
404      )
405      compEntryOldestSel.get(1) := DontCare
406
407      othersEntryOldestSel(0).valid := compEntryOldestSel.get(0).valid || simpEntryOldestSel.get(0).valid
408      othersEntryOldestSel(0).bits := Cat(
409        compEntryOldestSel.get(0).bits,
410        Fill(params.numSimp, !compEntryOldestSel.get(0).valid) & simpEntryOldestSel.get(0).bits,
411      )
412      othersEntryOldestSel(1) := DontCare
413
414      subDeqPolicy.io.request := Reverse(subDeqRequest.get)
415      subDeqSelValidVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => oh.valid)
416      subDeqSelOHVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => Reverse(oh.bits))
417    }
418
419    subDeqRequest.get := canIssueVec.asUInt & ~Cat(othersEntryOldestSel(0).bits, 0.U((params.numEnq).W))
420
421    deqSelValidVec(0) := othersEntryOldestSel(0).valid || subDeqSelValidVec.get(1)
422    deqSelValidVec(1) := subDeqSelValidVec.get(0)
423    deqSelOHVec(0) := Mux(othersEntryOldestSel(0).valid,
424                          Cat(othersEntryOldestSel(0).bits, 0.U((params.numEnq).W)),
425                          subDeqSelOHVec.get(1)) & canIssueMergeAllBusy(0)
426    deqSelOHVec(1) := subDeqSelOHVec.get(0) & canIssueMergeAllBusy(1)
427
428    finalDeqSelValidVec.zip(finalDeqSelOHVec).zip(deqSelValidVec).zip(deqSelOHVec).zipWithIndex.foreach { case ((((selValid, selOH), deqValid), deqOH), i) =>
429      selValid := deqValid && deqOH.orR && deqBeforeDly(i).ready
430      selOH := deqOH
431    }
432  }
433  else {
434    enqEntryOldestSel := NewAgeDetector(numEntries = params.numEnq,
435      enq = VecInit(s0_doEnqSelValidVec),
436      canIssue = VecInit(deqCanIssue.map(_(params.numEnq - 1, 0)))
437    )
438
439    if (params.isAllComp || params.isAllSimp) {
440      othersEntryOldestSel := AgeDetector(numEntries = params.numEntries - params.numEnq,
441        enq = othersEntryEnqSelVec.get,
442        canIssue = VecInit(deqCanIssue.map(_(params.numEntries - 1, params.numEnq)))
443      )
444
445      deqSelValidVec.zip(deqSelOHVec).zipWithIndex.foreach { case ((selValid, selOH), i) =>
446        if (params.exuBlockParams(i).fuConfigs.contains(FuConfig.FakeHystaCfg)) {
447          selValid := false.B
448          selOH := 0.U.asTypeOf(selOH)
449        } else {
450          selValid := othersEntryOldestSel(i).valid || enqEntryOldestSel(i).valid
451          selOH := Cat(othersEntryOldestSel(i).bits, Fill(params.numEnq, !othersEntryOldestSel(i).valid) & enqEntryOldestSel(i).bits)
452        }
453      }
454    }
455    else {
456      othersEntryOldestSel := DontCare
457
458      deqCanIssue.zipWithIndex.foreach { case (req, i) =>
459        simpAgeDetectRequest.get(i) := req(params.numEnq + params.numSimp - 1, params.numEnq)
460      }
461      simpAgeDetectRequest.get(params.numDeq) := VecInit(validVec.drop(params.numEnq).take(params.numSimp)).asUInt
462      if (params.numEnq == 2) {
463        simpAgeDetectRequest.get(params.numDeq + 1) := VecInit(validVec.drop(params.numEnq).take(params.numSimp)).asUInt & ~simpEntryOldestSel.get(params.numDeq).bits
464      }
465
466      simpEntryOldestSel.get := AgeDetector(numEntries = params.numSimp,
467        enq = simpEntryEnqSelVec.get,
468        canIssue = simpAgeDetectRequest.get
469      )
470
471      compEntryOldestSel.get := AgeDetector(numEntries = params.numComp,
472        enq = compEntryEnqSelVec.get,
473        canIssue = VecInit(deqCanIssue.map(_(params.numEntries - 1, params.numEnq + params.numSimp)))
474      )
475
476      deqSelValidVec.zip(deqSelOHVec).zipWithIndex.foreach { case ((selValid, selOH), i) =>
477        if (params.exuBlockParams(i).fuConfigs.contains(FuConfig.FakeHystaCfg)) {
478          selValid := false.B
479          selOH := 0.U.asTypeOf(selOH)
480        } else {
481          selValid := compEntryOldestSel.get(i).valid || simpEntryOldestSel.get(i).valid || enqEntryOldestSel(i).valid
482          selOH := Cat(
483            compEntryOldestSel.get(i).bits,
484            Fill(params.numSimp, !compEntryOldestSel.get(i).valid) & simpEntryOldestSel.get(i).bits,
485            Fill(params.numEnq, !compEntryOldestSel.get(i).valid && !simpEntryOldestSel.get(i).valid) & enqEntryOldestSel(i).bits
486          )
487        }
488      }
489    }
490
491    finalDeqSelValidVec.zip(finalDeqSelOHVec).zip(deqSelValidVec).zip(deqSelOHVec).zipWithIndex.foreach { case ((((selValid, selOH), deqValid), deqOH), i) =>
492      selValid := deqValid && deqBeforeDly(i).ready
493      selOH := deqOH
494    }
495  }
496
497  val toBusyTableDeqResp = Wire(Vec(params.numDeq, ValidIO(new IssueQueueDeqRespBundle)))
498
499  toBusyTableDeqResp.zipWithIndex.foreach { case (deqResp, i) =>
500    deqResp.valid := finalDeqSelValidVec(i)
501    deqResp.bits.resp   := RespType.success
502    deqResp.bits.robIdx := DontCare
503    deqResp.bits.fuType := deqBeforeDly(i).bits.common.fuType
504    deqResp.bits.uopIdx.foreach(_ := DontCare)
505  }
506
507  //fuBusyTable
508  fuBusyTableWrite.zip(fuBusyTableRead).zipWithIndex.foreach { case ((busyTableWrite: Option[FuBusyTableWrite], busyTableRead: Option[FuBusyTableRead]), i) =>
509    if(busyTableWrite.nonEmpty) {
510      val btwr = busyTableWrite.get
511      val btrd = busyTableRead.get
512      btwr.io.in.deqResp := toBusyTableDeqResp(i)
513      btwr.io.in.og0Resp := io.og0Resp(i)
514      btwr.io.in.og1Resp := io.og1Resp(i)
515      btrd.io.in.fuBusyTable := btwr.io.out.fuBusyTable
516      btrd.io.in.fuTypeRegVec := fuTypeVec
517      fuBusyTableMask(i) := btrd.io.out.fuBusyTableMask
518    }
519    else {
520      fuBusyTableMask(i) := 0.U(params.numEntries.W)
521    }
522  }
523
524  //wbfuBusyTable write
525  intWbBusyTableWrite.zip(intWbBusyTableOut).zip(intDeqRespSetOut).zipWithIndex.foreach { case (((busyTableWrite: Option[FuBusyTableWrite], busyTable: Option[UInt]), deqResp), i) =>
526    if(busyTableWrite.nonEmpty) {
527      val btwr = busyTableWrite.get
528      val bt = busyTable.get
529      val dq = deqResp.get
530      btwr.io.in.deqResp := toBusyTableDeqResp(i)
531      btwr.io.in.og0Resp := io.og0Resp(i)
532      btwr.io.in.og1Resp := io.og1Resp(i)
533      bt := btwr.io.out.fuBusyTable
534      dq := btwr.io.out.deqRespSet
535    }
536  }
537
538  fpWbBusyTableWrite.zip(fpWbBusyTableOut).zip(fpDeqRespSetOut).zipWithIndex.foreach { case (((busyTableWrite: Option[FuBusyTableWrite], busyTable: Option[UInt]), deqResp), i) =>
539    if (busyTableWrite.nonEmpty) {
540      val btwr = busyTableWrite.get
541      val bt = busyTable.get
542      val dq = deqResp.get
543      btwr.io.in.deqResp := toBusyTableDeqResp(i)
544      btwr.io.in.og0Resp := io.og0Resp(i)
545      btwr.io.in.og1Resp := io.og1Resp(i)
546      bt := btwr.io.out.fuBusyTable
547      dq := btwr.io.out.deqRespSet
548    }
549  }
550
551  vfWbBusyTableWrite.zip(vfWbBusyTableOut).zip(vfDeqRespSetOut).zipWithIndex.foreach { case (((busyTableWrite: Option[FuBusyTableWrite], busyTable: Option[UInt]), deqResp), i) =>
552    if (busyTableWrite.nonEmpty) {
553      val btwr = busyTableWrite.get
554      val bt = busyTable.get
555      val dq = deqResp.get
556      btwr.io.in.deqResp := toBusyTableDeqResp(i)
557      btwr.io.in.og0Resp := io.og0Resp(i)
558      btwr.io.in.og1Resp := io.og1Resp(i)
559      bt := btwr.io.out.fuBusyTable
560      dq := btwr.io.out.deqRespSet
561    }
562  }
563
564  //wbfuBusyTable read
565  intWbBusyTableRead.zip(intWbBusyTableIn).zipWithIndex.foreach { case ((busyTableRead: Option[FuBusyTableRead], busyTable: Option[UInt]), i) =>
566    if(busyTableRead.nonEmpty) {
567      val btrd = busyTableRead.get
568      val bt = busyTable.get
569      btrd.io.in.fuBusyTable := bt
570      btrd.io.in.fuTypeRegVec := fuTypeVec
571      intWbBusyTableMask(i) := btrd.io.out.fuBusyTableMask
572    }
573    else {
574      intWbBusyTableMask(i) := 0.U(params.numEntries.W)
575    }
576  }
577  fpWbBusyTableRead.zip(fpWbBusyTableIn).zipWithIndex.foreach { case ((busyTableRead: Option[FuBusyTableRead], busyTable: Option[UInt]), i) =>
578    if (busyTableRead.nonEmpty) {
579      val btrd = busyTableRead.get
580      val bt = busyTable.get
581      btrd.io.in.fuBusyTable := bt
582      btrd.io.in.fuTypeRegVec := fuTypeVec
583      fpWbBusyTableMask(i) := btrd.io.out.fuBusyTableMask
584    }
585    else {
586      fpWbBusyTableMask(i) := 0.U(params.numEntries.W)
587    }
588  }
589  vfWbBusyTableRead.zip(vfWbBusyTableIn).zipWithIndex.foreach { case ((busyTableRead: Option[FuBusyTableRead], busyTable: Option[UInt]), i) =>
590    if (busyTableRead.nonEmpty) {
591      val btrd = busyTableRead.get
592      val bt = busyTable.get
593      btrd.io.in.fuBusyTable := bt
594      btrd.io.in.fuTypeRegVec := fuTypeVec
595      vfWbBusyTableMask(i) := btrd.io.out.fuBusyTableMask
596    }
597    else {
598      vfWbBusyTableMask(i) := 0.U(params.numEntries.W)
599    }
600  }
601
602  wakeUpQueues.zipWithIndex.foreach { case (wakeUpQueueOption, i) =>
603    wakeUpQueueOption.foreach {
604      wakeUpQueue =>
605        val flush = Wire(new WakeupQueueFlush)
606        flush.redirect := io.flush
607        flush.ldCancel := io.ldCancel
608        flush.og0Fail := io.og0Resp(i).valid && RespType.isBlocked(io.og0Resp(i).bits.resp)
609        flush.og1Fail := io.og1Resp(i).valid && RespType.isBlocked(io.og1Resp(i).bits.resp)
610        wakeUpQueue.io.flush := flush
611        wakeUpQueue.io.enq.valid := deqBeforeDly(i).valid
612        wakeUpQueue.io.enq.bits.uop :<= deqBeforeDly(i).bits.common
613        wakeUpQueue.io.enq.bits.uop.pdestCopy.foreach(_ := 0.U)
614        wakeUpQueue.io.enq.bits.lat := getDeqLat(i, deqBeforeDly(i).bits.common.fuType)
615    }
616  }
617
618  deqBeforeDly.zipWithIndex.foreach { case (deq, i) =>
619    deq.valid                := finalDeqSelValidVec(i) && !cancelDeqVec(i)
620    deq.bits.addrOH          := finalDeqSelOHVec(i)
621    deq.bits.common.isFirstIssue := deqFirstIssueVec(i)
622    deq.bits.common.iqIdx    := OHToUInt(finalDeqSelOHVec(i))
623    deq.bits.common.fuType   := IQFuType.readFuType(deqEntryVec(i).bits.status.fuType, params.getFuCfgs.map(_.fuType)).asUInt
624    deq.bits.common.fuOpType := deqEntryVec(i).bits.payload.fuOpType
625    deq.bits.common.rfWen.foreach(_ := deqEntryVec(i).bits.payload.rfWen)
626    deq.bits.common.fpWen.foreach(_ := deqEntryVec(i).bits.payload.fpWen)
627    deq.bits.common.vecWen.foreach(_ := deqEntryVec(i).bits.payload.vecWen)
628    deq.bits.common.flushPipe.foreach(_ := deqEntryVec(i).bits.payload.flushPipe)
629    deq.bits.common.pdest := deqEntryVec(i).bits.payload.pdest
630    deq.bits.common.robIdx := deqEntryVec(i).bits.status.robIdx
631
632    require(deq.bits.common.dataSources.size <= finalDataSources(i).size)
633    deq.bits.common.dataSources.zip(finalDataSources(i)).foreach { case (sink, source) => sink := source}
634    deq.bits.common.l1ExuOH.foreach(_.zip(finalWakeUpL1ExuOH.get(i)).foreach { case (sink, source) => sink := source})
635    deq.bits.common.srcTimer.foreach(_ := DontCare)
636    deq.bits.common.loadDependency.foreach(_.zip(finalLoadDependency(i)).foreach { case (sink, source) => sink := source})
637    deq.bits.common.src := DontCare
638    deq.bits.common.preDecode.foreach(_ := deqEntryVec(i).bits.payload.preDecodeInfo)
639
640    deq.bits.rf.zip(deqEntryVec(i).bits.status.srcStatus.map(_.psrc)).zip(deqEntryVec(i).bits.status.srcStatus.map(_.srcType)).foreach { case ((rf, psrc), srcType) =>
641      // psrc in status array can be pregIdx of IntRegFile or VfRegFile
642      rf.foreach(_.addr := psrc)
643      rf.foreach(_.srcType := srcType)
644    }
645    deq.bits.srcType.zip(deqEntryVec(i).bits.status.srcStatus.map(_.srcType)).foreach { case (sink, source) =>
646      sink := source
647    }
648    deq.bits.immType := deqEntryVec(i).bits.payload.selImm
649    deq.bits.common.imm := deqEntryVec(i).bits.imm.getOrElse(0.U)
650
651    deq.bits.common.perfDebugInfo := deqEntryVec(i).bits.payload.debugInfo
652    deq.bits.common.perfDebugInfo.selectTime := GTimer()
653    deq.bits.common.perfDebugInfo.issueTime := GTimer() + 1.U
654  }
655
656  io.deqDelay.zip(deqBeforeDly).foreach { case (deqDly, deq) =>
657    NewPipelineConnect(
658      deq, deqDly, deqDly.valid,
659      false.B,
660      Option("Scheduler2DataPathPipe")
661    )
662  }
663  if(backendParams.debugEn) {
664    dontTouch(io.deqDelay)
665  }
666  io.wakeupToIQ.zipWithIndex.foreach { case (wakeup, i) =>
667    if (wakeUpQueues(i).nonEmpty && finalWakeUpL1ExuOH.nonEmpty) {
668      wakeup.valid := wakeUpQueues(i).get.io.deq.valid
669      wakeup.bits.fromExuInput(wakeUpQueues(i).get.io.deq.bits, finalWakeUpL1ExuOH.get(i))
670      wakeup.bits.loadDependency := wakeUpQueues(i).get.io.deq.bits.loadDependency.getOrElse(0.U.asTypeOf(wakeup.bits.loadDependency))
671      wakeup.bits.is0Lat := getDeqLat(i, wakeUpQueues(i).get.io.deq.bits.fuType) === 0.U
672    } else if (wakeUpQueues(i).nonEmpty) {
673      wakeup.valid := wakeUpQueues(i).get.io.deq.valid
674      wakeup.bits.fromExuInput(wakeUpQueues(i).get.io.deq.bits)
675      wakeup.bits.loadDependency := wakeUpQueues(i).get.io.deq.bits.loadDependency.getOrElse(0.U.asTypeOf(wakeup.bits.loadDependency))
676      wakeup.bits.is0Lat := getDeqLat(i, wakeUpQueues(i).get.io.deq.bits.fuType) === 0.U
677    } else {
678      wakeup.valid := false.B
679      wakeup.bits := 0.U.asTypeOf(wakeup.bits)
680      wakeup.bits.is0Lat :=  0.U
681    }
682    if (wakeUpQueues(i).nonEmpty) {
683      wakeup.bits.rfWen  := (if (wakeUpQueues(i).get.io.deq.bits.rfWen .nonEmpty) wakeUpQueues(i).get.io.deq.valid && wakeUpQueues(i).get.io.deq.bits.rfWen .get else false.B)
684      wakeup.bits.fpWen  := (if (wakeUpQueues(i).get.io.deq.bits.fpWen .nonEmpty) wakeUpQueues(i).get.io.deq.valid && wakeUpQueues(i).get.io.deq.bits.fpWen .get else false.B)
685      wakeup.bits.vecWen := (if (wakeUpQueues(i).get.io.deq.bits.vecWen.nonEmpty) wakeUpQueues(i).get.io.deq.valid && wakeUpQueues(i).get.io.deq.bits.vecWen.get else false.B)
686    }
687
688    if(wakeUpQueues(i).nonEmpty && wakeup.bits.pdestCopy.nonEmpty){
689      wakeup.bits.pdestCopy.get := wakeUpQueues(i).get.io.deq.bits.pdestCopy.get
690    }
691    if (wakeUpQueues(i).nonEmpty && wakeup.bits.rfWenCopy.nonEmpty) {
692      wakeup.bits.rfWenCopy.get := wakeUpQueues(i).get.io.deq.bits.rfWenCopy.get
693    }
694    if (wakeUpQueues(i).nonEmpty && wakeup.bits.fpWenCopy.nonEmpty) {
695      wakeup.bits.fpWenCopy.get := wakeUpQueues(i).get.io.deq.bits.fpWenCopy.get
696    }
697    if (wakeUpQueues(i).nonEmpty && wakeup.bits.vecWenCopy.nonEmpty) {
698      wakeup.bits.vecWenCopy.get := wakeUpQueues(i).get.io.deq.bits.vecWenCopy.get
699    }
700    if (wakeUpQueues(i).nonEmpty && wakeup.bits.loadDependencyCopy.nonEmpty) {
701      wakeup.bits.loadDependencyCopy.get := wakeUpQueues(i).get.io.deq.bits.loadDependencyCopy.get
702    }
703  }
704
705  // Todo: better counter implementation
706  private val enqHasValid = validVec.take(params.numEnq).reduce(_ | _)
707  private val enqEntryValidCnt = PopCount(validVec.take(params.numEnq))
708  private val othersValidCnt = PopCount(validVec.drop(params.numEnq))
709  private val enqEntryValidCntDeq0 = PopCount(
710    validVec.take(params.numEnq).zip(deqCanAcceptVec(0).take(params.numEnq)).map { case (a, b) => a && b }
711  )
712  private val othersValidCntDeq0 = PopCount(
713    validVec.drop(params.numEnq).zip(deqCanAcceptVec(0).drop(params.numEnq)).map { case (a, b) => a && b }
714  )
715  private val enqEntryValidCntDeq1 = PopCount(
716    validVec.take(params.numEnq).zip(deqCanAcceptVec.last.take(params.numEnq)).map { case (a, b) => a && b }
717  )
718  private val othersValidCntDeq1 = PopCount(
719    validVec.drop(params.numEnq).zip(deqCanAcceptVec.last.drop(params.numEnq)).map { case (a, b) => a && b }
720  )
721  protected val deqCanAcceptVecEnq: Seq[IndexedSeq[Bool]] = deqFuCfgs.map { fuCfgs: Seq[FuConfig] =>
722    io.enq.map(_.bits.fuType).map(fuType =>
723      FuType.FuTypeOrR(fuType, fuCfgs.map(_.fuType)))
724  }
725  protected val enqValidCntDeq0 = PopCount(io.enq.map(_.fire).zip(deqCanAcceptVecEnq(0)).map { case (a, b) => a && b })
726  protected val enqValidCntDeq1 = PopCount(io.enq.map(_.fire).zip(deqCanAcceptVecEnq.last).map { case (a, b) => a && b })
727  io.validCntDeqVec.head := RegNext(enqEntryValidCntDeq0 +& othersValidCntDeq0 - io.deqDelay.head.fire) // validCntDeqVec(0)
728  io.validCntDeqVec.last := RegNext(enqEntryValidCntDeq1 +& othersValidCntDeq1 - io.deqDelay.last.fire) // validCntDeqVec(1)
729  io.status.leftVec(0) := validVec.drop(params.numEnq).reduce(_ & _)
730  for (i <- 0 until params.numEnq) {
731    io.status.leftVec(i + 1) := othersValidCnt === (params.numEntries - params.numEnq - (i + 1)).U
732  }
733  private val othersLeftOneCaseVec = Wire(Vec(params.numEntries - params.numEnq, UInt((params.numEntries - params.numEnq).W)))
734  othersLeftOneCaseVec.zipWithIndex.foreach { case (leftone, i) =>
735    leftone := ~(1.U((params.numEntries - params.numEnq).W) << i)
736  }
737  private val othersLeftOne = othersLeftOneCaseVec.map(_ === VecInit(validVec.drop(params.numEnq)).asUInt).reduce(_ | _)
738  private val othersCanotIn = othersLeftOne || validVec.drop(params.numEnq).reduce(_ & _)
739
740  io.enq.foreach(_.ready := !othersCanotIn || !enqHasValid)
741  io.status.empty := !Cat(validVec).orR
742  io.status.full := othersCanotIn
743  io.status.validCnt := PopCount(validVec)
744
745  protected def getDeqLat(deqPortIdx: Int, fuType: UInt) : UInt = {
746    Mux1H(wakeupFuLatencyMaps(deqPortIdx) map { case (k, v) => (fuType(k.id), v.U) })
747  }
748
749  // issue perf counter
750  // enq count
751  XSPerfAccumulate("enq_valid_cnt", PopCount(io.enq.map(_.fire)))
752  XSPerfAccumulate("enq_fire_cnt", PopCount(io.enq.map(_.fire)))
753  XSPerfAccumulate("enq_alu_fire_cnt", PopCount(io.enq.map { case enq => enq.fire && FuType.isAlu(enq.bits.fuType) }))
754  XSPerfAccumulate("enq_brh_fire_cnt", PopCount(io.enq.map { case enq => enq.fire && FuType.isBrh(enq.bits.fuType) }))
755  XSPerfAccumulate("deqDelay0_fire_cnt", PopCount(io.deqDelay.head.fire))
756  XSPerfAccumulate("deqDelay1_fire_cnt", PopCount(io.deqDelay.last.fire))
757  // valid count
758  XSPerfHistogram("enq_entry_valid_cnt", enqEntryValidCnt, true.B, 0, params.numEnq + 1)
759  XSPerfHistogram("other_entry_valid_cnt", othersValidCnt, true.B, 0, params.numEntries - params.numEnq + 1)
760  XSPerfHistogram("valid_cnt", PopCount(validVec), true.B, 0, params.numEntries + 1)
761  // only split when more than 1 func type
762  if (params.getFuCfgs.size > 0) {
763    for (t <- FuType.functionNameMap.keys) {
764      val fuName = FuType.functionNameMap(t)
765      if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _)) {
766        XSPerfHistogram(s"valid_cnt_hist_futype_${fuName}", PopCount(validVec.zip(fuTypeVec).map { case (v, fu) => v && fu === t.U }), true.B, 0, params.numEntries, 1)
767      }
768    }
769  }
770  // ready instr count
771  private val readyEntriesCnt = PopCount(validVec.zip(canIssueVec).map(x => x._1 && x._2))
772  XSPerfHistogram("ready_cnt", readyEntriesCnt, true.B, 0, params.numEntries + 1)
773  // only split when more than 1 func type
774  if (params.getFuCfgs.size > 0) {
775    for (t <- FuType.functionNameMap.keys) {
776      val fuName = FuType.functionNameMap(t)
777      if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _)) {
778        XSPerfHistogram(s"ready_cnt_hist_futype_${fuName}", PopCount(validVec.zip(canIssueVec).zip(fuTypeVec).map { case ((v, c), fu) => v && c && fu === t.U }), true.B, 0, params.numEntries, 1)
779      }
780    }
781  }
782
783  // deq instr count
784  XSPerfAccumulate("issue_instr_pre_count", PopCount(deqBeforeDly.map(_.valid)))
785  XSPerfHistogram("issue_instr_pre_count_hist", PopCount(deqBeforeDly.map(_.valid)), true.B, 0, params.numDeq + 1, 1)
786  XSPerfAccumulate("issue_instr_count", PopCount(io.deqDelay.map(_.valid)))
787  XSPerfHistogram("issue_instr_count_hist", PopCount(io.deqDelay.map(_.valid)), true.B, 0, params.numDeq + 1, 1)
788
789  // deq instr data source count
790  XSPerfAccumulate("issue_datasource_reg", deqBeforeDly.map{ deq =>
791    PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) })
792  }.reduce(_ +& _))
793  XSPerfAccumulate("issue_datasource_bypass", deqBeforeDly.map{ deq =>
794    PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) })
795  }.reduce(_ +& _))
796  XSPerfAccumulate("issue_datasource_forward", deqBeforeDly.map{ deq =>
797    PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) })
798  }.reduce(_ +& _))
799  XSPerfAccumulate("issue_datasource_noreg", deqBeforeDly.map{ deq =>
800    PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) })
801  }.reduce(_ +& _))
802
803  XSPerfHistogram("issue_datasource_reg_hist", deqBeforeDly.map{ deq =>
804    PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) })
805  }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1)
806  XSPerfHistogram("issue_datasource_bypass_hist", deqBeforeDly.map{ deq =>
807    PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) })
808  }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1)
809  XSPerfHistogram("issue_datasource_forward_hist", deqBeforeDly.map{ deq =>
810    PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) })
811  }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1)
812  XSPerfHistogram("issue_datasource_noreg_hist", deqBeforeDly.map{ deq =>
813    PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) })
814  }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1)
815
816  // deq instr data source count for each futype
817  for (t <- FuType.functionNameMap.keys) {
818    val fuName = FuType.functionNameMap(t)
819    if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _)) {
820      XSPerfAccumulate(s"issue_datasource_reg_futype_${fuName}", deqBeforeDly.map{ deq =>
821        PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U })
822      }.reduce(_ +& _))
823      XSPerfAccumulate(s"issue_datasource_bypass_futype_${fuName}", deqBeforeDly.map{ deq =>
824        PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U })
825      }.reduce(_ +& _))
826      XSPerfAccumulate(s"issue_datasource_forward_futype_${fuName}", deqBeforeDly.map{ deq =>
827        PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U })
828      }.reduce(_ +& _))
829      XSPerfAccumulate(s"issue_datasource_noreg_futype_${fuName}", deqBeforeDly.map{ deq =>
830        PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U })
831      }.reduce(_ +& _))
832
833      XSPerfHistogram(s"issue_datasource_reg_hist_futype_${fuName}", deqBeforeDly.map{ deq =>
834        PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U })
835      }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1)
836      XSPerfHistogram(s"issue_datasource_bypass_hist_futype_${fuName}", deqBeforeDly.map{ deq =>
837        PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U })
838      }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1)
839      XSPerfHistogram(s"issue_datasource_forward_hist_futype_${fuName}", deqBeforeDly.map{ deq =>
840        PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U })
841      }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1)
842      XSPerfHistogram(s"issue_datasource_noreg_hist_futype_${fuName}", deqBeforeDly.map{ deq =>
843        PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U })
844      }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1)
845    }
846  }
847}
848
849class IssueQueueLoadBundle(implicit p: Parameters) extends XSBundle {
850  val fastMatch = UInt(backendParams.LduCnt.W)
851  val fastImm = UInt(12.W)
852}
853
854class IssueQueueIntIO()(implicit p: Parameters, params: IssueBlockParams) extends IssueQueueIO
855
856class IssueQueueIntImp(override val wrapper: IssueQueue)(implicit p: Parameters, iqParams: IssueBlockParams)
857  extends IssueQueueImp(wrapper)
858{
859  io.suggestName("none")
860  override lazy val io = IO(new IssueQueueIntIO).suggestName("io")
861
862  deqBeforeDly.zipWithIndex.foreach{ case (deq, i) => {
863    deq.bits.common.pc.foreach(_ := DontCare)
864    deq.bits.common.preDecode.foreach(_ := deqEntryVec(i).bits.payload.preDecodeInfo)
865    deq.bits.common.ftqIdx.foreach(_ := deqEntryVec(i).bits.payload.ftqPtr)
866    deq.bits.common.ftqOffset.foreach(_ := deqEntryVec(i).bits.payload.ftqOffset)
867    deq.bits.common.predictInfo.foreach(x => {
868      x.target := DontCare
869      x.taken := deqEntryVec(i).bits.payload.pred_taken
870    })
871    // for std
872    deq.bits.common.sqIdx.foreach(_ := deqEntryVec(i).bits.payload.sqIdx)
873    // for i2f
874    deq.bits.common.fpu.foreach(_ := deqEntryVec(i).bits.payload.fpu)
875  }}
876}
877
878class IssueQueueVfImp(override val wrapper: IssueQueue)(implicit p: Parameters, iqParams: IssueBlockParams)
879  extends IssueQueueImp(wrapper)
880{
881  deqBeforeDly.zipWithIndex.foreach{ case (deq, i) => {
882    deq.bits.common.fpu.foreach(_ := deqEntryVec(i).bits.payload.fpu)
883    deq.bits.common.vpu.foreach(_ := deqEntryVec(i).bits.payload.vpu)
884    deq.bits.common.vpu.foreach(_.vuopIdx := deqEntryVec(i).bits.payload.uopIdx)
885    deq.bits.common.vpu.foreach(_.lastUop := deqEntryVec(i).bits.payload.lastUop)
886  }}
887}
888
889class IssueQueueFpImp(override val wrapper: IssueQueue)(implicit p: Parameters, iqParams: IssueBlockParams)
890  extends IssueQueueImp(wrapper)
891{
892  deqBeforeDly.zipWithIndex.foreach{ case (deq, i) => {
893    deq.bits.common.fpu.foreach(_ := deqEntryVec(i).bits.payload.fpu)
894    deq.bits.common.vpu.foreach(_ := deqEntryVec(i).bits.payload.vpu)
895    deq.bits.common.vpu.foreach(_.vuopIdx := deqEntryVec(i).bits.payload.uopIdx)
896    deq.bits.common.vpu.foreach(_.lastUop := deqEntryVec(i).bits.payload.lastUop)
897  }}
898}
899
900class IssueQueueMemBundle(implicit p: Parameters, params: IssueBlockParams) extends Bundle {
901  val feedbackIO = Flipped(Vec(params.numDeq, new MemRSFeedbackIO))
902
903  // TODO: is still needed?
904  val checkWait = new Bundle {
905    val stIssuePtr = Input(new SqPtr)
906    val memWaitUpdateReq = Flipped(new MemWaitUpdateReq)
907  }
908  val loadFastMatch = Output(Vec(params.LdExuCnt, new IssueQueueLoadBundle))
909
910  // load wakeup
911  val loadWakeUp = Input(Vec(params.LdExuCnt, ValidIO(new DynInst())))
912
913  // vector
914  val sqDeqPtr = OptionWrapper(params.isVecMemIQ, Input(new SqPtr))
915  val lqDeqPtr = OptionWrapper(params.isVecMemIQ, Input(new LqPtr))
916}
917
918class IssueQueueMemIO(implicit p: Parameters, params: IssueBlockParams) extends IssueQueueIO {
919  val memIO = Some(new IssueQueueMemBundle)
920}
921
922class IssueQueueMemAddrImp(override val wrapper: IssueQueue)(implicit p: Parameters, params: IssueBlockParams)
923  extends IssueQueueImp(wrapper) with HasCircularQueuePtrHelper {
924
925  require(params.StdCnt == 0 && (params.LduCnt + params.StaCnt + params.HyuCnt) > 0, "IssueQueueMemAddrImp can only be instance of MemAddr IQ, " +
926    s"StdCnt: ${params.StdCnt}, LduCnt: ${params.LduCnt}, StaCnt: ${params.StaCnt}, HyuCnt: ${params.HyuCnt}")
927  println(s"[IssueQueueMemAddrImp] StdCnt: ${params.StdCnt}, LduCnt: ${params.LduCnt}, StaCnt: ${params.StaCnt}, HyuCnt: ${params.HyuCnt}")
928
929  io.suggestName("none")
930  override lazy val io = IO(new IssueQueueMemIO).suggestName("io")
931  private val memIO = io.memIO.get
932
933  memIO.loadFastMatch := 0.U.asTypeOf(memIO.loadFastMatch) // TODO: is still needed?
934
935  entries.io.fromMem.get.slowResp.zipWithIndex.foreach { case (slowResp, i) =>
936    slowResp.valid       := memIO.feedbackIO(i).feedbackSlow.valid
937    slowResp.bits.robIdx := memIO.feedbackIO(i).feedbackSlow.bits.robIdx
938    slowResp.bits.resp   := Mux(memIO.feedbackIO(i).feedbackSlow.bits.hit, RespType.success, RespType.block)
939    slowResp.bits.fuType := DontCare
940  }
941
942  entries.io.fromMem.get.fastResp.zipWithIndex.foreach { case (fastResp, i) =>
943    fastResp.valid       := memIO.feedbackIO(i).feedbackFast.valid
944    fastResp.bits.robIdx := memIO.feedbackIO(i).feedbackFast.bits.robIdx
945    fastResp.bits.resp   := Mux(memIO.feedbackIO(i).feedbackFast.bits.hit, RespType.success, RespType.block)
946    fastResp.bits.fuType := DontCare
947  }
948
949  // load wakeup
950  val loadWakeUpIter = memIO.loadWakeUp.iterator
951  io.wakeupToIQ.zip(params.exuBlockParams).zipWithIndex.foreach { case ((wakeup, param), i) =>
952    if (param.hasLoadExu) {
953      require(wakeUpQueues(i).isEmpty)
954      val uop = loadWakeUpIter.next()
955
956      wakeup.valid := GatedValidRegNext(uop.fire)
957      wakeup.bits.rfWen  := GatedValidRegNext(uop.bits.rfWen  && uop.fire)
958      wakeup.bits.fpWen  := GatedValidRegNext(uop.bits.fpWen  && uop.fire)
959      wakeup.bits.vecWen := GatedValidRegNext(uop.bits.vecWen && uop.fire)
960      wakeup.bits.pdest  := RegEnable(uop.bits.pdest, uop.fire)
961      wakeup.bits.loadDependency.foreach(_ := 0.U) // this is correct for load only
962
963      wakeup.bits.rfWenCopy .foreach(_.foreach(_ := GatedValidRegNext(uop.bits.rfWen  && uop.fire)))
964      wakeup.bits.fpWenCopy .foreach(_.foreach(_ := GatedValidRegNext(uop.bits.fpWen  && uop.fire)))
965      wakeup.bits.vecWenCopy.foreach(_.foreach(_ := GatedValidRegNext(uop.bits.vecWen && uop.fire)))
966      wakeup.bits.pdestCopy .foreach(_.foreach(_ := RegEnable(uop.bits.pdest, uop.fire)))
967      wakeup.bits.loadDependencyCopy.foreach(x => x := 0.U.asTypeOf(x)) // this is correct for load only
968
969      wakeup.bits.is0Lat := 0.U
970    }
971  }
972  require(!loadWakeUpIter.hasNext)
973
974  deqBeforeDly.zipWithIndex.foreach { case (deq, i) =>
975    deq.bits.common.loadWaitBit.foreach(_ := deqEntryVec(i).bits.payload.loadWaitBit)
976    deq.bits.common.waitForRobIdx.foreach(_ := deqEntryVec(i).bits.payload.waitForRobIdx)
977    deq.bits.common.storeSetHit.foreach(_ := deqEntryVec(i).bits.payload.storeSetHit)
978    deq.bits.common.loadWaitStrict.foreach(_ := deqEntryVec(i).bits.payload.loadWaitStrict)
979    deq.bits.common.ssid.foreach(_ := deqEntryVec(i).bits.payload.ssid)
980    deq.bits.common.sqIdx.get := deqEntryVec(i).bits.payload.sqIdx
981    deq.bits.common.lqIdx.get := deqEntryVec(i).bits.payload.lqIdx
982    deq.bits.common.ftqIdx.foreach(_ := deqEntryVec(i).bits.payload.ftqPtr)
983    deq.bits.common.ftqOffset.foreach(_ := deqEntryVec(i).bits.payload.ftqOffset)
984  }
985}
986
987class IssueQueueVecMemImp(override val wrapper: IssueQueue)(implicit p: Parameters, params: IssueBlockParams)
988  extends IssueQueueImp(wrapper) with HasCircularQueuePtrHelper {
989
990  require((params.VlduCnt + params.VstuCnt) > 0, "IssueQueueVecMemImp can only be instance of VecMem IQ")
991  println(s"[IssueQueueVecMemImp] VlduCnt: ${params.VlduCnt}, VstuCnt: ${params.VstuCnt}")
992
993  io.suggestName("none")
994  override lazy val io = IO(new IssueQueueMemIO).suggestName("io")
995  private val memIO = io.memIO.get
996
997  require(params.numExu == 1, "VecMem IssueQueue has not supported more than 1 deq ports")
998
999  def selectOldUop(robIdx: Seq[RobPtr], uopIdx: Seq[UInt], valid: Seq[Bool]): Vec[Bool] = {
1000    val compareVec = (0 until robIdx.length).map(i => (0 until i).map(j => isAfter(robIdx(j), robIdx(i)) || (robIdx(j).value === robIdx(i).value && uopIdx(i) < uopIdx(j))))
1001    val resultOnehot = VecInit((0 until robIdx.length).map(i => Cat((0 until robIdx.length).map(j =>
1002      (if (j < i) !valid(j) || compareVec(i)(j)
1003      else if (j == i) valid(i)
1004      else !valid(j) || !compareVec(j)(i))
1005    )).andR))
1006    resultOnehot
1007  }
1008
1009  val robIdxVec = entries.io.robIdx.get
1010  val uopIdxVec = entries.io.uopIdx.get
1011  val allEntryOldestOH = selectOldUop(robIdxVec, uopIdxVec, validVec)
1012
1013  deqSelValidVec.head := (allEntryOldestOH.asUInt & canIssueVec.asUInt).orR
1014  deqSelOHVec.head := allEntryOldestOH.asUInt & canIssueVec.asUInt
1015  finalDeqSelValidVec.head := (allEntryOldestOH.asUInt & canIssueVec.asUInt).orR && deqBeforeDly.head.ready
1016  finalDeqSelOHVec.head := deqSelOHVec.head
1017
1018  for (i <- entries.io.enq.indices) {
1019    entries.io.enq(i).bits.status match { case enqData =>
1020      enqData.vecMem.get.sqIdx := s0_enqBits(i).sqIdx
1021      enqData.vecMem.get.lqIdx := s0_enqBits(i).lqIdx
1022
1023      // update blocked
1024      val isLsqHead = {
1025        s0_enqBits(i).lqIdx <= memIO.lqDeqPtr.get &&
1026        s0_enqBits(i).sqIdx <= memIO.sqDeqPtr.get
1027      }
1028      enqData.blocked          := !isLsqHead
1029    }
1030  }
1031
1032  entries.io.fromMem.get.slowResp.zipWithIndex.foreach { case (slowResp, i) =>
1033    slowResp.valid                 := memIO.feedbackIO(i).feedbackSlow.valid
1034    slowResp.bits.robIdx           := memIO.feedbackIO(i).feedbackSlow.bits.robIdx
1035    slowResp.bits.resp             := Mux(memIO.feedbackIO(i).feedbackSlow.bits.hit, RespType.success, RespType.block)
1036    slowResp.bits.fuType           := DontCare
1037    slowResp.bits.uopIdx.get       := 0.U // Todo
1038  }
1039
1040  entries.io.fromMem.get.fastResp.zipWithIndex.foreach { case (fastResp, i) =>
1041    fastResp.valid                 := memIO.feedbackIO(i).feedbackFast.valid
1042    fastResp.bits.robIdx           := memIO.feedbackIO(i).feedbackFast.bits.robIdx
1043    fastResp.bits.resp             := Mux(memIO.feedbackIO(i).feedbackFast.bits.hit, RespType.success, RespType.block)
1044    fastResp.bits.fuType           := DontCare
1045    fastResp.bits.uopIdx.get       := 0.U // Todo
1046  }
1047
1048  entries.io.vecMemIn.get.sqDeqPtr := memIO.sqDeqPtr.get
1049  entries.io.vecMemIn.get.lqDeqPtr := memIO.lqDeqPtr.get
1050
1051
1052  deqBeforeDly.zipWithIndex.foreach { case (deq, i) =>
1053    deq.bits.common.sqIdx.foreach(_ := deqEntryVec(i).bits.status.vecMem.get.sqIdx)
1054    deq.bits.common.lqIdx.foreach(_ := deqEntryVec(i).bits.status.vecMem.get.lqIdx)
1055    if (params.isVecLduIQ) {
1056      deq.bits.common.ftqIdx.get := deqEntryVec(i).bits.payload.ftqPtr
1057      deq.bits.common.ftqOffset.get := deqEntryVec(i).bits.payload.ftqOffset
1058    }
1059    deq.bits.common.fpu.foreach(_ := deqEntryVec(i).bits.payload.fpu)
1060    deq.bits.common.vpu.foreach(_ := deqEntryVec(i).bits.payload.vpu)
1061    deq.bits.common.vpu.foreach(_.vuopIdx := deqEntryVec(i).bits.payload.uopIdx)
1062    deq.bits.common.vpu.foreach(_.lastUop := deqEntryVec(i).bits.payload.lastUop)
1063  }
1064}
1065