1package xiangshan.backend.issue 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 7import utility.{GTimer, HasCircularQueuePtrHelper, SelectOne} 8import utils._ 9import xiangshan._ 10import xiangshan.backend.Bundles._ 11import xiangshan.backend.issue.EntryBundles._ 12import xiangshan.backend.decode.{ImmUnion, Imm_LUI_LOAD} 13import xiangshan.backend.datapath.DataConfig._ 14import xiangshan.backend.datapath.DataSource 15import xiangshan.backend.fu.{FuConfig, FuType} 16import xiangshan.mem.{MemWaitUpdateReq, SqPtr, LqPtr} 17import xiangshan.backend.rob.RobPtr 18import xiangshan.backend.datapath.NewPipelineConnect 19 20class IssueQueue(params: IssueBlockParams)(implicit p: Parameters) extends LazyModule with HasXSParameter { 21 override def shouldBeInlined: Boolean = false 22 23 implicit val iqParams = params 24 lazy val module: IssueQueueImp = iqParams.schdType match { 25 case IntScheduler() => new IssueQueueIntImp(this) 26 case VfScheduler() => new IssueQueueVfImp(this) 27 case MemScheduler() => 28 if (iqParams.StdCnt == 0 && !iqParams.isVecMemIQ) new IssueQueueMemAddrImp(this) 29 else if (iqParams.isVecMemIQ) new IssueQueueVecMemImp(this) 30 else new IssueQueueIntImp(this) 31 case _ => null 32 } 33} 34 35class IssueQueueStatusBundle(numEnq: Int, numEntries: Int) extends Bundle { 36 val empty = Output(Bool()) 37 val full = Output(Bool()) 38 val validCnt = Output(UInt(log2Ceil(numEntries).W)) 39 val leftVec = Output(Vec(numEnq + 1, Bool())) 40} 41 42class IssueQueueDeqRespBundle(implicit p:Parameters, params: IssueBlockParams) extends EntryDeqRespBundle 43 44class IssueQueueIO()(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 45 // Inputs 46 val flush = Flipped(ValidIO(new Redirect)) 47 val enq = Vec(params.numEnq, Flipped(DecoupledIO(new DynInst))) 48 49 val og0Resp = Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle))) 50 val og1Resp = Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle))) 51 val finalIssueResp = OptionWrapper(params.LdExuCnt > 0, Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle)))) 52 val memAddrIssueResp = OptionWrapper(params.LdExuCnt > 0, Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle)))) 53 val wbBusyTableRead = Input(params.genWbFuBusyTableReadBundle()) 54 val wbBusyTableWrite = Output(params.genWbFuBusyTableWriteBundle()) 55 val wakeupFromWB: MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = Flipped(params.genWBWakeUpSinkValidBundle) 56 val wakeupFromIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(params.genIQWakeUpSinkValidBundle) 57 val og0Cancel = Input(ExuOH(backendParams.numExu)) 58 val og1Cancel = Input(ExuOH(backendParams.numExu)) 59 val ldCancel = Vec(backendParams.LduCnt + backendParams.HyuCnt, Flipped(new LoadCancelIO)) 60 61 // Outputs 62 val wakeupToIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = params.genIQWakeUpSourceValidBundle 63 val status = Output(new IssueQueueStatusBundle(params.numEnq, params.numEntries)) 64 // val statusNext = Output(new IssueQueueStatusBundle(params.numEnq)) 65 66 val deqDelay: MixedVec[DecoupledIO[IssueQueueIssueBundle]] = params.genIssueDecoupledBundle// = deq.cloneType 67 def allWakeUp = wakeupFromWB ++ wakeupFromIQ 68} 69 70class IssueQueueImp(override val wrapper: IssueQueue)(implicit p: Parameters, val params: IssueBlockParams) 71 extends LazyModuleImp(wrapper) 72 with HasXSParameter { 73 74 override def desiredName: String = s"${params.getIQName}" 75 76 println(s"[IssueQueueImp] ${params.getIQName} wakeupFromWB(${io.wakeupFromWB.size}), " + 77 s"wakeup exu in(${params.wakeUpInExuSources.size}): ${params.wakeUpInExuSources.map(_.name).mkString("{",",","}")}, " + 78 s"wakeup exu out(${params.wakeUpOutExuSources.size}): ${params.wakeUpOutExuSources.map(_.name).mkString("{",",","}")}, " + 79 s"numEntries: ${params.numEntries}, numRegSrc: ${params.numRegSrc}, " + 80 s"numEnq: ${params.numEnq}, numSimp: ${params.numSimp}, numComp: ${params.numComp}, numDeq: ${params.numDeq}, " + 81 s"isAllSimp: ${params.isAllSimp}, isAllComp: ${params.isAllComp}") 82 83 require(params.numExu <= 2, "IssueQueue has not supported more than 2 deq ports") 84 require(params.numEnq <= 2, "IssueQueue has not supported more than 2 enq ports") 85 require(params.numSimp == 0 || params.numSimp >= params.numEnq, "numSimp should be 0 or at least not less than numEnq") 86 require(params.numComp == 0 || params.numComp >= params.numEnq, "numComp should be 0 or at least not less than numEnq") 87 88 val deqFuCfgs : Seq[Seq[FuConfig]] = params.exuBlockParams.map(_.fuConfigs) 89 val allDeqFuCfgs : Seq[FuConfig] = params.exuBlockParams.flatMap(_.fuConfigs) 90 val fuCfgsCnt : Map[FuConfig, Int] = allDeqFuCfgs.groupBy(x => x).map { case (cfg, cfgSeq) => (cfg, cfgSeq.length) } 91 val commonFuCfgs : Seq[FuConfig] = fuCfgsCnt.filter(_._2 > 1).keys.toSeq 92 val fuLatencyMaps : Seq[Map[FuType.OHType, Int]] = params.exuBlockParams.map(x => x.fuLatencyMap) 93 94 println(s"[IssueQueueImp] ${params.getIQName} fuLatencyMaps: ${fuLatencyMaps}") 95 println(s"[IssueQueueImp] ${params.getIQName} commonFuCfgs: ${commonFuCfgs.map(_.name)}") 96 lazy val io = IO(new IssueQueueIO()) 97 98 // Modules 99 val entries = Module(new Entries) 100 val fuBusyTableWrite = params.exuBlockParams.map { case x => OptionWrapper(x.latencyValMax > 0, Module(new FuBusyTableWrite(x.fuLatencyMap))) } 101 val fuBusyTableRead = params.exuBlockParams.map { case x => OptionWrapper(x.latencyValMax > 0, Module(new FuBusyTableRead(x.fuLatencyMap))) } 102 val intWbBusyTableWrite = params.exuBlockParams.map { case x => OptionWrapper(x.intLatencyCertain, Module(new FuBusyTableWrite(x.intFuLatencyMap))) } 103 val intWbBusyTableRead = params.exuBlockParams.map { case x => OptionWrapper(x.intLatencyCertain, Module(new FuBusyTableRead(x.intFuLatencyMap))) } 104 val vfWbBusyTableWrite = params.exuBlockParams.map { case x => OptionWrapper(x.vfLatencyCertain, Module(new FuBusyTableWrite(x.vfFuLatencyMap))) } 105 val vfWbBusyTableRead = params.exuBlockParams.map { case x => OptionWrapper(x.vfLatencyCertain, Module(new FuBusyTableRead(x.vfFuLatencyMap))) } 106 107 class WakeupQueueFlush extends Bundle { 108 val redirect = ValidIO(new Redirect) 109 val ldCancel = Vec(backendParams.LduCnt + backendParams.HyuCnt, new LoadCancelIO) 110 val og0Fail = Output(Bool()) 111 val og1Fail = Output(Bool()) 112 } 113 114 private def flushFunc(exuInput: ExuInput, flush: WakeupQueueFlush, stage: Int): Bool = { 115 val redirectFlush = exuInput.robIdx.needFlush(flush.redirect) 116 val loadDependencyFlush = LoadShouldCancel(exuInput.loadDependency, flush.ldCancel) 117 val ogFailFlush = stage match { 118 case 1 => flush.og0Fail 119 case 2 => flush.og1Fail 120 case _ => false.B 121 } 122 redirectFlush || loadDependencyFlush || ogFailFlush 123 } 124 125 private def modificationFunc(exuInput: ExuInput): ExuInput = { 126 val newExuInput = WireDefault(exuInput) 127 newExuInput.loadDependency match { 128 case Some(deps) => deps.zip(exuInput.loadDependency.get).foreach(x => x._1 := x._2 << 1) 129 case None => 130 } 131 newExuInput 132 } 133 134 private def lastConnectFunc(exuInput: ExuInput, newInput: ExuInput): ExuInput = { 135 val lastExuInput = WireDefault(exuInput) 136 val newExuInput = WireDefault(newInput) 137 newExuInput.elements.foreach { case (name, data) => 138 if (lastExuInput.elements.contains(name)) { 139 data := lastExuInput.elements(name) 140 } 141 } 142 if (newExuInput.pdestCopy.nonEmpty && !lastExuInput.pdestCopy.nonEmpty) { 143 newExuInput.pdestCopy.get.foreach(_ := lastExuInput.pdest) 144 } 145 if (newExuInput.rfWenCopy.nonEmpty && !lastExuInput.rfWenCopy.nonEmpty) { 146 newExuInput.rfWenCopy.get.foreach(_ := lastExuInput.rfWen.get) 147 } 148 if (newExuInput.fpWenCopy.nonEmpty && !lastExuInput.fpWenCopy.nonEmpty) { 149 newExuInput.fpWenCopy.get.foreach(_ := lastExuInput.fpWen.get) 150 } 151 if (newExuInput.vecWenCopy.nonEmpty && !lastExuInput.vecWenCopy.nonEmpty) { 152 newExuInput.vecWenCopy.get.foreach(_ := lastExuInput.rfWen.get) 153 } 154 if (newExuInput.loadDependencyCopy.nonEmpty && !lastExuInput.loadDependencyCopy.nonEmpty) { 155 newExuInput.loadDependencyCopy.get.foreach(_ := lastExuInput.loadDependency.get) 156 } 157 newExuInput 158 } 159 160 val wakeUpQueues: Seq[Option[MultiWakeupQueue[ExuInput, WakeupQueueFlush]]] = params.exuBlockParams.map { x => OptionWrapper(x.isIQWakeUpSource && !x.hasLoadExu, Module( 161 new MultiWakeupQueue(new ExuInput(x), new ExuInput(x, x.copyWakeupOut, x.copyNum), new WakeupQueueFlush, x.fuLatancySet, flushFunc, modificationFunc, lastConnectFunc) 162 ))} 163 val deqBeforeDly = Wire(params.genIssueDecoupledBundle) 164 165 val intWbBusyTableIn = io.wbBusyTableRead.map(_.intWbBusyTable) 166 val vfWbBusyTableIn = io.wbBusyTableRead.map(_.vfWbBusyTable) 167 val intWbBusyTableOut = io.wbBusyTableWrite.map(_.intWbBusyTable) 168 val vfWbBusyTableOut = io.wbBusyTableWrite.map(_.vfWbBusyTable) 169 val intDeqRespSetOut = io.wbBusyTableWrite.map(_.intDeqRespSet) 170 val vfDeqRespSetOut = io.wbBusyTableWrite.map(_.vfDeqRespSet) 171 val fuBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 172 val intWbBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 173 val vfWbBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 174 val s0_enqValidVec = io.enq.map(_.valid) 175 val s0_enqSelValidVec = Wire(Vec(params.numEnq, Bool())) 176 val s0_enqNotFlush = !io.flush.valid 177 val s0_enqBits = WireInit(VecInit(io.enq.map(_.bits))) 178 val s0_doEnqSelValidVec = s0_enqSelValidVec.map(_ && s0_enqNotFlush) //enqValid && notFlush && enqReady 179 180 181 val finalDeqSelValidVec = Wire(Vec(params.numDeq, Bool())) 182 val finalDeqSelOHVec = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 183 184 val validVec = VecInit(entries.io.valid.asBools) 185 val canIssueVec = VecInit(entries.io.canIssue.asBools) 186 dontTouch(canIssueVec) 187 val deqFirstIssueVec = entries.io.isFirstIssue 188 189 val dataSources: Vec[Vec[DataSource]] = entries.io.dataSources 190 val finalDataSources: Vec[Vec[DataSource]] = VecInit(finalDeqSelOHVec.map(oh => Mux1H(oh, dataSources))) 191 val loadDependency: Option[Vec[Vec[UInt]]] = entries.io.loadDependency 192 val finalLoadDependency: Option[IndexedSeq[Vec[UInt]]] = loadDependency.map(x => finalDeqSelOHVec.map(oh => Mux1H(oh, x))) 193 // (entryIdx)(srcIdx)(exuIdx) 194 val wakeUpL1ExuOH: Option[Vec[Vec[UInt]]] = entries.io.srcWakeUpL1ExuOH 195 val srcTimer: Option[Vec[Vec[UInt]]] = entries.io.srcTimer 196 197 // (deqIdx)(srcIdx)(exuIdx) 198 val finalWakeUpL1ExuOH: Option[Vec[Vec[UInt]]] = wakeUpL1ExuOH.map(x => VecInit(finalDeqSelOHVec.map(oh => Mux1H(oh, x)))) 199 val finalSrcTimer = srcTimer.map(x => VecInit(finalDeqSelOHVec.map(oh => Mux1H(oh, x)))) 200 201 val fuTypeVec = Wire(Vec(params.numEntries, FuType())) 202 val deqEntryVec = Wire(Vec(params.numDeq, ValidIO(new EntryBundle))) 203 val canIssueMergeAllBusy = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 204 val deqCanIssue = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 205 206 //deq 207 val enqEntryOldestSel = Wire(Vec(params.numDeq, ValidIO(UInt(params.numEnq.W)))) 208 val simpEntryOldestSel = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numDeq + params.numEnq, ValidIO(UInt(params.numSimp.W))))) 209 val compEntryOldestSel = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numDeq, ValidIO(UInt(params.numComp.W))))) 210 val othersEntryOldestSel = Wire(Vec(params.numDeq, ValidIO(UInt((params.numEntries - params.numEnq).W)))) 211 val deqSelValidVec = Wire(Vec(params.numDeq, Bool())) 212 val deqSelOHVec = Wire(Vec(params.numDeq, UInt(params.numEntries.W))) 213 val cancelDeqVec = Wire(Vec(params.numDeq, Bool())) 214 215 val subDeqSelValidVec = OptionWrapper(params.deqFuSame, Wire(Vec(params.numDeq, Bool()))) 216 val subDeqSelOHVec = OptionWrapper(params.deqFuSame, Wire(Vec(params.numDeq, UInt(params.numEntries.W)))) 217 val subDeqRequest = OptionWrapper(params.deqFuSame, Wire(UInt(params.numEntries.W))) 218 219 //trans 220 val simpEntryEnqSelVec = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numEnq, UInt(params.numSimp.W)))) 221 val compEntryEnqSelVec = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numEnq, UInt(params.numComp.W)))) 222 val othersEntryEnqSelVec = OptionWrapper(params.isAllComp || params.isAllSimp, Wire(Vec(params.numEnq, UInt((params.numEntries - params.numEnq).W)))) 223 val simpAgeDetectRequest = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numDeq + params.numEnq, UInt(params.numSimp.W)))) 224 simpAgeDetectRequest.foreach(_ := 0.U.asTypeOf(simpAgeDetectRequest.get)) 225 226 /** 227 * Connection of [[entries]] 228 */ 229 entries.io match { case entriesIO: EntriesIO => 230 entriesIO.flush := io.flush 231 entriesIO.enq.zipWithIndex.foreach { case (enq, enqIdx) => 232 enq.valid := s0_doEnqSelValidVec(enqIdx) 233 enq.bits.status.robIdx := s0_enqBits(enqIdx).robIdx 234 enq.bits.status.fuType := IQFuType.readFuType(VecInit(s0_enqBits(enqIdx).fuType.asBools), params.getFuCfgs.map(_.fuType)) 235 val numLsrc = s0_enqBits(enqIdx).srcType.size.min(enq.bits.status.srcStatus.map(_.srcType).size) 236 for(j <- 0 until numLsrc) { 237 enq.bits.status.srcStatus(j).psrc := s0_enqBits(enqIdx).psrc(j) 238 enq.bits.status.srcStatus(j).srcType := s0_enqBits(enqIdx).srcType(j) 239 enq.bits.status.srcStatus(j).srcState := s0_enqBits(enqIdx).srcState(j) & !LoadShouldCancel(Some(s0_enqBits(enqIdx).srcLoadDependency(j)), io.ldCancel) 240 enq.bits.status.srcStatus(j).dataSources.value := DataSource.reg 241 if(params.hasIQWakeUp) { 242 enq.bits.status.srcStatus(j).srcTimer.get := 0.U(3.W) 243 enq.bits.status.srcStatus(j).srcWakeUpL1ExuOH.get := 0.U.asTypeOf(ExuVec()) 244 enq.bits.status.srcStatus(j).srcLoadDependency.get := VecInit(s0_enqBits(enqIdx).srcLoadDependency(j).map(x => x(x.getWidth - 2, 0) << 1)) 245 } 246 } 247 enq.bits.status.blocked := false.B 248 enq.bits.status.issued := false.B 249 enq.bits.status.firstIssue := false.B 250 enq.bits.status.issueTimer := "b10".U 251 enq.bits.status.deqPortIdx := 0.U 252 if (params.isVecMemIQ) { 253 enq.bits.status.vecMem.get.uopIdx := s0_enqBits(enqIdx).uopIdx 254 } 255 if (params.inIntSchd && params.AluCnt > 0) { 256 // dirty code for lui+addi(w) fusion 257 val isLuiAddiFusion = s0_enqBits(enqIdx).isLUI32 258 val luiImm = Cat(s0_enqBits(enqIdx).lsrc(1), s0_enqBits(enqIdx).lsrc(0), s0_enqBits(enqIdx).imm(ImmUnion.maxLen - 1, 0)) 259 enq.bits.imm.foreach(_ := Mux(isLuiAddiFusion, ImmUnion.LUI32.toImm32(luiImm), s0_enqBits(enqIdx).imm)) 260 } 261 else if (params.inMemSchd && params.LduCnt > 0) { 262 // dirty code for fused_lui_load 263 val isLuiLoadFusion = SrcType.isNotReg(s0_enqBits(enqIdx).srcType(0)) && FuType.isLoad(s0_enqBits(enqIdx).fuType) 264 enq.bits.imm.foreach(_ := Mux(isLuiLoadFusion, Imm_LUI_LOAD().getLuiImm(s0_enqBits(enqIdx)), s0_enqBits(enqIdx).imm)) 265 } 266 else { 267 enq.bits.imm.foreach(_ := s0_enqBits(enqIdx).imm) 268 } 269 enq.bits.payload := s0_enqBits(enqIdx) 270 } 271 entriesIO.og0Resp.zipWithIndex.foreach { case (og0Resp, i) => 272 og0Resp.valid := io.og0Resp(i).valid 273 og0Resp.bits.robIdx := io.og0Resp(i).bits.robIdx 274 og0Resp.bits.uopIdx.foreach(_ := io.og0Resp(i).bits.uopIdx.get) 275 og0Resp.bits.dataInvalidSqIdx := io.og0Resp(i).bits.dataInvalidSqIdx 276 og0Resp.bits.respType := io.og0Resp(i).bits.respType 277 og0Resp.bits.rfWen := io.og0Resp(i).bits.rfWen 278 og0Resp.bits.fuType := io.og0Resp(i).bits.fuType 279 } 280 entriesIO.og1Resp.zipWithIndex.foreach { case (og1Resp, i) => 281 og1Resp.valid := io.og1Resp(i).valid 282 og1Resp.bits.robIdx := io.og1Resp(i).bits.robIdx 283 og1Resp.bits.uopIdx.foreach(_ := io.og1Resp(i).bits.uopIdx.get) 284 og1Resp.bits.dataInvalidSqIdx := io.og1Resp(i).bits.dataInvalidSqIdx 285 og1Resp.bits.respType := io.og1Resp(i).bits.respType 286 og1Resp.bits.rfWen := io.og1Resp(i).bits.rfWen 287 og1Resp.bits.fuType := io.og1Resp(i).bits.fuType 288 } 289 entriesIO.finalIssueResp.foreach(_.zipWithIndex.foreach { case (finalIssueResp, i) => 290 finalIssueResp := io.finalIssueResp.get(i) 291 }) 292 for(deqIdx <- 0 until params.numDeq) { 293 entriesIO.deqReady(deqIdx) := deqBeforeDly(deqIdx).ready 294 entriesIO.deqSelOH(deqIdx).valid := deqSelValidVec(deqIdx) 295 entriesIO.deqSelOH(deqIdx).bits := deqSelOHVec(deqIdx) 296 entriesIO.enqEntryOldestSel(deqIdx) := enqEntryOldestSel(deqIdx) 297 entriesIO.simpEntryOldestSel.foreach(_(deqIdx) := simpEntryOldestSel.get(deqIdx)) 298 entriesIO.compEntryOldestSel.foreach(_(deqIdx) := compEntryOldestSel.get(deqIdx)) 299 entriesIO.othersEntryOldestSel.foreach(_(deqIdx) := othersEntryOldestSel(deqIdx)) 300 entriesIO.subDeqRequest.foreach(_(deqIdx) := subDeqRequest.get) 301 entriesIO.subDeqSelOH.foreach(_(deqIdx) := subDeqSelOHVec.get(deqIdx)) 302 } 303 entriesIO.wakeUpFromWB := io.wakeupFromWB 304 entriesIO.wakeUpFromIQ := io.wakeupFromIQ 305 entriesIO.og0Cancel := io.og0Cancel 306 entriesIO.og1Cancel := io.og1Cancel 307 entriesIO.ldCancel := io.ldCancel 308 entriesIO.simpEntryDeqSelVec.foreach(_ := VecInit(simpEntryOldestSel.get.takeRight(params.numEnq).map(_.bits))) 309 //output 310 fuTypeVec := entriesIO.fuType 311 deqEntryVec := entriesIO.deqEntry 312 cancelDeqVec := entriesIO.cancelDeqVec 313 simpEntryEnqSelVec.foreach(_ := entriesIO.simpEntryEnqSelVec.get) 314 compEntryEnqSelVec.foreach(_ := entriesIO.compEntryEnqSelVec.get) 315 othersEntryEnqSelVec.foreach(_ := entriesIO.othersEntryEnqSelVec.get) 316 } 317 318 319 s0_enqSelValidVec := s0_enqValidVec.zip(io.enq).map{ case (enqValid, enq) => enqValid && enq.ready} 320 321 protected val commonAccept: UInt = Cat(fuTypeVec.map(fuType => 322 FuType.FuTypeOrR(fuType, commonFuCfgs.map(_.fuType)) 323 ).reverse) 324 325 // if deq port can accept the uop 326 protected val canAcceptVec: Seq[UInt] = deqFuCfgs.map { fuCfgs: Seq[FuConfig] => 327 Cat(fuTypeVec.map(fuType => 328 FuType.FuTypeOrR(fuType, fuCfgs.map(_.fuType)) 329 ).reverse) 330 } 331 332 protected val deqCanAcceptVec: Seq[IndexedSeq[Bool]] = deqFuCfgs.map { fuCfgs: Seq[FuConfig] => 333 fuTypeVec.map(fuType => 334 FuType.FuTypeOrR(fuType, fuCfgs.map(_.fuType))) 335 } 336 337 canIssueMergeAllBusy.zipWithIndex.foreach { case (merge, i) => 338 val mergeFuBusy = { 339 if (fuBusyTableWrite(i).nonEmpty) canIssueVec.asUInt & (~fuBusyTableMask(i)) 340 else canIssueVec.asUInt 341 } 342 val mergeIntWbBusy = { 343 if (intWbBusyTableRead(i).nonEmpty) mergeFuBusy & (~intWbBusyTableMask(i)) 344 else mergeFuBusy 345 } 346 val mergeVfWbBusy = { 347 if (vfWbBusyTableRead(i).nonEmpty) mergeIntWbBusy & (~vfWbBusyTableMask(i)) 348 else mergeIntWbBusy 349 } 350 merge := mergeVfWbBusy 351 } 352 353 deqCanIssue.zipWithIndex.foreach { case (req, i) => 354 req := canIssueMergeAllBusy(i) & VecInit(deqCanAcceptVec(i)).asUInt 355 } 356 dontTouch(fuTypeVec) 357 dontTouch(canIssueMergeAllBusy) 358 dontTouch(deqCanIssue) 359 360 if (params.numDeq == 2) { 361 require(params.deqFuSame || params.deqFuDiff, "The 2 deq ports need to be identical or completely different") 362 } 363 364 if (params.numDeq == 2 && params.deqFuSame) { 365 val subDeqPolicy = Module(new DeqPolicy()) 366 367 enqEntryOldestSel := DontCare 368 369 if (params.isAllComp || params.isAllSimp) { 370 othersEntryOldestSel(0) := AgeDetector(numEntries = params.numEntries - params.numEnq, 371 enq = othersEntryEnqSelVec.get, 372 canIssue = canIssueVec.asUInt(params.numEntries-1, params.numEnq) 373 ) 374 othersEntryOldestSel(1) := DontCare 375 376 subDeqPolicy.io.request := subDeqRequest.get 377 subDeqSelValidVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => oh.valid) 378 subDeqSelOHVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => oh.bits) 379 } 380 else { 381 simpAgeDetectRequest.get(0) := canIssueVec.asUInt(params.numEnq + params.numSimp - 1, params.numEnq) 382 simpAgeDetectRequest.get(1) := DontCare 383 simpAgeDetectRequest.get(params.numDeq) := VecInit(validVec.drop(params.numEnq).take(params.numSimp)).asUInt 384 if (params.numEnq == 2) { 385 simpAgeDetectRequest.get(params.numDeq + 1) := VecInit(validVec.drop(params.numEnq).take(params.numSimp)).asUInt & ~simpEntryOldestSel.get(params.numDeq).bits 386 } 387 388 simpEntryOldestSel.get := AgeDetector(numEntries = params.numSimp, 389 enq = simpEntryEnqSelVec.get, 390 canIssue = simpAgeDetectRequest.get 391 ) 392 393 compEntryOldestSel.get(0) := AgeDetector(numEntries = params.numComp, 394 enq = compEntryEnqSelVec.get, 395 canIssue = canIssueVec.asUInt(params.numEntries - 1, params.numEnq + params.numSimp) 396 ) 397 compEntryOldestSel.get(1) := DontCare 398 399 othersEntryOldestSel(0).valid := compEntryOldestSel.get(0).valid || simpEntryOldestSel.get(0).valid 400 othersEntryOldestSel(0).bits := Cat( 401 compEntryOldestSel.get(0).bits, 402 Fill(params.numSimp, !compEntryOldestSel.get(0).valid) & simpEntryOldestSel.get(0).bits, 403 ) 404 othersEntryOldestSel(1) := DontCare 405 406 subDeqPolicy.io.request := Reverse(subDeqRequest.get) 407 subDeqSelValidVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => oh.valid) 408 subDeqSelOHVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => Reverse(oh.bits)) 409 } 410 411 subDeqRequest.get := canIssueVec.asUInt & ~Cat(othersEntryOldestSel(0).bits, 0.U((params.numEnq).W)) 412 413 deqSelValidVec(0) := othersEntryOldestSel(0).valid || subDeqSelValidVec.get(1) 414 deqSelValidVec(1) := subDeqSelValidVec.get(0) 415 deqSelOHVec(0) := Mux(othersEntryOldestSel(0).valid, 416 Cat(othersEntryOldestSel(0).bits, 0.U((params.numEnq).W)), 417 subDeqSelOHVec.get(1)) & canIssueMergeAllBusy(0) 418 deqSelOHVec(1) := subDeqSelOHVec.get(0) & canIssueMergeAllBusy(1) 419 420 finalDeqSelValidVec.zip(finalDeqSelOHVec).zip(deqSelValidVec).zip(deqSelOHVec).zipWithIndex.foreach { case ((((selValid, selOH), deqValid), deqOH), i) => 421 selValid := deqValid && deqOH.orR && deqBeforeDly(i).ready 422 selOH := deqOH 423 } 424 } 425 else { 426 enqEntryOldestSel := NewAgeDetector(numEntries = params.numEnq, 427 enq = VecInit(s0_doEnqSelValidVec), 428 canIssue = VecInit(deqCanIssue.map(_(params.numEnq - 1, 0))) 429 ) 430 431 if (params.isAllComp || params.isAllSimp) { 432 othersEntryOldestSel := AgeDetector(numEntries = params.numEntries - params.numEnq, 433 enq = othersEntryEnqSelVec.get, 434 canIssue = VecInit(deqCanIssue.map(_(params.numEntries - 1, params.numEnq))) 435 ) 436 437 deqSelValidVec.zip(deqSelOHVec).zipWithIndex.foreach { case ((selValid, selOH), i) => 438 if (params.exuBlockParams(i).fuConfigs.contains(FuConfig.FakeHystaCfg)) { 439 selValid := false.B 440 selOH := 0.U.asTypeOf(selOH) 441 } else { 442 selValid := othersEntryOldestSel(i).valid || enqEntryOldestSel(i).valid 443 selOH := Cat(othersEntryOldestSel(i).bits, Fill(params.numEnq, !othersEntryOldestSel(i).valid) & enqEntryOldestSel(i).bits) 444 } 445 } 446 } 447 else { 448 othersEntryOldestSel := DontCare 449 450 deqCanIssue.zipWithIndex.foreach { case (req, i) => 451 simpAgeDetectRequest.get(i) := req(params.numEnq + params.numSimp - 1, params.numEnq) 452 } 453 simpAgeDetectRequest.get(params.numDeq) := VecInit(validVec.drop(params.numEnq).take(params.numSimp)).asUInt 454 if (params.numEnq == 2) { 455 simpAgeDetectRequest.get(params.numDeq + 1) := VecInit(validVec.drop(params.numEnq).take(params.numSimp)).asUInt & ~simpEntryOldestSel.get(params.numDeq).bits 456 } 457 458 simpEntryOldestSel.get := AgeDetector(numEntries = params.numSimp, 459 enq = simpEntryEnqSelVec.get, 460 canIssue = simpAgeDetectRequest.get 461 ) 462 463 compEntryOldestSel.get := AgeDetector(numEntries = params.numComp, 464 enq = compEntryEnqSelVec.get, 465 canIssue = VecInit(deqCanIssue.map(_(params.numEntries - 1, params.numEnq + params.numSimp))) 466 ) 467 468 deqSelValidVec.zip(deqSelOHVec).zipWithIndex.foreach { case ((selValid, selOH), i) => 469 selValid := compEntryOldestSel.get(i).valid || simpEntryOldestSel.get(i).valid || enqEntryOldestSel(i).valid 470 selOH := Cat( 471 compEntryOldestSel.get(i).bits, 472 Fill(params.numSimp, !compEntryOldestSel.get(i).valid) & simpEntryOldestSel.get(i).bits, 473 Fill(params.numEnq, !compEntryOldestSel.get(i).valid && !simpEntryOldestSel.get(i).valid) & enqEntryOldestSel(i).bits 474 ) 475 } 476 } 477 478 finalDeqSelValidVec.zip(finalDeqSelOHVec).zip(deqSelValidVec).zip(deqSelOHVec).zipWithIndex.foreach { case ((((selValid, selOH), deqValid), deqOH), i) => 479 selValid := deqValid && deqBeforeDly(i).ready 480 selOH := deqOH 481 } 482 } 483 484 val toBusyTableDeqResp = Wire(Vec(params.numDeq, ValidIO(new IssueQueueDeqRespBundle))) 485 486 toBusyTableDeqResp.zipWithIndex.foreach { case (deqResp, i) => 487 deqResp.valid := finalDeqSelValidVec(i) 488 deqResp.bits.respType := RSFeedbackType.issueSuccess 489 deqResp.bits.robIdx := DontCare 490 deqResp.bits.dataInvalidSqIdx := DontCare 491 deqResp.bits.rfWen := DontCare 492 deqResp.bits.fuType := deqBeforeDly(i).bits.common.fuType 493 deqResp.bits.uopIdx.foreach(_ := DontCare) 494 } 495 496 //fuBusyTable 497 fuBusyTableWrite.zip(fuBusyTableRead).zipWithIndex.foreach { case ((busyTableWrite: Option[FuBusyTableWrite], busyTableRead: Option[FuBusyTableRead]), i) => 498 if(busyTableWrite.nonEmpty) { 499 val btwr = busyTableWrite.get 500 val btrd = busyTableRead.get 501 btwr.io.in.deqResp := toBusyTableDeqResp(i) 502 btwr.io.in.og0Resp := io.og0Resp(i) 503 btwr.io.in.og1Resp := io.og1Resp(i) 504 btrd.io.in.fuBusyTable := btwr.io.out.fuBusyTable 505 btrd.io.in.fuTypeRegVec := fuTypeVec 506 fuBusyTableMask(i) := btrd.io.out.fuBusyTableMask 507 } 508 else { 509 fuBusyTableMask(i) := 0.U(params.numEntries.W) 510 } 511 } 512 513 //wbfuBusyTable write 514 intWbBusyTableWrite.zip(intWbBusyTableOut).zip(intDeqRespSetOut).zipWithIndex.foreach { case (((busyTableWrite: Option[FuBusyTableWrite], busyTable: Option[UInt]), deqResp), i) => 515 if(busyTableWrite.nonEmpty) { 516 val btwr = busyTableWrite.get 517 val bt = busyTable.get 518 val dq = deqResp.get 519 btwr.io.in.deqResp := toBusyTableDeqResp(i) 520 btwr.io.in.og0Resp := io.og0Resp(i) 521 btwr.io.in.og1Resp := io.og1Resp(i) 522 bt := btwr.io.out.fuBusyTable 523 dq := btwr.io.out.deqRespSet 524 } 525 } 526 527 vfWbBusyTableWrite.zip(vfWbBusyTableOut).zip(vfDeqRespSetOut).zipWithIndex.foreach { case (((busyTableWrite: Option[FuBusyTableWrite], busyTable: Option[UInt]), deqResp), i) => 528 if (busyTableWrite.nonEmpty) { 529 val btwr = busyTableWrite.get 530 val bt = busyTable.get 531 val dq = deqResp.get 532 btwr.io.in.deqResp := toBusyTableDeqResp(i) 533 btwr.io.in.og0Resp := io.og0Resp(i) 534 btwr.io.in.og1Resp := io.og1Resp(i) 535 bt := btwr.io.out.fuBusyTable 536 dq := btwr.io.out.deqRespSet 537 } 538 } 539 540 //wbfuBusyTable read 541 intWbBusyTableRead.zip(intWbBusyTableIn).zipWithIndex.foreach { case ((busyTableRead: Option[FuBusyTableRead], busyTable: Option[UInt]), i) => 542 if(busyTableRead.nonEmpty) { 543 val btrd = busyTableRead.get 544 val bt = busyTable.get 545 btrd.io.in.fuBusyTable := bt 546 btrd.io.in.fuTypeRegVec := fuTypeVec 547 intWbBusyTableMask(i) := btrd.io.out.fuBusyTableMask 548 } 549 else { 550 intWbBusyTableMask(i) := 0.U(params.numEntries.W) 551 } 552 } 553 vfWbBusyTableRead.zip(vfWbBusyTableIn).zipWithIndex.foreach { case ((busyTableRead: Option[FuBusyTableRead], busyTable: Option[UInt]), i) => 554 if (busyTableRead.nonEmpty) { 555 val btrd = busyTableRead.get 556 val bt = busyTable.get 557 btrd.io.in.fuBusyTable := bt 558 btrd.io.in.fuTypeRegVec := fuTypeVec 559 vfWbBusyTableMask(i) := btrd.io.out.fuBusyTableMask 560 } 561 else { 562 vfWbBusyTableMask(i) := 0.U(params.numEntries.W) 563 } 564 } 565 566 wakeUpQueues.zipWithIndex.foreach { case (wakeUpQueueOption, i) => 567 wakeUpQueueOption.foreach { 568 wakeUpQueue => 569 val flush = Wire(new WakeupQueueFlush) 570 flush.redirect := io.flush 571 flush.ldCancel := io.ldCancel 572 flush.og0Fail := io.og0Resp(i).valid && RSFeedbackType.isBlocked(io.og0Resp(i).bits.respType) 573 flush.og1Fail := io.og1Resp(i).valid && RSFeedbackType.isBlocked(io.og1Resp(i).bits.respType) 574 wakeUpQueue.io.flush := flush 575 wakeUpQueue.io.enq.valid := deqBeforeDly(i).valid 576 wakeUpQueue.io.enq.bits.uop :<= deqBeforeDly(i).bits.common 577 wakeUpQueue.io.enq.bits.uop.pdestCopy.foreach(_ := 0.U) 578 wakeUpQueue.io.enq.bits.lat := getDeqLat(i, deqBeforeDly(i).bits.common.fuType) 579 } 580 } 581 582 deqBeforeDly.zipWithIndex.foreach { case (deq, i) => 583 deq.valid := finalDeqSelValidVec(i) && !cancelDeqVec(i) 584 deq.bits.addrOH := finalDeqSelOHVec(i) 585 deq.bits.common.isFirstIssue := deqFirstIssueVec(i) 586 deq.bits.common.iqIdx := OHToUInt(finalDeqSelOHVec(i)) 587 deq.bits.common.fuType := IQFuType.readFuType(deqEntryVec(i).bits.status.fuType, params.getFuCfgs.map(_.fuType)).asUInt 588 deq.bits.common.fuOpType := deqEntryVec(i).bits.payload.fuOpType 589 deq.bits.common.rfWen.foreach(_ := deqEntryVec(i).bits.payload.rfWen) 590 deq.bits.common.fpWen.foreach(_ := deqEntryVec(i).bits.payload.fpWen) 591 deq.bits.common.vecWen.foreach(_ := deqEntryVec(i).bits.payload.vecWen) 592 deq.bits.common.flushPipe.foreach(_ := deqEntryVec(i).bits.payload.flushPipe) 593 deq.bits.common.pdest := deqEntryVec(i).bits.payload.pdest 594 deq.bits.common.robIdx := deqEntryVec(i).bits.status.robIdx 595 596 require(deq.bits.common.dataSources.size <= finalDataSources(i).size) 597 deq.bits.common.dataSources.zip(finalDataSources(i)).foreach { case (sink, source) => sink := source} 598 deq.bits.common.l1ExuOH.foreach(_ := finalWakeUpL1ExuOH.get(i)) 599 deq.bits.common.srcTimer.foreach(_ := finalSrcTimer.get(i)) 600 deq.bits.common.loadDependency.foreach(_ := finalLoadDependency.get(i)) 601 deq.bits.common.src := DontCare 602 deq.bits.common.preDecode.foreach(_ := deqEntryVec(i).bits.payload.preDecodeInfo) 603 604 deq.bits.rf.zip(deqEntryVec(i).bits.status.srcStatus.map(_.psrc)).zip(deqEntryVec(i).bits.status.srcStatus.map(_.srcType)).foreach { case ((rf, psrc), srcType) => 605 // psrc in status array can be pregIdx of IntRegFile or VfRegFile 606 rf.foreach(_.addr := psrc) 607 rf.foreach(_.srcType := srcType) 608 } 609 deq.bits.srcType.zip(deqEntryVec(i).bits.status.srcStatus.map(_.srcType)).foreach { case (sink, source) => 610 sink := source 611 } 612 deq.bits.immType := deqEntryVec(i).bits.payload.selImm 613 deq.bits.common.imm := deqEntryVec(i).bits.imm.getOrElse(0.U) 614 615 deq.bits.common.perfDebugInfo := deqEntryVec(i).bits.payload.debugInfo 616 deq.bits.common.perfDebugInfo.selectTime := GTimer() 617 deq.bits.common.perfDebugInfo.issueTime := GTimer() + 1.U 618 } 619 620 private val deqShift = WireDefault(deqBeforeDly) 621 deqShift.zip(deqBeforeDly).foreach { 622 case (shifted, original) => 623 original.ready := shifted.ready // this will not cause combinational loop 624 shifted.bits.common.loadDependency.foreach( 625 _ := original.bits.common.loadDependency.get.map(_ << 1) 626 ) 627 } 628 io.deqDelay.zip(deqShift).foreach { case (deqDly, deq) => 629 NewPipelineConnect( 630 deq, deqDly, deqDly.valid, 631 false.B, 632 Option("Scheduler2DataPathPipe") 633 ) 634 } 635 if(backendParams.debugEn) { 636 dontTouch(io.deqDelay) 637 } 638 io.wakeupToIQ.zipWithIndex.foreach { case (wakeup, i) => 639 if (wakeUpQueues(i).nonEmpty && finalWakeUpL1ExuOH.nonEmpty) { 640 wakeup.valid := wakeUpQueues(i).get.io.deq.valid 641 wakeup.bits.fromExuInput(wakeUpQueues(i).get.io.deq.bits, finalWakeUpL1ExuOH.get(i)) 642 wakeup.bits.loadDependency := wakeUpQueues(i).get.io.deq.bits.loadDependency.getOrElse(0.U.asTypeOf(wakeup.bits.loadDependency)) 643 wakeup.bits.is0Lat := getDeqLat(i, wakeUpQueues(i).get.io.deq.bits.fuType) === 0.U 644 } else if (wakeUpQueues(i).nonEmpty) { 645 wakeup.valid := wakeUpQueues(i).get.io.deq.valid 646 wakeup.bits.fromExuInput(wakeUpQueues(i).get.io.deq.bits) 647 wakeup.bits.loadDependency := wakeUpQueues(i).get.io.deq.bits.loadDependency.getOrElse(0.U.asTypeOf(wakeup.bits.loadDependency)) 648 wakeup.bits.is0Lat := getDeqLat(i, wakeUpQueues(i).get.io.deq.bits.fuType) === 0.U 649 } else { 650 wakeup.valid := false.B 651 wakeup.bits := 0.U.asTypeOf(wakeup.bits) 652 wakeup.bits.is0Lat := 0.U 653 } 654 if (wakeUpQueues(i).nonEmpty) { 655 wakeup.bits.rfWen := (if (wakeUpQueues(i).get.io.deq.bits.rfWen .nonEmpty) wakeUpQueues(i).get.io.deq.valid && wakeUpQueues(i).get.io.deq.bits.rfWen .get else false.B) 656 wakeup.bits.fpWen := (if (wakeUpQueues(i).get.io.deq.bits.fpWen .nonEmpty) wakeUpQueues(i).get.io.deq.valid && wakeUpQueues(i).get.io.deq.bits.fpWen .get else false.B) 657 wakeup.bits.vecWen := (if (wakeUpQueues(i).get.io.deq.bits.vecWen.nonEmpty) wakeUpQueues(i).get.io.deq.valid && wakeUpQueues(i).get.io.deq.bits.vecWen.get else false.B) 658 } 659 660 if(wakeUpQueues(i).nonEmpty && wakeup.bits.pdestCopy.nonEmpty){ 661 wakeup.bits.pdestCopy.get := wakeUpQueues(i).get.io.deq.bits.pdestCopy.get 662 } 663 if (wakeUpQueues(i).nonEmpty && wakeup.bits.rfWenCopy.nonEmpty) { 664 wakeup.bits.rfWenCopy.get := wakeUpQueues(i).get.io.deq.bits.rfWenCopy.get 665 } 666 if (wakeUpQueues(i).nonEmpty && wakeup.bits.fpWenCopy.nonEmpty) { 667 wakeup.bits.fpWenCopy.get := wakeUpQueues(i).get.io.deq.bits.fpWenCopy.get 668 } 669 if (wakeUpQueues(i).nonEmpty && wakeup.bits.vecWenCopy.nonEmpty) { 670 wakeup.bits.vecWenCopy.get := wakeUpQueues(i).get.io.deq.bits.vecWenCopy.get 671 } 672 if (wakeUpQueues(i).nonEmpty && wakeup.bits.loadDependencyCopy.nonEmpty) { 673 wakeup.bits.loadDependencyCopy.get := wakeUpQueues(i).get.io.deq.bits.loadDependencyCopy.get 674 } 675 } 676 677 // Todo: better counter implementation 678 private val enqHasValid = validVec.take(params.numEnq).reduce(_ | _) 679 private val enqEntryValidCnt = PopCount(validVec.take(params.numEnq)) 680 private val othersValidCnt = PopCount(validVec.drop(params.numEnq)) 681 io.status.leftVec(0) := validVec.drop(params.numEnq).reduce(_ & _) 682 for (i <- 0 until params.numEnq) { 683 io.status.leftVec(i + 1) := othersValidCnt === (params.numEntries - params.numEnq - (i + 1)).U 684 } 685 private val othersLeftOneCaseVec = Wire(Vec(params.numEntries - params.numEnq, UInt((params.numEntries - params.numEnq).W))) 686 othersLeftOneCaseVec.zipWithIndex.foreach { case (leftone, i) => 687 leftone := ~(1.U((params.numEntries - params.numEnq).W) << i) 688 } 689 private val othersLeftOne = othersLeftOneCaseVec.map(_ === VecInit(validVec.drop(params.numEnq)).asUInt).reduce(_ | _) 690 private val othersCanotIn = othersLeftOne || validVec.drop(params.numEnq).reduce(_ & _) 691 692 io.enq.foreach(_.ready := !othersCanotIn || !enqHasValid) 693 io.status.empty := !Cat(validVec).orR 694 io.status.full := othersCanotIn 695 io.status.validCnt := PopCount(validVec) 696 697 protected def getDeqLat(deqPortIdx: Int, fuType: UInt) : UInt = { 698 Mux1H(fuLatencyMaps(deqPortIdx) map { case (k, v) => (fuType(k.id), v.U) }) 699 } 700 701 // issue perf counter 702 // enq count 703 XSPerfAccumulate("enq_valid_cnt", PopCount(io.enq.map(_.fire))) 704 XSPerfAccumulate("enq_fire_cnt", PopCount(io.enq.map(_.fire))) 705 // valid count 706 XSPerfHistogram("enq_entry_valid_cnt", enqEntryValidCnt, true.B, 0, params.numEnq + 1) 707 XSPerfHistogram("other_entry_valid_cnt", othersValidCnt, true.B, 0, params.numEntries - params.numEnq + 1) 708 XSPerfHistogram("valid_cnt", PopCount(validVec), true.B, 0, params.numEntries + 1) 709 // only split when more than 1 func type 710 if (params.getFuCfgs.size > 0) { 711 for (t <- FuType.functionNameMap.keys) { 712 val fuName = FuType.functionNameMap(t) 713 if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _)) { 714 XSPerfHistogram(s"valid_cnt_hist_futype_${fuName}", PopCount(validVec.zip(fuTypeVec).map { case (v, fu) => v && fu === t.U }), true.B, 0, params.numEntries, 1) 715 } 716 } 717 } 718 // ready instr count 719 private val readyEntriesCnt = PopCount(validVec.zip(canIssueVec).map(x => x._1 && x._2)) 720 XSPerfHistogram("ready_cnt", readyEntriesCnt, true.B, 0, params.numEntries + 1) 721 // only split when more than 1 func type 722 if (params.getFuCfgs.size > 0) { 723 for (t <- FuType.functionNameMap.keys) { 724 val fuName = FuType.functionNameMap(t) 725 if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _)) { 726 XSPerfHistogram(s"ready_cnt_hist_futype_${fuName}", PopCount(validVec.zip(canIssueVec).zip(fuTypeVec).map { case ((v, c), fu) => v && c && fu === t.U }), true.B, 0, params.numEntries, 1) 727 } 728 } 729 } 730 731 // deq instr count 732 XSPerfAccumulate("issue_instr_pre_count", PopCount(deqBeforeDly.map(_.valid))) 733 XSPerfHistogram("issue_instr_pre_count_hist", PopCount(deqBeforeDly.map(_.valid)), true.B, 0, params.numDeq + 1, 1) 734 XSPerfAccumulate("issue_instr_count", PopCount(io.deqDelay.map(_.valid))) 735 XSPerfHistogram("issue_instr_count_hist", PopCount(io.deqDelay.map(_.valid)), true.B, 0, params.numDeq + 1, 1) 736 737 // deq instr data source count 738 XSPerfAccumulate("issue_datasource_reg", deqBeforeDly.map{ deq => 739 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) }) 740 }.reduce(_ +& _)) 741 XSPerfAccumulate("issue_datasource_bypass", deqBeforeDly.map{ deq => 742 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) }) 743 }.reduce(_ +& _)) 744 XSPerfAccumulate("issue_datasource_forward", deqBeforeDly.map{ deq => 745 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) }) 746 }.reduce(_ +& _)) 747 XSPerfAccumulate("issue_datasource_noreg", deqBeforeDly.map{ deq => 748 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) }) 749 }.reduce(_ +& _)) 750 751 XSPerfHistogram("issue_datasource_reg_hist", deqBeforeDly.map{ deq => 752 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) }) 753 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 754 XSPerfHistogram("issue_datasource_bypass_hist", deqBeforeDly.map{ deq => 755 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) }) 756 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 757 XSPerfHistogram("issue_datasource_forward_hist", deqBeforeDly.map{ deq => 758 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) }) 759 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 760 XSPerfHistogram("issue_datasource_noreg_hist", deqBeforeDly.map{ deq => 761 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) }) 762 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 763 764 // deq instr data source count for each futype 765 for (t <- FuType.functionNameMap.keys) { 766 val fuName = FuType.functionNameMap(t) 767 if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _)) { 768 XSPerfAccumulate(s"issue_datasource_reg_futype_${fuName}", deqBeforeDly.map{ deq => 769 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 770 }.reduce(_ +& _)) 771 XSPerfAccumulate(s"issue_datasource_bypass_futype_${fuName}", deqBeforeDly.map{ deq => 772 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 773 }.reduce(_ +& _)) 774 XSPerfAccumulate(s"issue_datasource_forward_futype_${fuName}", deqBeforeDly.map{ deq => 775 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 776 }.reduce(_ +& _)) 777 XSPerfAccumulate(s"issue_datasource_noreg_futype_${fuName}", deqBeforeDly.map{ deq => 778 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 779 }.reduce(_ +& _)) 780 781 XSPerfHistogram(s"issue_datasource_reg_hist_futype_${fuName}", deqBeforeDly.map{ deq => 782 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 783 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 784 XSPerfHistogram(s"issue_datasource_bypass_hist_futype_${fuName}", deqBeforeDly.map{ deq => 785 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 786 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 787 XSPerfHistogram(s"issue_datasource_forward_hist_futype_${fuName}", deqBeforeDly.map{ deq => 788 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 789 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 790 XSPerfHistogram(s"issue_datasource_noreg_hist_futype_${fuName}", deqBeforeDly.map{ deq => 791 PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U }) 792 }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1) 793 } 794 } 795 796 // cancel instr count 797 if (params.hasIQWakeUp) { 798 val cancelVec: Vec[Bool] = entries.io.cancel.get 799 XSPerfAccumulate("cancel_instr_count", PopCount(validVec.zip(cancelVec).map(x => x._1 & x._2))) 800 XSPerfHistogram("cancel_instr_hist", PopCount(validVec.zip(cancelVec).map(x => x._1 & x._2)), true.B, 0, params.numEntries, 1) 801 for (t <- FuType.functionNameMap.keys) { 802 val fuName = FuType.functionNameMap(t) 803 if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _)) { 804 XSPerfAccumulate(s"cancel_instr_count_futype_${fuName}", PopCount(validVec.zip(cancelVec).zip(fuTypeVec).map{ case ((x, y), fu) => x & y & fu === t.U })) 805 XSPerfHistogram(s"cancel_instr_hist_futype_${fuName}", PopCount(validVec.zip(cancelVec).zip(fuTypeVec).map{ case ((x, y), fu) => x & y & fu === t.U }), true.B, 0, params.numEntries, 1) 806 } 807 } 808 } 809} 810 811class IssueQueueJumpBundle extends Bundle { 812 val pc = UInt(VAddrData().dataWidth.W) 813} 814 815class IssueQueueLoadBundle(implicit p: Parameters) extends XSBundle { 816 val fastMatch = UInt(backendParams.LduCnt.W) 817 val fastImm = UInt(12.W) 818} 819 820class IssueQueueIntIO()(implicit p: Parameters, params: IssueBlockParams) extends IssueQueueIO 821 822class IssueQueueIntImp(override val wrapper: IssueQueue)(implicit p: Parameters, iqParams: IssueBlockParams) 823 extends IssueQueueImp(wrapper) 824{ 825 io.suggestName("none") 826 override lazy val io = IO(new IssueQueueIntIO).suggestName("io") 827 828 deqBeforeDly.zipWithIndex.foreach{ case (deq, i) => { 829 deq.bits.common.pc.foreach(_ := deqEntryVec(i).bits.payload.pc) 830 deq.bits.common.preDecode.foreach(_ := deqEntryVec(i).bits.payload.preDecodeInfo) 831 deq.bits.common.ftqIdx.foreach(_ := deqEntryVec(i).bits.payload.ftqPtr) 832 deq.bits.common.ftqOffset.foreach(_ := deqEntryVec(i).bits.payload.ftqOffset) 833 deq.bits.common.predictInfo.foreach(x => { 834 x.target := DontCare 835 x.taken := deqEntryVec(i).bits.payload.pred_taken 836 }) 837 // for std 838 deq.bits.common.sqIdx.foreach(_ := deqEntryVec(i).bits.payload.sqIdx) 839 // for i2f 840 deq.bits.common.fpu.foreach(_ := deqEntryVec(i).bits.payload.fpu) 841 }} 842} 843 844class IssueQueueVfImp(override val wrapper: IssueQueue)(implicit p: Parameters, iqParams: IssueBlockParams) 845 extends IssueQueueImp(wrapper) 846{ 847 s0_enqBits.foreach{ x => 848 x.srcType(3) := SrcType.vp // v0: mask src 849 x.srcType(4) := SrcType.vp // vl&vtype 850 } 851 deqBeforeDly.zipWithIndex.foreach{ case (deq, i) => { 852 deq.bits.common.fpu.foreach(_ := deqEntryVec(i).bits.payload.fpu) 853 deq.bits.common.vpu.foreach(_ := deqEntryVec(i).bits.payload.vpu) 854 deq.bits.common.vpu.foreach(_.vuopIdx := deqEntryVec(i).bits.payload.uopIdx) 855 deq.bits.common.vpu.foreach(_.lastUop := deqEntryVec(i).bits.payload.lastUop) 856 }} 857} 858 859class IssueQueueMemBundle(implicit p: Parameters, params: IssueBlockParams) extends Bundle { 860 val feedbackIO = Flipped(Vec(params.numDeq, new MemRSFeedbackIO)) 861 val checkWait = new Bundle { 862 val stIssuePtr = Input(new SqPtr) 863 val memWaitUpdateReq = Flipped(new MemWaitUpdateReq) 864 } 865 val loadFastMatch = Output(Vec(params.LdExuCnt, new IssueQueueLoadBundle)) 866 val loadWakeUp = Input(Vec(params.LdExuCnt, ValidIO(new DynInst()))) 867 868 // vector 869 val sqDeqPtr = OptionWrapper(params.isVecMemIQ, Input(new SqPtr)) 870 val lqDeqPtr = OptionWrapper(params.isVecMemIQ, Input(new LqPtr)) 871} 872 873class IssueQueueMemIO(implicit p: Parameters, params: IssueBlockParams) extends IssueQueueIO { 874 val memIO = Some(new IssueQueueMemBundle) 875} 876 877class IssueQueueMemAddrImp(override val wrapper: IssueQueue)(implicit p: Parameters, params: IssueBlockParams) 878 extends IssueQueueImp(wrapper) with HasCircularQueuePtrHelper { 879 880 require(params.StdCnt == 0 && (params.LduCnt + params.StaCnt + params.HyuCnt + params.VlduCnt) > 0, "IssueQueueMemAddrImp can only be instance of MemAddr IQ, " + 881 s"StdCnt: ${params.StdCnt}, LduCnt: ${params.LduCnt}, StaCnt: ${params.StaCnt}, HyuCnt: ${params.HyuCnt}") 882 println(s"[IssueQueueMemAddrImp] StdCnt: ${params.StdCnt}, LduCnt: ${params.LduCnt}, StaCnt: ${params.StaCnt}, HyuCnt: ${params.HyuCnt}") 883 884 io.suggestName("none") 885 override lazy val io = IO(new IssueQueueMemIO).suggestName("io") 886 private val memIO = io.memIO.get 887 888 memIO.loadFastMatch := 0.U.asTypeOf(memIO.loadFastMatch) // TODO: is still needed? 889 890 for (i <- io.enq.indices) { 891 val blockNotReleased = isAfter(io.enq(i).bits.sqIdx, memIO.checkWait.stIssuePtr) 892 val storeAddrWaitForIsIssuing = VecInit((0 until StorePipelineWidth).map(i => { 893 memIO.checkWait.memWaitUpdateReq.robIdx(i).valid && 894 memIO.checkWait.memWaitUpdateReq.robIdx(i).bits.value === io.enq(i).bits.waitForRobIdx.value 895 })).asUInt.orR && !io.enq(i).bits.loadWaitStrict // is waiting for store addr ready 896 s0_enqBits(i).loadWaitBit := io.enq(i).bits.loadWaitBit && !storeAddrWaitForIsIssuing && blockNotReleased 897 // when have vpu 898 if (params.VlduCnt > 0 || params.VstuCnt > 0) { 899 s0_enqBits(i).srcType(3) := SrcType.vp // v0: mask src 900 s0_enqBits(i).srcType(4) := SrcType.vp // vl&vtype 901 } 902 } 903 904 for (i <- entries.io.enq.indices) { 905 entries.io.enq(i).bits.status match { case enqData => 906 enqData.blocked := false.B // s0_enqBits(i).loadWaitBit 907 enqData.mem.get.strictWait := s0_enqBits(i).loadWaitStrict 908 enqData.mem.get.waitForStd := false.B 909 enqData.mem.get.waitForRobIdx := s0_enqBits(i).waitForRobIdx 910 enqData.mem.get.waitForSqIdx := 0.U.asTypeOf(enqData.mem.get.waitForSqIdx) // generated by sq, will be updated later 911 enqData.mem.get.sqIdx := s0_enqBits(i).sqIdx 912 } 913 } 914 entries.io.fromMem.get.slowResp.zipWithIndex.foreach { case (slowResp, i) => 915 slowResp.valid := memIO.feedbackIO(i).feedbackSlow.valid 916 slowResp.bits.robIdx := memIO.feedbackIO(i).feedbackSlow.bits.robIdx 917 slowResp.bits.respType := Mux(memIO.feedbackIO(i).feedbackSlow.bits.hit, RSFeedbackType.fuIdle, RSFeedbackType.feedbackInvalid) 918 slowResp.bits.dataInvalidSqIdx := memIO.feedbackIO(i).feedbackSlow.bits.dataInvalidSqIdx 919 slowResp.bits.rfWen := DontCare 920 slowResp.bits.fuType := DontCare 921 } 922 923 entries.io.fromMem.get.fastResp.zipWithIndex.foreach { case (fastResp, i) => 924 fastResp.valid := memIO.feedbackIO(i).feedbackFast.valid 925 fastResp.bits.robIdx := memIO.feedbackIO(i).feedbackFast.bits.robIdx 926 fastResp.bits.respType := Mux(memIO.feedbackIO(i).feedbackFast.bits.hit, RSFeedbackType.fuIdle, memIO.feedbackIO(i).feedbackFast.bits.sourceType) 927 fastResp.bits.dataInvalidSqIdx := 0.U.asTypeOf(fastResp.bits.dataInvalidSqIdx) 928 fastResp.bits.rfWen := DontCare 929 fastResp.bits.fuType := DontCare 930 } 931 932 entries.io.fromMem.get.memWaitUpdateReq := memIO.checkWait.memWaitUpdateReq 933 entries.io.fromMem.get.stIssuePtr := memIO.checkWait.stIssuePtr 934 935 // load wakeup 936 val loadWakeUpIter = memIO.loadWakeUp.iterator 937 io.wakeupToIQ.zip(params.exuBlockParams).zipWithIndex.foreach { case ((wakeup, param), i) => 938 if (param.hasLoadExu) { 939 require(wakeUpQueues(i).isEmpty) 940 val uop = loadWakeUpIter.next() 941 942 wakeup.valid := RegNext(uop.fire) 943 wakeup.bits.rfWen := RegNext(uop.bits.rfWen && uop.fire) 944 wakeup.bits.fpWen := RegNext(uop.bits.fpWen && uop.fire) 945 wakeup.bits.vecWen := RegNext(uop.bits.vecWen && uop.fire) 946 wakeup.bits.pdest := RegNext(uop.bits.pdest) 947 wakeup.bits.loadDependency.foreach(_ := 0.U) // this is correct for load only 948 949 wakeup.bits.rfWenCopy .foreach(_.foreach(_ := RegNext(uop.bits.rfWen && uop.fire))) 950 wakeup.bits.fpWenCopy .foreach(_.foreach(_ := RegNext(uop.bits.fpWen && uop.fire))) 951 wakeup.bits.vecWenCopy.foreach(_.foreach(_ := RegNext(uop.bits.vecWen && uop.fire))) 952 wakeup.bits.pdestCopy .foreach(_.foreach(_ := RegNext(uop.bits.pdest))) 953 wakeup.bits.loadDependencyCopy.foreach(x => x := 0.U.asTypeOf(x)) // this is correct for load only 954 955 wakeup.bits.is0Lat := 0.U 956 } 957 } 958 require(!loadWakeUpIter.hasNext) 959 960 deqBeforeDly.zipWithIndex.foreach { case (deq, i) => 961 deq.bits.common.loadWaitBit.foreach(_ := deqEntryVec(i).bits.payload.loadWaitBit) 962 deq.bits.common.waitForRobIdx.foreach(_ := deqEntryVec(i).bits.payload.waitForRobIdx) 963 deq.bits.common.storeSetHit.foreach(_ := deqEntryVec(i).bits.payload.storeSetHit) 964 deq.bits.common.loadWaitStrict.foreach(_ := deqEntryVec(i).bits.payload.loadWaitStrict) 965 deq.bits.common.ssid.foreach(_ := deqEntryVec(i).bits.payload.ssid) 966 deq.bits.common.sqIdx.get := deqEntryVec(i).bits.payload.sqIdx 967 deq.bits.common.lqIdx.get := deqEntryVec(i).bits.payload.lqIdx 968 deq.bits.common.ftqIdx.foreach(_ := deqEntryVec(i).bits.payload.ftqPtr) 969 deq.bits.common.ftqOffset.foreach(_ := deqEntryVec(i).bits.payload.ftqOffset) 970 // when have vpu 971 if (params.VlduCnt > 0 || params.VstuCnt > 0) { 972 deq.bits.common.vpu.foreach(_ := deqEntryVec(i).bits.payload.vpu) 973 deq.bits.common.vpu.foreach(_.vuopIdx := deqEntryVec(i).bits.payload.uopIdx) 974 } 975 } 976} 977 978class IssueQueueVecMemImp(override val wrapper: IssueQueue)(implicit p: Parameters, params: IssueBlockParams) 979 extends IssueQueueImp(wrapper) with HasCircularQueuePtrHelper { 980 981 require((params.VstdCnt + params.VlduCnt + params.VstaCnt) > 0, "IssueQueueVecMemImp can only be instance of VecMem IQ") 982 983 io.suggestName("none") 984 override lazy val io = IO(new IssueQueueMemIO).suggestName("io") 985 private val memIO = io.memIO.get 986 987 def selectOldUop(robIdx: Seq[RobPtr], uopIdx: Seq[UInt], valid: Seq[Bool]): Vec[Bool] = { 988 val compareVec = (0 until robIdx.length).map(i => (0 until i).map(j => isAfter(robIdx(j), robIdx(i)) || (robIdx(j).value === robIdx(i).value && uopIdx(i) < uopIdx(j)))) 989 val resultOnehot = VecInit((0 until robIdx.length).map(i => Cat((0 until robIdx.length).map(j => 990 (if (j < i) !valid(j) || compareVec(i)(j) 991 else if (j == i) valid(i) 992 else !valid(j) || !compareVec(j)(i)) 993 )).andR)) 994 resultOnehot 995 } 996 997 val robIdxVec = entries.io.robIdx.get 998 val uopIdxVec = entries.io.uopIdx.get 999 val allEntryOldestOH = selectOldUop(robIdxVec, uopIdxVec, validVec) 1000 1001 finalDeqSelValidVec.head := (allEntryOldestOH.asUInt & canIssueVec.asUInt).orR 1002 finalDeqSelOHVec.head := allEntryOldestOH.asUInt & canIssueVec.asUInt 1003 1004 if (params.isVecMemAddrIQ) { 1005 s0_enqBits.foreach{ x => 1006 x.srcType(3) := SrcType.vp // v0: mask src 1007 x.srcType(4) := SrcType.vp // vl&vtype 1008 } 1009 1010 for (i <- io.enq.indices) { 1011 s0_enqBits(i).loadWaitBit := false.B 1012 } 1013 1014 for (i <- entries.io.enq.indices) { 1015 entries.io.enq(i).bits.status match { case enqData => 1016 enqData.blocked := false.B // s0_enqBits(i).loadWaitBit 1017 enqData.mem.get.strictWait := s0_enqBits(i).loadWaitStrict 1018 enqData.mem.get.waitForStd := false.B 1019 enqData.mem.get.waitForRobIdx := s0_enqBits(i).waitForRobIdx 1020 enqData.mem.get.waitForSqIdx := 0.U.asTypeOf(enqData.mem.get.waitForSqIdx) // generated by sq, will be updated later 1021 enqData.mem.get.sqIdx := s0_enqBits(i).sqIdx 1022 } 1023 1024 entries.io.fromMem.get.slowResp.zipWithIndex.foreach { case (slowResp, i) => 1025 slowResp.valid := memIO.feedbackIO(i).feedbackSlow.valid 1026 slowResp.bits.robIdx := memIO.feedbackIO(i).feedbackSlow.bits.robIdx 1027 slowResp.bits.respType := Mux(memIO.feedbackIO(i).feedbackSlow.bits.hit, RSFeedbackType.fuIdle, RSFeedbackType.feedbackInvalid) 1028 slowResp.bits.dataInvalidSqIdx := memIO.feedbackIO(i).feedbackSlow.bits.dataInvalidSqIdx 1029 slowResp.bits.rfWen := DontCare 1030 slowResp.bits.fuType := DontCare 1031 } 1032 1033 entries.io.fromMem.get.fastResp.zipWithIndex.foreach { case (fastResp, i) => 1034 fastResp.valid := memIO.feedbackIO(i).feedbackFast.valid 1035 fastResp.bits.robIdx := memIO.feedbackIO(i).feedbackFast.bits.robIdx 1036 fastResp.bits.respType := memIO.feedbackIO(i).feedbackFast.bits.sourceType 1037 fastResp.bits.dataInvalidSqIdx := 0.U.asTypeOf(fastResp.bits.dataInvalidSqIdx) 1038 fastResp.bits.rfWen := DontCare 1039 fastResp.bits.fuType := DontCare 1040 } 1041 1042 entries.io.fromMem.get.memWaitUpdateReq := memIO.checkWait.memWaitUpdateReq 1043 entries.io.fromMem.get.stIssuePtr := memIO.checkWait.stIssuePtr 1044 } 1045 } 1046 1047 for (i <- entries.io.enq.indices) { 1048 entries.io.enq(i).bits.status.vecMem.get match { 1049 case enqData => 1050 enqData.sqIdx := s0_enqBits(i).sqIdx 1051 enqData.lqIdx := s0_enqBits(i).lqIdx 1052 enqData.uopIdx := s0_enqBits(i).uopIdx 1053 } 1054 } 1055 1056 entries.io.vecMemIn.get.sqDeqPtr := memIO.sqDeqPtr.get 1057 entries.io.vecMemIn.get.lqDeqPtr := memIO.lqDeqPtr.get 1058 1059 entries.io.fromMem.get.fastResp.zipWithIndex.foreach { case (resp, i) => 1060 resp.bits.uopIdx.get := 0.U // Todo 1061 } 1062 1063 entries.io.fromMem.get.slowResp.zipWithIndex.foreach { case (resp, i) => 1064 resp.bits.uopIdx.get := 0.U // Todo 1065 } 1066 1067 deqBeforeDly.zipWithIndex.foreach { case (deq, i) => 1068 deq.bits.common.sqIdx.foreach(_ := deqEntryVec(i).bits.payload.sqIdx) 1069 deq.bits.common.lqIdx.foreach(_ := deqEntryVec(i).bits.payload.lqIdx) 1070 if (params.isVecLdAddrIQ) { 1071 deq.bits.common.ftqIdx.get := deqEntryVec(i).bits.payload.ftqPtr 1072 deq.bits.common.ftqOffset.get := deqEntryVec(i).bits.payload.ftqOffset 1073 } 1074 deq.bits.common.fpu.foreach(_ := deqEntryVec(i).bits.payload.fpu) 1075 deq.bits.common.vpu.foreach(_ := deqEntryVec(i).bits.payload.vpu) 1076 deq.bits.common.vpu.foreach(_.vuopIdx := deqEntryVec(i).bits.payload.uopIdx) 1077 deq.bits.common.vpu.foreach(_.lastUop := deqEntryVec(i).bits.payload.lastUop) 1078 } 1079} 1080