xref: /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala (revision 195ef4a53ab54326d879e884c4e1568f424f2668) 
1package xiangshan.backend.issue
2
3import org.chipsalliance.cde.config.Parameters
4import chisel3._
5import chisel3.util._
6import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
7import utility.{GTimer, GatedValidRegNext, HasCircularQueuePtrHelper, SelectOne}
8import utils._
9import xiangshan._
10import xiangshan.backend.Bundles._
11import xiangshan.backend.issue.EntryBundles._
12import xiangshan.backend.decode.{ImmUnion, Imm_LUI_LOAD}
13import xiangshan.backend.datapath.DataConfig._
14import xiangshan.backend.datapath.DataSource
15import xiangshan.backend.fu.{FuConfig, FuType}
16import xiangshan.mem.{LqPtr, MemWaitUpdateReq, SqPtr}
17import xiangshan.backend.rob.RobPtr
18import xiangshan.backend.datapath.NewPipelineConnect
19import xiangshan.backend.fu.vector.Bundles.VSew
20
21class IssueQueue(params: IssueBlockParams)(implicit p: Parameters) extends LazyModule with HasXSParameter {
22  override def shouldBeInlined: Boolean = false
23
24  implicit val iqParams: IssueBlockParams = params
25  lazy val module: IssueQueueImp = iqParams.schdType match {
26    case IntScheduler() => new IssueQueueIntImp(this)
27    case FpScheduler() => new IssueQueueFpImp(this)
28    case VfScheduler() => new IssueQueueVfImp(this)
29    case MemScheduler() =>
30      if (iqParams.StdCnt == 0 && !iqParams.isVecMemIQ) new IssueQueueMemAddrImp(this)
31      else if (iqParams.isVecMemIQ) new IssueQueueVecMemImp(this)
32      else new IssueQueueIntImp(this)
33    case _ => null
34  }
35}
36
37class IssueQueueStatusBundle(numEnq: Int, numEntries: Int) extends Bundle {
38  val empty = Output(Bool())
39  val full = Output(Bool())
40  val validCnt = Output(UInt(log2Ceil(numEntries).W))
41  val leftVec = Output(Vec(numEnq + 1, Bool()))
42}
43
44class IssueQueueDeqRespBundle(implicit p:Parameters, params: IssueBlockParams) extends EntryDeqRespBundle
45
46class IssueQueueIO()(implicit p: Parameters, params: IssueBlockParams) extends XSBundle {
47  // Inputs
48  val flush = Flipped(ValidIO(new Redirect))
49  val enq = Vec(params.numEnq, Flipped(DecoupledIO(new DynInst)))
50
51  val og0Resp = Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle)))
52  val og1Resp = Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle)))
53  val og2Resp = OptionWrapper(params.inVfSchd, Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle))))
54  val finalIssueResp = OptionWrapper(params.LdExuCnt > 0, Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle))))
55  val memAddrIssueResp = OptionWrapper(params.LdExuCnt > 0, Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle))))
56  val vecLoadIssueResp = OptionWrapper(params.VlduCnt > 0, Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle))))
57  val wbBusyTableRead = Input(params.genWbFuBusyTableReadBundle())
58  val wbBusyTableWrite = Output(params.genWbFuBusyTableWriteBundle())
59  val wakeupFromWB: MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = Flipped(params.genWBWakeUpSinkValidBundle)
60  val wakeupFromIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(params.genIQWakeUpSinkValidBundle)
61  val vlIsZero = Input(Bool())
62  val vlIsVlmax = Input(Bool())
63  val og0Cancel = Input(ExuOH(backendParams.numExu))
64  val og1Cancel = Input(ExuOH(backendParams.numExu))
65  val ldCancel = Vec(backendParams.LduCnt + backendParams.HyuCnt, Flipped(new LoadCancelIO))
66
67  // Outputs
68  val wakeupToIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = params.genIQWakeUpSourceValidBundle
69  val status = Output(new IssueQueueStatusBundle(params.numEnq, params.numEntries))
70  val validCntDeqVec = Output(Vec(params.numDeq,UInt(params.numEntries.U.getWidth.W)))
71  // val statusNext = Output(new IssueQueueStatusBundle(params.numEnq))
72
73  val deqDelay: MixedVec[DecoupledIO[IssueQueueIssueBundle]] = params.genIssueDecoupledBundle// = deq.cloneType
74  def allWakeUp = wakeupFromWB ++ wakeupFromIQ
75}
76
77class IssueQueueImp(override val wrapper: IssueQueue)(implicit p: Parameters, val params: IssueBlockParams)
78  extends LazyModuleImp(wrapper)
79  with HasXSParameter {
80
81  override def desiredName: String = s"${params.getIQName}"
82
83  println(s"[IssueQueueImp] ${params.getIQName} wakeupFromWB(${io.wakeupFromWB.size}), " +
84    s"wakeup exu in(${params.wakeUpInExuSources.size}): ${params.wakeUpInExuSources.map(_.name).mkString("{",",","}")}, " +
85    s"wakeup exu out(${params.wakeUpOutExuSources.size}): ${params.wakeUpOutExuSources.map(_.name).mkString("{",",","}")}, " +
86    s"numEntries: ${params.numEntries}, numRegSrc: ${params.numRegSrc}, " +
87    s"numEnq: ${params.numEnq}, numSimp: ${params.numSimp}, numComp: ${params.numComp}, numDeq: ${params.numDeq}, " +
88    s"isAllSimp: ${params.isAllSimp}, isAllComp: ${params.isAllComp}")
89
90  require(params.numExu <= 2, "IssueQueue has not supported more than 2 deq ports")
91  require(params.numEnq <= 2, "IssueQueue has not supported more than 2 enq ports")
92  require(params.numSimp == 0 || params.numSimp >= params.numEnq, "numSimp should be 0 or at least not less than numEnq")
93  require(params.numComp == 0 || params.numComp >= params.numEnq, "numComp should be 0 or at least not less than numEnq")
94
95  val deqFuCfgs     : Seq[Seq[FuConfig]] = params.exuBlockParams.map(_.fuConfigs)
96  val allDeqFuCfgs  : Seq[FuConfig] = params.exuBlockParams.flatMap(_.fuConfigs)
97  val fuCfgsCnt     : Map[FuConfig, Int] = allDeqFuCfgs.groupBy(x => x).map { case (cfg, cfgSeq) => (cfg, cfgSeq.length) }
98  val commonFuCfgs  : Seq[FuConfig] = fuCfgsCnt.filter(_._2 > 1).keys.toSeq
99  val wakeupFuLatencyMaps : Seq[Map[FuType.OHType, Int]] = params.exuBlockParams.map(x => x.wakeUpFuLatencyMap)
100
101  println(s"[IssueQueueImp] ${params.getIQName} fuLatencyMaps: ${wakeupFuLatencyMaps}")
102  println(s"[IssueQueueImp] ${params.getIQName} commonFuCfgs: ${commonFuCfgs.map(_.name)}")
103  lazy val io = IO(new IssueQueueIO())
104
105  // Modules
106  val entries = Module(new Entries)
107  val fuBusyTableWrite = params.exuBlockParams.map { case x => OptionWrapper(x.latencyValMax > 0, Module(new FuBusyTableWrite(x.fuLatencyMap))) }
108  val fuBusyTableRead = params.exuBlockParams.map { case x => OptionWrapper(x.latencyValMax > 0, Module(new FuBusyTableRead(x.fuLatencyMap))) }
109  val intWbBusyTableWrite = params.exuBlockParams.map { case x => OptionWrapper(x.intLatencyCertain, Module(new FuBusyTableWrite(x.intFuLatencyMap))) }
110  val intWbBusyTableRead = params.exuBlockParams.map { case x => OptionWrapper(x.intLatencyCertain, Module(new FuBusyTableRead(x.intFuLatencyMap))) }
111  val fpWbBusyTableWrite = params.exuBlockParams.map { case x => OptionWrapper(x.fpLatencyCertain, Module(new FuBusyTableWrite(x.fpFuLatencyMap))) }
112  val fpWbBusyTableRead = params.exuBlockParams.map { case x => OptionWrapper(x.fpLatencyCertain, Module(new FuBusyTableRead(x.fpFuLatencyMap))) }
113  val vfWbBusyTableWrite = params.exuBlockParams.map { case x => OptionWrapper(x.vfLatencyCertain, Module(new FuBusyTableWrite(x.vfFuLatencyMap))) }
114  val vfWbBusyTableRead = params.exuBlockParams.map { case x => OptionWrapper(x.vfLatencyCertain, Module(new FuBusyTableRead(x.vfFuLatencyMap))) }
115  val v0WbBusyTableWrite = params.exuBlockParams.map { case x => OptionWrapper(x.v0LatencyCertain, Module(new FuBusyTableWrite(x.v0FuLatencyMap))) }
116  val v0WbBusyTableRead = params.exuBlockParams.map { case x => OptionWrapper(x.v0LatencyCertain, Module(new FuBusyTableRead(x.v0FuLatencyMap))) }
117  val vlWbBusyTableWrite = params.exuBlockParams.map { case x => OptionWrapper(x.vlLatencyCertain, Module(new FuBusyTableWrite(x.vlFuLatencyMap))) }
118  val vlWbBusyTableRead = params.exuBlockParams.map { case x => OptionWrapper(x.vlLatencyCertain, Module(new FuBusyTableRead(x.vlFuLatencyMap))) }
119
120  class WakeupQueueFlush extends Bundle {
121    val redirect = ValidIO(new Redirect)
122    val ldCancel = Vec(backendParams.LduCnt + backendParams.HyuCnt, new LoadCancelIO)
123    val og0Fail = Output(Bool())
124    val og1Fail = Output(Bool())
125  }
126
127  private def flushFunc(exuInput: ExuInput, flush: WakeupQueueFlush, stage: Int): Bool = {
128    val redirectFlush = exuInput.robIdx.needFlush(flush.redirect)
129    val loadDependencyFlush = LoadShouldCancel(exuInput.loadDependency, flush.ldCancel)
130    val ogFailFlush = stage match {
131      case 1 => flush.og0Fail
132      case 2 => flush.og1Fail
133      case _ => false.B
134    }
135    redirectFlush || loadDependencyFlush || ogFailFlush
136  }
137
138  private def modificationFunc(exuInput: ExuInput): ExuInput = {
139    val newExuInput = WireDefault(exuInput)
140    newExuInput.loadDependency match {
141      case Some(deps) => deps.zip(exuInput.loadDependency.get).foreach(x => x._1 := x._2 << 1)
142      case None =>
143    }
144    newExuInput
145  }
146
147  private def lastConnectFunc(exuInput: ExuInput, newInput: ExuInput): ExuInput = {
148    val lastExuInput = WireDefault(exuInput)
149    val newExuInput = WireDefault(newInput)
150    newExuInput.elements.foreach { case (name, data) =>
151      if (lastExuInput.elements.contains(name)) {
152        data := lastExuInput.elements(name)
153      }
154    }
155    if (newExuInput.pdestCopy.nonEmpty && !lastExuInput.pdestCopy.nonEmpty) {
156      newExuInput.pdestCopy.get.foreach(_ := lastExuInput.pdest)
157    }
158    if (newExuInput.rfWenCopy.nonEmpty && !lastExuInput.rfWenCopy.nonEmpty) {
159      newExuInput.rfWenCopy.get.foreach(_ := lastExuInput.rfWen.get)
160    }
161    if (newExuInput.fpWenCopy.nonEmpty && !lastExuInput.fpWenCopy.nonEmpty) {
162      newExuInput.fpWenCopy.get.foreach(_ := lastExuInput.fpWen.get)
163    }
164    if (newExuInput.vecWenCopy.nonEmpty && !lastExuInput.vecWenCopy.nonEmpty) {
165      newExuInput.vecWenCopy.get.foreach(_ := lastExuInput.vecWen.get)
166    }
167    if (newExuInput.v0WenCopy.nonEmpty && !lastExuInput.v0WenCopy.nonEmpty) {
168      newExuInput.v0WenCopy.get.foreach(_ := lastExuInput.v0Wen.get)
169    }
170    if (newExuInput.vlWenCopy.nonEmpty && !lastExuInput.vlWenCopy.nonEmpty) {
171      newExuInput.vlWenCopy.get.foreach(_ := lastExuInput.vlWen.get)
172    }
173    if (newExuInput.loadDependencyCopy.nonEmpty && !lastExuInput.loadDependencyCopy.nonEmpty) {
174      newExuInput.loadDependencyCopy.get.foreach(_ := lastExuInput.loadDependency.get)
175    }
176    newExuInput
177  }
178
179  val wakeUpQueues: Seq[Option[MultiWakeupQueue[ExuInput, WakeupQueueFlush]]] = params.exuBlockParams.map { x => OptionWrapper(x.isIQWakeUpSource && !x.hasLoadExu, Module(
180    new MultiWakeupQueue(new ExuInput(x), new ExuInput(x, x.copyWakeupOut, x.copyNum), new WakeupQueueFlush, x.wakeUpFuLatancySet, flushFunc, modificationFunc, lastConnectFunc)
181  ))}
182  val deqBeforeDly = Wire(params.genIssueDecoupledBundle)
183
184  val intWbBusyTableIn = io.wbBusyTableRead.map(_.intWbBusyTable)
185  val fpWbBusyTableIn = io.wbBusyTableRead.map(_.fpWbBusyTable)
186  val vfWbBusyTableIn = io.wbBusyTableRead.map(_.vfWbBusyTable)
187  val v0WbBusyTableIn = io.wbBusyTableRead.map(_.v0WbBusyTable)
188  val vlWbBusyTableIn = io.wbBusyTableRead.map(_.vlWbBusyTable)
189
190  val intWbBusyTableOut = io.wbBusyTableWrite.map(_.intWbBusyTable)
191  val fpWbBusyTableOut = io.wbBusyTableWrite.map(_.fpWbBusyTable)
192  val vfWbBusyTableOut = io.wbBusyTableWrite.map(_.vfWbBusyTable)
193  val v0WbBusyTableOut = io.wbBusyTableWrite.map(_.v0WbBusyTable)
194  val vlWbBusyTableOut = io.wbBusyTableWrite.map(_.vlWbBusyTable)
195
196  val intDeqRespSetOut = io.wbBusyTableWrite.map(_.intDeqRespSet)
197  val fpDeqRespSetOut = io.wbBusyTableWrite.map(_.fpDeqRespSet)
198  val vfDeqRespSetOut = io.wbBusyTableWrite.map(_.vfDeqRespSet)
199  val v0DeqRespSetOut = io.wbBusyTableWrite.map(_.v0DeqRespSet)
200  val vlDeqRespSetOut = io.wbBusyTableWrite.map(_.vlDeqRespSet)
201
202  val fuBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W)))
203  val intWbBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W)))
204  val fpWbBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W)))
205  val vfWbBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W)))
206  val v0WbBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W)))
207  val vlWbBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W)))
208
209  val s0_enqValidVec = io.enq.map(_.valid)
210  val s0_enqSelValidVec = Wire(Vec(params.numEnq, Bool()))
211  val s0_enqNotFlush = !io.flush.valid
212  val s0_enqBits = WireInit(VecInit(io.enq.map(_.bits)))
213  val s0_doEnqSelValidVec = s0_enqSelValidVec.map(_ && s0_enqNotFlush) //enqValid && notFlush && enqReady
214
215
216  val finalDeqSelValidVec = Wire(Vec(params.numDeq, Bool()))
217  val finalDeqSelOHVec    = Wire(Vec(params.numDeq, UInt(params.numEntries.W)))
218
219  val validVec = VecInit(entries.io.valid.asBools)
220  val canIssueVec = VecInit(entries.io.canIssue.asBools)
221  dontTouch(canIssueVec)
222  val deqFirstIssueVec = entries.io.isFirstIssue
223
224  val dataSources: Vec[Vec[DataSource]] = entries.io.dataSources
225  val finalDataSources: Vec[Vec[DataSource]] = VecInit(finalDeqSelOHVec.map(oh => Mux1H(oh, dataSources)))
226  val loadDependency: Vec[Vec[UInt]] = entries.io.loadDependency
227  val finalLoadDependency: IndexedSeq[Vec[UInt]] = VecInit(finalDeqSelOHVec.map(oh => Mux1H(oh, loadDependency)))
228  // (entryIdx)(srcIdx)(exuIdx)
229  val wakeUpL1ExuOH: Option[Vec[Vec[Vec[Bool]]]] = entries.io.srcWakeUpL1ExuOH
230  // (deqIdx)(srcIdx)(exuIdx)
231  val finalWakeUpL1ExuOH: Option[Vec[Vec[Vec[Bool]]]] = wakeUpL1ExuOH.map(x => VecInit(finalDeqSelOHVec.map(oh => Mux1H(oh, x))))
232
233  val fuTypeVec = Wire(Vec(params.numEntries, FuType()))
234  val deqEntryVec = Wire(Vec(params.numDeq, ValidIO(new EntryBundle)))
235  val canIssueMergeAllBusy = Wire(Vec(params.numDeq, UInt(params.numEntries.W)))
236  val deqCanIssue = Wire(Vec(params.numDeq, UInt(params.numEntries.W)))
237
238  //deq
239  val enqEntryOldestSel = Wire(Vec(params.numDeq, ValidIO(UInt(params.numEnq.W))))
240  val simpEntryOldestSel = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numDeq + params.numEnq, ValidIO(UInt(params.numSimp.W)))))
241  val compEntryOldestSel = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numDeq, ValidIO(UInt(params.numComp.W)))))
242  val othersEntryOldestSel = Wire(Vec(params.numDeq, ValidIO(UInt((params.numEntries - params.numEnq).W))))
243  val deqSelValidVec = Wire(Vec(params.numDeq, Bool()))
244  val deqSelOHVec    = Wire(Vec(params.numDeq, UInt(params.numEntries.W)))
245  val cancelDeqVec = Wire(Vec(params.numDeq, Bool()))
246
247  val subDeqSelValidVec = OptionWrapper(params.deqFuSame, Wire(Vec(params.numDeq, Bool())))
248  val subDeqSelOHVec = OptionWrapper(params.deqFuSame, Wire(Vec(params.numDeq, UInt(params.numEntries.W))))
249  val subDeqRequest = OptionWrapper(params.deqFuSame, Wire(UInt(params.numEntries.W)))
250
251  //trans
252  val simpEntryEnqSelVec = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numEnq, UInt(params.numSimp.W))))
253  val compEntryEnqSelVec = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numEnq, UInt(params.numComp.W))))
254  val othersEntryEnqSelVec = OptionWrapper(params.isAllComp || params.isAllSimp, Wire(Vec(params.numEnq, UInt((params.numEntries - params.numEnq).W))))
255  val simpAgeDetectRequest = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numDeq + params.numEnq, UInt(params.numSimp.W))))
256  simpAgeDetectRequest.foreach(_ := 0.U.asTypeOf(simpAgeDetectRequest.get))
257
258  // when vf exu (with og2) wake up int/mem iq (without og2), the wakeup signals should delay 1 cycle
259  // as vf exu's min latency is 1, we do not need consider og0cancel
260  val wakeupFromIQ = Wire(chiselTypeOf(io.wakeupFromIQ))
261  wakeupFromIQ.zip(io.wakeupFromIQ).foreach { case (w, w_src) =>
262    if (!params.inVfSchd && params.readVfRf && params.hasWakeupFromVf && w_src.bits.params.isVfExeUnit) {
263      val noCancel = !LoadShouldCancel(Some(w_src.bits.loadDependency), io.ldCancel)
264      w := RegNext(Mux(noCancel, w_src, 0.U.asTypeOf(w)))
265      w.bits.loadDependency.zip(w_src.bits.loadDependency).foreach{ case (ld, ld_src) => ld := RegNext(Mux(noCancel, ld_src << 1, 0.U.asTypeOf(ld))) }
266    } else {
267      w := w_src
268    }
269  }
270
271  /**
272    * Connection of [[entries]]
273    */
274  entries.io match { case entriesIO: EntriesIO =>
275    entriesIO.flush                                             := io.flush
276    entriesIO.enq.zipWithIndex.foreach { case (enq, enqIdx) =>
277      enq.valid                                                 := s0_doEnqSelValidVec(enqIdx)
278      enq.bits.status.robIdx                                    := s0_enqBits(enqIdx).robIdx
279      enq.bits.status.fuType                                    := IQFuType.readFuType(VecInit(s0_enqBits(enqIdx).fuType.asBools), params.getFuCfgs.map(_.fuType))
280      val numLsrc = s0_enqBits(enqIdx).srcType.size.min(enq.bits.status.srcStatus.map(_.srcType).size)
281      for(j <- 0 until numLsrc) {
282        enq.bits.status.srcStatus(j).psrc                       := s0_enqBits(enqIdx).psrc(j)
283        enq.bits.status.srcStatus(j).srcType                    := s0_enqBits(enqIdx).srcType(j)
284        enq.bits.status.srcStatus(j).srcState                   := (if (j < 3) {
285                                                                      Mux(SrcType.isVp(s0_enqBits(enqIdx).srcType(j)) && (s0_enqBits(enqIdx).psrc(j) === 0.U),
286                                                                          SrcState.rdy,
287                                                                          s0_enqBits(enqIdx).srcState(j))
288                                                                    } else {
289                                                                      s0_enqBits(enqIdx).srcState(j)
290                                                                    })
291        enq.bits.status.srcStatus(j).dataSources.value          := (if (j < 3) {
292                                                                      MuxCase(DataSource.reg, Seq(
293                                                                        (SrcType.isXp(s0_enqBits(enqIdx).srcType(j)) && (s0_enqBits(enqIdx).psrc(j) === 0.U)) -> DataSource.zero,
294                                                                        SrcType.isNotReg(s0_enqBits(enqIdx).srcType(j))                                       -> DataSource.imm,
295                                                                        (SrcType.isVp(s0_enqBits(enqIdx).srcType(j)) && (s0_enqBits(enqIdx).psrc(j) === 0.U)) -> DataSource.v0,
296                                                                      ))
297                                                                    } else {
298                                                                      MuxCase(DataSource.reg, Seq(
299                                                                        SrcType.isNotReg(s0_enqBits(enqIdx).srcType(j))  -> DataSource.imm,
300                                                                      ))
301                                                                    })
302        enq.bits.status.srcStatus(j).srcLoadDependency          := VecInit(s0_enqBits(enqIdx).srcLoadDependency(j).map(x => x << 1))
303        if(params.hasIQWakeUp) {
304          enq.bits.status.srcStatus(j).srcWakeUpL1ExuOH.get     := 0.U.asTypeOf(ExuVec())
305        }
306      }
307      enq.bits.status.blocked                                   := false.B
308      enq.bits.status.issued                                    := false.B
309      enq.bits.status.firstIssue                                := false.B
310      enq.bits.status.issueTimer                                := "b11".U
311      enq.bits.status.deqPortIdx                                := 0.U
312      enq.bits.imm.foreach(_                                    := s0_enqBits(enqIdx).imm)
313      enq.bits.payload                                          := s0_enqBits(enqIdx)
314    }
315    entriesIO.og0Resp.zipWithIndex.foreach { case (og0Resp, i) =>
316      og0Resp                                                   := io.og0Resp(i)
317    }
318    entriesIO.og1Resp.zipWithIndex.foreach { case (og1Resp, i) =>
319      og1Resp                                                   := io.og1Resp(i)
320    }
321    if (params.inVfSchd) {
322      entriesIO.og2Resp.get.zipWithIndex.foreach { case (og2Resp, i) =>
323        og2Resp                                                 := io.og2Resp.get(i)
324      }
325    }
326    if (params.isLdAddrIQ || params.isHyAddrIQ) {
327      entriesIO.fromLoad.get.finalIssueResp.zipWithIndex.foreach { case (finalIssueResp, i) =>
328        finalIssueResp                                          := io.finalIssueResp.get(i)
329      }
330      entriesIO.fromLoad.get.memAddrIssueResp.zipWithIndex.foreach { case (memAddrIssueResp, i) =>
331        memAddrIssueResp                                        := io.memAddrIssueResp.get(i)
332      }
333    }
334    if (params.isVecLduIQ) {
335      entriesIO.vecLdIn.get.resp.zipWithIndex.foreach { case (resp, i) =>
336        resp                                                    := io.vecLoadIssueResp.get(i)
337      }
338    }
339    for(deqIdx <- 0 until params.numDeq) {
340      entriesIO.deqReady(deqIdx)                                := deqBeforeDly(deqIdx).ready
341      entriesIO.deqSelOH(deqIdx).valid                          := deqSelValidVec(deqIdx)
342      entriesIO.deqSelOH(deqIdx).bits                           := deqSelOHVec(deqIdx)
343      entriesIO.enqEntryOldestSel(deqIdx)                       := enqEntryOldestSel(deqIdx)
344      entriesIO.simpEntryOldestSel.foreach(_(deqIdx)            := simpEntryOldestSel.get(deqIdx))
345      entriesIO.compEntryOldestSel.foreach(_(deqIdx)            := compEntryOldestSel.get(deqIdx))
346      entriesIO.othersEntryOldestSel.foreach(_(deqIdx)          := othersEntryOldestSel(deqIdx))
347      entriesIO.subDeqRequest.foreach(_(deqIdx)                 := subDeqRequest.get)
348      entriesIO.subDeqSelOH.foreach(_(deqIdx)                   := subDeqSelOHVec.get(deqIdx))
349    }
350    entriesIO.wakeUpFromWB                                      := io.wakeupFromWB
351    entriesIO.wakeUpFromIQ                                      := wakeupFromIQ
352    entriesIO.vlIsZero                                          := io.vlIsZero
353    entriesIO.vlIsVlmax                                         := io.vlIsVlmax
354    entriesIO.og0Cancel                                         := io.og0Cancel
355    entriesIO.og1Cancel                                         := io.og1Cancel
356    entriesIO.ldCancel                                          := io.ldCancel
357    entriesIO.simpEntryDeqSelVec.foreach(_                      := VecInit(simpEntryOldestSel.get.takeRight(params.numEnq).map(_.bits)))
358    //output
359    fuTypeVec                                                   := entriesIO.fuType
360    deqEntryVec                                                 := entriesIO.deqEntry
361    cancelDeqVec                                                := entriesIO.cancelDeqVec
362    simpEntryEnqSelVec.foreach(_                                := entriesIO.simpEntryEnqSelVec.get)
363    compEntryEnqSelVec.foreach(_                                := entriesIO.compEntryEnqSelVec.get)
364    othersEntryEnqSelVec.foreach(_                              := entriesIO.othersEntryEnqSelVec.get)
365  }
366
367
368  s0_enqSelValidVec := s0_enqValidVec.zip(io.enq).map{ case (enqValid, enq) => enqValid && enq.ready}
369
370  protected val commonAccept: UInt = Cat(fuTypeVec.map(fuType =>
371    FuType.FuTypeOrR(fuType, commonFuCfgs.map(_.fuType))
372  ).reverse)
373
374  // if deq port can accept the uop
375  protected val canAcceptVec: Seq[UInt] = deqFuCfgs.map { fuCfgs: Seq[FuConfig] =>
376    Cat(fuTypeVec.map(fuType =>
377      FuType.FuTypeOrR(fuType, fuCfgs.map(_.fuType))
378    ).reverse)
379  }
380
381  protected val deqCanAcceptVec: Seq[IndexedSeq[Bool]] = deqFuCfgs.map { fuCfgs: Seq[FuConfig] =>
382    fuTypeVec.map(fuType =>
383      FuType.FuTypeOrR(fuType, fuCfgs.map(_.fuType)))
384  }
385
386  canIssueMergeAllBusy.zipWithIndex.foreach { case (merge, i) =>
387    val mergeFuBusy = {
388      if (fuBusyTableWrite(i).nonEmpty) canIssueVec.asUInt & (~fuBusyTableMask(i))
389      else canIssueVec.asUInt
390    }
391    val mergeIntWbBusy = {
392      if (intWbBusyTableRead(i).nonEmpty) mergeFuBusy & (~intWbBusyTableMask(i))
393      else mergeFuBusy
394    }
395    val mergefpWbBusy = {
396      if (fpWbBusyTableRead(i).nonEmpty) mergeIntWbBusy & (~fpWbBusyTableMask(i))
397      else mergeIntWbBusy
398    }
399    val mergeVfWbBusy = {
400      if (vfWbBusyTableRead(i).nonEmpty) mergefpWbBusy & (~vfWbBusyTableMask(i))
401      else mergefpWbBusy
402    }
403    val mergeV0WbBusy = {
404      if (v0WbBusyTableRead(i).nonEmpty) mergeVfWbBusy & (~v0WbBusyTableMask(i))
405      else mergeVfWbBusy
406    }
407    val mergeVlWbBusy = {
408      if (vlWbBusyTableRead(i).nonEmpty) mergeV0WbBusy & (~vlWbBusyTableMask(i))
409      else  mergeV0WbBusy
410    }
411    merge := mergeVlWbBusy
412  }
413
414  deqCanIssue.zipWithIndex.foreach { case (req, i) =>
415    req := canIssueMergeAllBusy(i) & VecInit(deqCanAcceptVec(i)).asUInt
416  }
417  dontTouch(fuTypeVec)
418  dontTouch(canIssueMergeAllBusy)
419  dontTouch(deqCanIssue)
420
421  if (params.numDeq == 2) {
422    require(params.deqFuSame || params.deqFuDiff, "The 2 deq ports need to be identical or completely different")
423  }
424
425  if (params.numDeq == 2 && params.deqFuSame) {
426    val subDeqPolicy = Module(new DeqPolicy())
427
428    enqEntryOldestSel := DontCare
429
430    if (params.isAllComp || params.isAllSimp) {
431      othersEntryOldestSel(0) := AgeDetector(numEntries = params.numEntries - params.numEnq,
432        enq = othersEntryEnqSelVec.get,
433        canIssue = canIssueVec.asUInt(params.numEntries-1, params.numEnq)
434      )
435      othersEntryOldestSel(1) := DontCare
436
437      subDeqPolicy.io.request := subDeqRequest.get
438      subDeqSelValidVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => oh.valid)
439      subDeqSelOHVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => oh.bits)
440    }
441    else {
442      simpAgeDetectRequest.get(0) := canIssueVec.asUInt(params.numEnq + params.numSimp - 1, params.numEnq)
443      simpAgeDetectRequest.get(1) := DontCare
444      simpAgeDetectRequest.get(params.numDeq) := VecInit(validVec.drop(params.numEnq).take(params.numSimp)).asUInt
445      if (params.numEnq == 2) {
446        simpAgeDetectRequest.get(params.numDeq + 1) := VecInit(validVec.drop(params.numEnq).take(params.numSimp)).asUInt & ~simpEntryOldestSel.get(params.numDeq).bits
447      }
448
449      simpEntryOldestSel.get := AgeDetector(numEntries = params.numSimp,
450        enq = simpEntryEnqSelVec.get,
451        canIssue = simpAgeDetectRequest.get
452      )
453
454      compEntryOldestSel.get(0) := AgeDetector(numEntries = params.numComp,
455        enq = compEntryEnqSelVec.get,
456        canIssue = canIssueVec.asUInt(params.numEntries - 1, params.numEnq + params.numSimp)
457      )
458      compEntryOldestSel.get(1) := DontCare
459
460      othersEntryOldestSel(0).valid := compEntryOldestSel.get(0).valid || simpEntryOldestSel.get(0).valid
461      othersEntryOldestSel(0).bits := Cat(
462        compEntryOldestSel.get(0).bits,
463        Fill(params.numSimp, !compEntryOldestSel.get(0).valid) & simpEntryOldestSel.get(0).bits,
464      )
465      othersEntryOldestSel(1) := DontCare
466
467      subDeqPolicy.io.request := Reverse(subDeqRequest.get)
468      subDeqSelValidVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => oh.valid)
469      subDeqSelOHVec.get := subDeqPolicy.io.deqSelOHVec.map(oh => Reverse(oh.bits))
470    }
471
472    subDeqRequest.get := canIssueVec.asUInt & ~Cat(othersEntryOldestSel(0).bits, 0.U((params.numEnq).W))
473
474    deqSelValidVec(0) := othersEntryOldestSel(0).valid || subDeqSelValidVec.get(1)
475    deqSelValidVec(1) := subDeqSelValidVec.get(0)
476    deqSelOHVec(0) := Mux(othersEntryOldestSel(0).valid,
477                          Cat(othersEntryOldestSel(0).bits, 0.U((params.numEnq).W)),
478                          subDeqSelOHVec.get(1)) & canIssueMergeAllBusy(0)
479    deqSelOHVec(1) := subDeqSelOHVec.get(0) & canIssueMergeAllBusy(1)
480
481    finalDeqSelValidVec.zip(finalDeqSelOHVec).zip(deqSelValidVec).zip(deqSelOHVec).zipWithIndex.foreach { case ((((selValid, selOH), deqValid), deqOH), i) =>
482      selValid := deqValid && deqOH.orR && deqBeforeDly(i).ready
483      selOH := deqOH
484    }
485  }
486  else {
487    enqEntryOldestSel := NewAgeDetector(numEntries = params.numEnq,
488      enq = VecInit(s0_doEnqSelValidVec),
489      canIssue = VecInit(deqCanIssue.map(_(params.numEnq - 1, 0)))
490    )
491
492    if (params.isAllComp || params.isAllSimp) {
493      othersEntryOldestSel := AgeDetector(numEntries = params.numEntries - params.numEnq,
494        enq = othersEntryEnqSelVec.get,
495        canIssue = VecInit(deqCanIssue.map(_(params.numEntries - 1, params.numEnq)))
496      )
497
498      deqSelValidVec.zip(deqSelOHVec).zipWithIndex.foreach { case ((selValid, selOH), i) =>
499        if (params.exuBlockParams(i).fuConfigs.contains(FuConfig.FakeHystaCfg)) {
500          selValid := false.B
501          selOH := 0.U.asTypeOf(selOH)
502        } else {
503          selValid := othersEntryOldestSel(i).valid || enqEntryOldestSel(i).valid
504          selOH := Cat(othersEntryOldestSel(i).bits, Fill(params.numEnq, !othersEntryOldestSel(i).valid) & enqEntryOldestSel(i).bits)
505        }
506      }
507    }
508    else {
509      othersEntryOldestSel := DontCare
510
511      deqCanIssue.zipWithIndex.foreach { case (req, i) =>
512        simpAgeDetectRequest.get(i) := req(params.numEnq + params.numSimp - 1, params.numEnq)
513      }
514      simpAgeDetectRequest.get(params.numDeq) := VecInit(validVec.drop(params.numEnq).take(params.numSimp)).asUInt
515      if (params.numEnq == 2) {
516        simpAgeDetectRequest.get(params.numDeq + 1) := VecInit(validVec.drop(params.numEnq).take(params.numSimp)).asUInt & ~simpEntryOldestSel.get(params.numDeq).bits
517      }
518
519      simpEntryOldestSel.get := AgeDetector(numEntries = params.numSimp,
520        enq = simpEntryEnqSelVec.get,
521        canIssue = simpAgeDetectRequest.get
522      )
523
524      compEntryOldestSel.get := AgeDetector(numEntries = params.numComp,
525        enq = compEntryEnqSelVec.get,
526        canIssue = VecInit(deqCanIssue.map(_(params.numEntries - 1, params.numEnq + params.numSimp)))
527      )
528
529      deqSelValidVec.zip(deqSelOHVec).zipWithIndex.foreach { case ((selValid, selOH), i) =>
530        if (params.exuBlockParams(i).fuConfigs.contains(FuConfig.FakeHystaCfg)) {
531          selValid := false.B
532          selOH := 0.U.asTypeOf(selOH)
533        } else {
534          selValid := compEntryOldestSel.get(i).valid || simpEntryOldestSel.get(i).valid || enqEntryOldestSel(i).valid
535          selOH := Cat(
536            compEntryOldestSel.get(i).bits,
537            Fill(params.numSimp, !compEntryOldestSel.get(i).valid) & simpEntryOldestSel.get(i).bits,
538            Fill(params.numEnq, !compEntryOldestSel.get(i).valid && !simpEntryOldestSel.get(i).valid) & enqEntryOldestSel(i).bits
539          )
540        }
541      }
542    }
543
544    finalDeqSelValidVec.zip(finalDeqSelOHVec).zip(deqSelValidVec).zip(deqSelOHVec).zipWithIndex.foreach { case ((((selValid, selOH), deqValid), deqOH), i) =>
545      selValid := deqValid && deqBeforeDly(i).ready
546      selOH := deqOH
547    }
548  }
549
550  val toBusyTableDeqResp = Wire(Vec(params.numDeq, ValidIO(new IssueQueueDeqRespBundle)))
551
552  toBusyTableDeqResp.zipWithIndex.foreach { case (deqResp, i) =>
553    deqResp.valid := finalDeqSelValidVec(i)
554    deqResp.bits.resp   := RespType.success
555    deqResp.bits.robIdx := DontCare
556    deqResp.bits.fuType := deqBeforeDly(i).bits.common.fuType
557    deqResp.bits.uopIdx.foreach(_ := DontCare)
558  }
559
560  //fuBusyTable
561  fuBusyTableWrite.zip(fuBusyTableRead).zipWithIndex.foreach { case ((busyTableWrite: Option[FuBusyTableWrite], busyTableRead: Option[FuBusyTableRead]), i) =>
562    if(busyTableWrite.nonEmpty) {
563      val btwr = busyTableWrite.get
564      val btrd = busyTableRead.get
565      btwr.io.in.deqResp := toBusyTableDeqResp(i)
566      btwr.io.in.og0Resp := io.og0Resp(i)
567      btwr.io.in.og1Resp := io.og1Resp(i)
568      btrd.io.in.fuBusyTable := btwr.io.out.fuBusyTable
569      btrd.io.in.fuTypeRegVec := fuTypeVec
570      fuBusyTableMask(i) := btrd.io.out.fuBusyTableMask
571    }
572    else {
573      fuBusyTableMask(i) := 0.U(params.numEntries.W)
574    }
575  }
576
577  //wbfuBusyTable write
578  intWbBusyTableWrite.zip(intWbBusyTableOut).zip(intDeqRespSetOut).zipWithIndex.foreach { case (((busyTableWrite: Option[FuBusyTableWrite], busyTable: Option[UInt]), deqResp), i) =>
579    if(busyTableWrite.nonEmpty) {
580      val btwr = busyTableWrite.get
581      val bt = busyTable.get
582      val dq = deqResp.get
583      btwr.io.in.deqResp := toBusyTableDeqResp(i)
584      btwr.io.in.og0Resp := io.og0Resp(i)
585      btwr.io.in.og1Resp := io.og1Resp(i)
586      bt := btwr.io.out.fuBusyTable
587      dq := btwr.io.out.deqRespSet
588    }
589  }
590
591  fpWbBusyTableWrite.zip(fpWbBusyTableOut).zip(fpDeqRespSetOut).zipWithIndex.foreach { case (((busyTableWrite: Option[FuBusyTableWrite], busyTable: Option[UInt]), deqResp), i) =>
592    if (busyTableWrite.nonEmpty) {
593      val btwr = busyTableWrite.get
594      val bt = busyTable.get
595      val dq = deqResp.get
596      btwr.io.in.deqResp := toBusyTableDeqResp(i)
597      btwr.io.in.og0Resp := io.og0Resp(i)
598      btwr.io.in.og1Resp := io.og1Resp(i)
599      bt := btwr.io.out.fuBusyTable
600      dq := btwr.io.out.deqRespSet
601    }
602  }
603
604  vfWbBusyTableWrite.zip(vfWbBusyTableOut).zip(vfDeqRespSetOut).zipWithIndex.foreach { case (((busyTableWrite: Option[FuBusyTableWrite], busyTable: Option[UInt]), deqResp), i) =>
605    if (busyTableWrite.nonEmpty) {
606      val btwr = busyTableWrite.get
607      val bt = busyTable.get
608      val dq = deqResp.get
609      btwr.io.in.deqResp := toBusyTableDeqResp(i)
610      btwr.io.in.og0Resp := io.og0Resp(i)
611      btwr.io.in.og1Resp := io.og1Resp(i)
612      bt := btwr.io.out.fuBusyTable
613      dq := btwr.io.out.deqRespSet
614    }
615  }
616
617  v0WbBusyTableWrite.zip(v0WbBusyTableOut).zip(v0DeqRespSetOut).zipWithIndex.foreach { case (((busyTableWrite: Option[FuBusyTableWrite], busyTable: Option[UInt]), deqResp), i) =>
618    if (busyTableWrite.nonEmpty) {
619      val btwr = busyTableWrite.get
620      val bt = busyTable.get
621      val dq = deqResp.get
622      btwr.io.in.deqResp := toBusyTableDeqResp(i)
623      btwr.io.in.og0Resp := io.og0Resp(i)
624      btwr.io.in.og1Resp := io.og1Resp(i)
625      bt := btwr.io.out.fuBusyTable
626      dq := btwr.io.out.deqRespSet
627    }
628  }
629
630  vlWbBusyTableWrite.zip(vlWbBusyTableOut).zip(vlDeqRespSetOut).zipWithIndex.foreach { case (((busyTableWrite: Option[FuBusyTableWrite], busyTable: Option[UInt]), deqResp), i) =>
631    if (busyTableWrite.nonEmpty) {
632      val btwr = busyTableWrite.get
633      val bt = busyTable.get
634      val dq = deqResp.get
635      btwr.io.in.deqResp := toBusyTableDeqResp(i)
636      btwr.io.in.og0Resp := io.og0Resp(i)
637      btwr.io.in.og1Resp := io.og1Resp(i)
638      bt := btwr.io.out.fuBusyTable
639      dq := btwr.io.out.deqRespSet
640    }
641  }
642
643  //wbfuBusyTable read
644  intWbBusyTableRead.zip(intWbBusyTableIn).zipWithIndex.foreach { case ((busyTableRead: Option[FuBusyTableRead], busyTable: Option[UInt]), i) =>
645    if(busyTableRead.nonEmpty) {
646      val btrd = busyTableRead.get
647      val bt = busyTable.get
648      btrd.io.in.fuBusyTable := bt
649      btrd.io.in.fuTypeRegVec := fuTypeVec
650      intWbBusyTableMask(i) := btrd.io.out.fuBusyTableMask
651    }
652    else {
653      intWbBusyTableMask(i) := 0.U(params.numEntries.W)
654    }
655  }
656  fpWbBusyTableRead.zip(fpWbBusyTableIn).zipWithIndex.foreach { case ((busyTableRead: Option[FuBusyTableRead], busyTable: Option[UInt]), i) =>
657    if (busyTableRead.nonEmpty) {
658      val btrd = busyTableRead.get
659      val bt = busyTable.get
660      btrd.io.in.fuBusyTable := bt
661      btrd.io.in.fuTypeRegVec := fuTypeVec
662      fpWbBusyTableMask(i) := btrd.io.out.fuBusyTableMask
663    }
664    else {
665      fpWbBusyTableMask(i) := 0.U(params.numEntries.W)
666    }
667  }
668  vfWbBusyTableRead.zip(vfWbBusyTableIn).zipWithIndex.foreach { case ((busyTableRead: Option[FuBusyTableRead], busyTable: Option[UInt]), i) =>
669    if (busyTableRead.nonEmpty) {
670      val btrd = busyTableRead.get
671      val bt = busyTable.get
672      btrd.io.in.fuBusyTable := bt
673      btrd.io.in.fuTypeRegVec := fuTypeVec
674      vfWbBusyTableMask(i) := btrd.io.out.fuBusyTableMask
675    }
676    else {
677      vfWbBusyTableMask(i) := 0.U(params.numEntries.W)
678    }
679  }
680  v0WbBusyTableRead.zip(v0WbBusyTableIn).zipWithIndex.foreach { case ((busyTableRead: Option[FuBusyTableRead], busyTable: Option[UInt]), i) =>
681    if (busyTableRead.nonEmpty) {
682      val btrd = busyTableRead.get
683      val bt = busyTable.get
684      btrd.io.in.fuBusyTable := bt
685      btrd.io.in.fuTypeRegVec := fuTypeVec
686      v0WbBusyTableMask(i) := btrd.io.out.fuBusyTableMask
687    }
688    else {
689      v0WbBusyTableMask(i) := 0.U(params.numEntries.W)
690    }
691  }
692  vlWbBusyTableRead.zip(vlWbBusyTableIn).zipWithIndex.foreach { case ((busyTableRead: Option[FuBusyTableRead], busyTable: Option[UInt]), i) =>
693    if (busyTableRead.nonEmpty) {
694      val btrd = busyTableRead.get
695      val bt = busyTable.get
696      btrd.io.in.fuBusyTable := bt
697      btrd.io.in.fuTypeRegVec := fuTypeVec
698      vlWbBusyTableMask(i) := btrd.io.out.fuBusyTableMask
699    }
700    else {
701      vlWbBusyTableMask(i) := 0.U(params.numEntries.W)
702    }
703  }
704
705  wakeUpQueues.zipWithIndex.foreach { case (wakeUpQueueOption, i) =>
706    wakeUpQueueOption.foreach {
707      wakeUpQueue =>
708        val flush = Wire(new WakeupQueueFlush)
709        flush.redirect := io.flush
710        flush.ldCancel := io.ldCancel
711        flush.og0Fail := io.og0Resp(i).valid && RespType.isBlocked(io.og0Resp(i).bits.resp)
712        flush.og1Fail := io.og1Resp(i).valid && RespType.isBlocked(io.og1Resp(i).bits.resp)
713        wakeUpQueue.io.flush := flush
714        wakeUpQueue.io.enq.valid := deqBeforeDly(i).valid
715        wakeUpQueue.io.enq.bits.uop :<= deqBeforeDly(i).bits.common
716        wakeUpQueue.io.enq.bits.uop.pdestCopy.foreach(_ := 0.U)
717        wakeUpQueue.io.enq.bits.lat := getDeqLat(i, deqBeforeDly(i).bits.common.fuType)
718    }
719  }
720
721  deqBeforeDly.zipWithIndex.foreach { case (deq, i) =>
722    deq.valid                := finalDeqSelValidVec(i) && !cancelDeqVec(i)
723    deq.bits.addrOH          := finalDeqSelOHVec(i)
724    deq.bits.common.isFirstIssue := deqFirstIssueVec(i)
725    deq.bits.common.iqIdx    := OHToUInt(finalDeqSelOHVec(i))
726    deq.bits.common.fuType   := IQFuType.readFuType(deqEntryVec(i).bits.status.fuType, params.getFuCfgs.map(_.fuType)).asUInt
727    deq.bits.common.fuOpType := deqEntryVec(i).bits.payload.fuOpType
728    deq.bits.common.rfWen.foreach(_ := deqEntryVec(i).bits.payload.rfWen)
729    deq.bits.common.fpWen.foreach(_ := deqEntryVec(i).bits.payload.fpWen)
730    deq.bits.common.vecWen.foreach(_ := deqEntryVec(i).bits.payload.vecWen)
731    deq.bits.common.v0Wen.foreach(_ := deqEntryVec(i).bits.payload.v0Wen)
732    deq.bits.common.vlWen.foreach(_ := deqEntryVec(i).bits.payload.vlWen)
733    deq.bits.common.flushPipe.foreach(_ := deqEntryVec(i).bits.payload.flushPipe)
734    deq.bits.common.pdest := deqEntryVec(i).bits.payload.pdest
735    deq.bits.common.robIdx := deqEntryVec(i).bits.status.robIdx
736
737    require(deq.bits.common.dataSources.size <= finalDataSources(i).size)
738    deq.bits.common.dataSources.zip(finalDataSources(i)).foreach { case (sink, source) => sink := source}
739    deq.bits.common.l1ExuOH.foreach(_.zip(finalWakeUpL1ExuOH.get(i)).foreach { case (sink, source) => sink := source})
740    deq.bits.common.srcTimer.foreach(_ := DontCare)
741    deq.bits.common.loadDependency.foreach(_.zip(finalLoadDependency(i)).foreach { case (sink, source) => sink := source})
742    deq.bits.common.src := DontCare
743    deq.bits.common.preDecode.foreach(_ := deqEntryVec(i).bits.payload.preDecodeInfo)
744
745    deq.bits.rf.zip(deqEntryVec(i).bits.status.srcStatus.map(_.psrc)).zip(deqEntryVec(i).bits.status.srcStatus.map(_.srcType)).foreach { case ((rf, psrc), srcType) =>
746      // psrc in status array can be pregIdx of IntRegFile or VfRegFile
747      rf.foreach(_.addr := psrc)
748      rf.foreach(_.srcType := srcType)
749    }
750    deq.bits.srcType.zip(deqEntryVec(i).bits.status.srcStatus.map(_.srcType)).foreach { case (sink, source) =>
751      sink := source
752    }
753    deq.bits.immType := deqEntryVec(i).bits.payload.selImm
754    deq.bits.common.imm := deqEntryVec(i).bits.imm.getOrElse(0.U)
755
756    deq.bits.common.perfDebugInfo := deqEntryVec(i).bits.payload.debugInfo
757    deq.bits.common.perfDebugInfo.selectTime := GTimer()
758    deq.bits.common.perfDebugInfo.issueTime := GTimer() + 1.U
759  }
760
761  io.deqDelay.zip(deqBeforeDly).foreach { case (deqDly, deq) =>
762    NewPipelineConnect(
763      deq, deqDly, deqDly.valid,
764      false.B,
765      Option("Scheduler2DataPathPipe")
766    )
767  }
768  if(backendParams.debugEn) {
769    dontTouch(io.deqDelay)
770  }
771  io.wakeupToIQ.zipWithIndex.foreach { case (wakeup, i) =>
772    if (wakeUpQueues(i).nonEmpty && finalWakeUpL1ExuOH.nonEmpty) {
773      wakeup.valid := wakeUpQueues(i).get.io.deq.valid
774      wakeup.bits.fromExuInput(wakeUpQueues(i).get.io.deq.bits, finalWakeUpL1ExuOH.get(i))
775      wakeup.bits.loadDependency := wakeUpQueues(i).get.io.deq.bits.loadDependency.getOrElse(0.U.asTypeOf(wakeup.bits.loadDependency))
776      wakeup.bits.is0Lat := getDeqLat(i, wakeUpQueues(i).get.io.deq.bits.fuType) === 0.U
777    } else if (wakeUpQueues(i).nonEmpty) {
778      wakeup.valid := wakeUpQueues(i).get.io.deq.valid
779      wakeup.bits.fromExuInput(wakeUpQueues(i).get.io.deq.bits)
780      wakeup.bits.loadDependency := wakeUpQueues(i).get.io.deq.bits.loadDependency.getOrElse(0.U.asTypeOf(wakeup.bits.loadDependency))
781      wakeup.bits.is0Lat := getDeqLat(i, wakeUpQueues(i).get.io.deq.bits.fuType) === 0.U
782    } else {
783      wakeup.valid := false.B
784      wakeup.bits := 0.U.asTypeOf(wakeup.bits)
785      wakeup.bits.is0Lat :=  0.U
786    }
787    if (wakeUpQueues(i).nonEmpty) {
788      wakeup.bits.rfWen  := (if (wakeUpQueues(i).get.io.deq.bits.rfWen .nonEmpty) wakeUpQueues(i).get.io.deq.valid && wakeUpQueues(i).get.io.deq.bits.rfWen .get else false.B)
789      wakeup.bits.fpWen  := (if (wakeUpQueues(i).get.io.deq.bits.fpWen .nonEmpty) wakeUpQueues(i).get.io.deq.valid && wakeUpQueues(i).get.io.deq.bits.fpWen .get else false.B)
790      wakeup.bits.vecWen := (if (wakeUpQueues(i).get.io.deq.bits.vecWen.nonEmpty) wakeUpQueues(i).get.io.deq.valid && wakeUpQueues(i).get.io.deq.bits.vecWen.get else false.B)
791      wakeup.bits.v0Wen  := (if (wakeUpQueues(i).get.io.deq.bits.v0Wen .nonEmpty) wakeUpQueues(i).get.io.deq.valid && wakeUpQueues(i).get.io.deq.bits.v0Wen.get else false.B)
792      wakeup.bits.vlWen  := (if (wakeUpQueues(i).get.io.deq.bits.vlWen .nonEmpty) wakeUpQueues(i).get.io.deq.valid && wakeUpQueues(i).get.io.deq.bits.vlWen.get else false.B)
793    }
794
795    if(wakeUpQueues(i).nonEmpty && wakeup.bits.pdestCopy.nonEmpty){
796      wakeup.bits.pdestCopy.get := wakeUpQueues(i).get.io.deq.bits.pdestCopy.get
797    }
798    if (wakeUpQueues(i).nonEmpty && wakeup.bits.rfWenCopy.nonEmpty) {
799      wakeup.bits.rfWenCopy.get := wakeUpQueues(i).get.io.deq.bits.rfWenCopy.get
800    }
801    if (wakeUpQueues(i).nonEmpty && wakeup.bits.fpWenCopy.nonEmpty) {
802      wakeup.bits.fpWenCopy.get := wakeUpQueues(i).get.io.deq.bits.fpWenCopy.get
803    }
804    if (wakeUpQueues(i).nonEmpty && wakeup.bits.vecWenCopy.nonEmpty) {
805      wakeup.bits.vecWenCopy.get := wakeUpQueues(i).get.io.deq.bits.vecWenCopy.get
806    }
807    if (wakeUpQueues(i).nonEmpty && wakeup.bits.v0WenCopy.nonEmpty) {
808      wakeup.bits.v0WenCopy.get := wakeUpQueues(i).get.io.deq.bits.v0WenCopy.get
809    }
810    if (wakeUpQueues(i).nonEmpty && wakeup.bits.vlWenCopy.nonEmpty) {
811      wakeup.bits.vlWenCopy.get := wakeUpQueues(i).get.io.deq.bits.vlWenCopy.get
812    }
813    if (wakeUpQueues(i).nonEmpty && wakeup.bits.loadDependencyCopy.nonEmpty) {
814      wakeup.bits.loadDependencyCopy.get := wakeUpQueues(i).get.io.deq.bits.loadDependencyCopy.get
815    }
816  }
817
818  // Todo: better counter implementation
819  private val enqHasValid = validVec.take(params.numEnq).reduce(_ | _)
820  private val enqEntryValidCnt = PopCount(validVec.take(params.numEnq))
821  private val othersValidCnt = PopCount(validVec.drop(params.numEnq))
822  private val enqEntryValidCntDeq0 = PopCount(
823    validVec.take(params.numEnq).zip(deqCanAcceptVec(0).take(params.numEnq)).map { case (a, b) => a && b }
824  )
825  private val othersValidCntDeq0 = PopCount(
826    validVec.drop(params.numEnq).zip(deqCanAcceptVec(0).drop(params.numEnq)).map { case (a, b) => a && b }
827  )
828  private val enqEntryValidCntDeq1 = PopCount(
829    validVec.take(params.numEnq).zip(deqCanAcceptVec.last.take(params.numEnq)).map { case (a, b) => a && b }
830  )
831  private val othersValidCntDeq1 = PopCount(
832    validVec.drop(params.numEnq).zip(deqCanAcceptVec.last.drop(params.numEnq)).map { case (a, b) => a && b }
833  )
834  protected val deqCanAcceptVecEnq: Seq[IndexedSeq[Bool]] = deqFuCfgs.map { fuCfgs: Seq[FuConfig] =>
835    io.enq.map(_.bits.fuType).map(fuType =>
836      FuType.FuTypeOrR(fuType, fuCfgs.map(_.fuType)))
837  }
838  protected val enqValidCntDeq0 = PopCount(io.enq.map(_.fire).zip(deqCanAcceptVecEnq(0)).map { case (a, b) => a && b })
839  protected val enqValidCntDeq1 = PopCount(io.enq.map(_.fire).zip(deqCanAcceptVecEnq.last).map { case (a, b) => a && b })
840  io.validCntDeqVec.head := RegNext(enqEntryValidCntDeq0 +& othersValidCntDeq0 - io.deqDelay.head.fire) // validCntDeqVec(0)
841  io.validCntDeqVec.last := RegNext(enqEntryValidCntDeq1 +& othersValidCntDeq1 - io.deqDelay.last.fire) // validCntDeqVec(1)
842  io.status.leftVec(0) := validVec.drop(params.numEnq).reduce(_ & _)
843  for (i <- 0 until params.numEnq) {
844    io.status.leftVec(i + 1) := othersValidCnt === (params.numEntries - params.numEnq - (i + 1)).U
845  }
846  private val othersLeftOneCaseVec = Wire(Vec(params.numEntries - params.numEnq, UInt((params.numEntries - params.numEnq).W)))
847  othersLeftOneCaseVec.zipWithIndex.foreach { case (leftone, i) =>
848    leftone := ~(1.U((params.numEntries - params.numEnq).W) << i)
849  }
850  private val othersLeftOne = othersLeftOneCaseVec.map(_ === VecInit(validVec.drop(params.numEnq)).asUInt).reduce(_ | _)
851  private val othersCanotIn = othersLeftOne || validVec.drop(params.numEnq).reduce(_ & _)
852
853  io.enq.foreach(_.ready := !othersCanotIn || !enqHasValid)
854  io.status.empty := !Cat(validVec).orR
855  io.status.full := othersCanotIn
856  io.status.validCnt := PopCount(validVec)
857
858  protected def getDeqLat(deqPortIdx: Int, fuType: UInt) : UInt = {
859    Mux1H(wakeupFuLatencyMaps(deqPortIdx) map { case (k, v) => (fuType(k.id), v.U) })
860  }
861
862  // issue perf counter
863  // enq count
864  XSPerfAccumulate("enq_valid_cnt", PopCount(io.enq.map(_.fire)))
865  XSPerfAccumulate("enq_fire_cnt", PopCount(io.enq.map(_.fire)))
866  XSPerfAccumulate("enq_alu_fire_cnt", PopCount(io.enq.map { case enq => enq.fire && FuType.isAlu(enq.bits.fuType) }))
867  XSPerfAccumulate("enq_brh_fire_cnt", PopCount(io.enq.map { case enq => enq.fire && FuType.isBrh(enq.bits.fuType) }))
868  XSPerfAccumulate("deqDelay0_fire_cnt", PopCount(io.deqDelay.head.fire))
869  XSPerfAccumulate("deqDelay1_fire_cnt", PopCount(io.deqDelay.last.fire))
870  // valid count
871  XSPerfHistogram("enq_entry_valid_cnt", enqEntryValidCnt, true.B, 0, params.numEnq + 1)
872  XSPerfHistogram("other_entry_valid_cnt", othersValidCnt, true.B, 0, params.numEntries - params.numEnq + 1)
873  XSPerfHistogram("valid_cnt", PopCount(validVec), true.B, 0, params.numEntries + 1)
874  // only split when more than 1 func type
875  if (params.getFuCfgs.size > 0) {
876    for (t <- FuType.functionNameMap.keys) {
877      val fuName = FuType.functionNameMap(t)
878      if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _)) {
879        XSPerfHistogram(s"valid_cnt_hist_futype_${fuName}", PopCount(validVec.zip(fuTypeVec).map { case (v, fu) => v && fu === t.U }), true.B, 0, params.numEntries, 1)
880      }
881    }
882  }
883  // ready instr count
884  private val readyEntriesCnt = PopCount(validVec.zip(canIssueVec).map(x => x._1 && x._2))
885  XSPerfHistogram("ready_cnt", readyEntriesCnt, true.B, 0, params.numEntries + 1)
886  // only split when more than 1 func type
887  if (params.getFuCfgs.size > 0) {
888    for (t <- FuType.functionNameMap.keys) {
889      val fuName = FuType.functionNameMap(t)
890      if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _)) {
891        XSPerfHistogram(s"ready_cnt_hist_futype_${fuName}", PopCount(validVec.zip(canIssueVec).zip(fuTypeVec).map { case ((v, c), fu) => v && c && fu === t.U }), true.B, 0, params.numEntries, 1)
892      }
893    }
894  }
895
896  // deq instr count
897  XSPerfAccumulate("issue_instr_pre_count", PopCount(deqBeforeDly.map(_.valid)))
898  XSPerfHistogram("issue_instr_pre_count_hist", PopCount(deqBeforeDly.map(_.valid)), true.B, 0, params.numDeq + 1, 1)
899  XSPerfAccumulate("issue_instr_count", PopCount(io.deqDelay.map(_.valid)))
900  XSPerfHistogram("issue_instr_count_hist", PopCount(io.deqDelay.map(_.valid)), true.B, 0, params.numDeq + 1, 1)
901
902  // deq instr data source count
903  XSPerfAccumulate("issue_datasource_reg", deqBeforeDly.map{ deq =>
904    PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) })
905  }.reduce(_ +& _))
906  XSPerfAccumulate("issue_datasource_bypass", deqBeforeDly.map{ deq =>
907    PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) })
908  }.reduce(_ +& _))
909  XSPerfAccumulate("issue_datasource_forward", deqBeforeDly.map{ deq =>
910    PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) })
911  }.reduce(_ +& _))
912  XSPerfAccumulate("issue_datasource_noreg", deqBeforeDly.map{ deq =>
913    PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) })
914  }.reduce(_ +& _))
915
916  XSPerfHistogram("issue_datasource_reg_hist", deqBeforeDly.map{ deq =>
917    PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) })
918  }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1)
919  XSPerfHistogram("issue_datasource_bypass_hist", deqBeforeDly.map{ deq =>
920    PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) })
921  }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1)
922  XSPerfHistogram("issue_datasource_forward_hist", deqBeforeDly.map{ deq =>
923    PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) })
924  }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1)
925  XSPerfHistogram("issue_datasource_noreg_hist", deqBeforeDly.map{ deq =>
926    PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) })
927  }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1)
928
929  // deq instr data source count for each futype
930  for (t <- FuType.functionNameMap.keys) {
931    val fuName = FuType.functionNameMap(t)
932    if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _)) {
933      XSPerfAccumulate(s"issue_datasource_reg_futype_${fuName}", deqBeforeDly.map{ deq =>
934        PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U })
935      }.reduce(_ +& _))
936      XSPerfAccumulate(s"issue_datasource_bypass_futype_${fuName}", deqBeforeDly.map{ deq =>
937        PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U })
938      }.reduce(_ +& _))
939      XSPerfAccumulate(s"issue_datasource_forward_futype_${fuName}", deqBeforeDly.map{ deq =>
940        PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U })
941      }.reduce(_ +& _))
942      XSPerfAccumulate(s"issue_datasource_noreg_futype_${fuName}", deqBeforeDly.map{ deq =>
943        PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U })
944      }.reduce(_ +& _))
945
946      XSPerfHistogram(s"issue_datasource_reg_hist_futype_${fuName}", deqBeforeDly.map{ deq =>
947        PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.reg && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U })
948      }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1)
949      XSPerfHistogram(s"issue_datasource_bypass_hist_futype_${fuName}", deqBeforeDly.map{ deq =>
950        PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.bypass && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U })
951      }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1)
952      XSPerfHistogram(s"issue_datasource_forward_hist_futype_${fuName}", deqBeforeDly.map{ deq =>
953        PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && ds.value === DataSource.forward && !SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U })
954      }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1)
955      XSPerfHistogram(s"issue_datasource_noreg_hist_futype_${fuName}", deqBeforeDly.map{ deq =>
956        PopCount(deq.bits.common.dataSources.zipWithIndex.map{ case (ds, j) => deq.valid && SrcType.isNotReg(deq.bits.srcType(j)) && deq.bits.common.fuType === t.U })
957      }.reduce(_ +& _), true.B, 0, params.numDeq * params.numRegSrc + 1, 1)
958    }
959  }
960}
961
962class IssueQueueLoadBundle(implicit p: Parameters) extends XSBundle {
963  val fastMatch = UInt(backendParams.LduCnt.W)
964  val fastImm = UInt(12.W)
965}
966
967class IssueQueueIntIO()(implicit p: Parameters, params: IssueBlockParams) extends IssueQueueIO
968
969class IssueQueueIntImp(override val wrapper: IssueQueue)(implicit p: Parameters, iqParams: IssueBlockParams)
970  extends IssueQueueImp(wrapper)
971{
972  io.suggestName("none")
973  override lazy val io = IO(new IssueQueueIntIO).suggestName("io")
974
975  deqBeforeDly.zipWithIndex.foreach{ case (deq, i) => {
976    deq.bits.common.pc.foreach(_ := DontCare)
977    deq.bits.common.preDecode.foreach(_ := deqEntryVec(i).bits.payload.preDecodeInfo)
978    deq.bits.common.ftqIdx.foreach(_ := deqEntryVec(i).bits.payload.ftqPtr)
979    deq.bits.common.ftqOffset.foreach(_ := deqEntryVec(i).bits.payload.ftqOffset)
980    deq.bits.common.predictInfo.foreach(x => {
981      x.target := DontCare
982      x.taken := deqEntryVec(i).bits.payload.pred_taken
983    })
984    // for std
985    deq.bits.common.sqIdx.foreach(_ := deqEntryVec(i).bits.payload.sqIdx)
986    // for i2f
987    deq.bits.common.fpu.foreach(_ := deqEntryVec(i).bits.payload.fpu)
988  }}
989}
990
991class IssueQueueVfImp(override val wrapper: IssueQueue)(implicit p: Parameters, iqParams: IssueBlockParams)
992  extends IssueQueueImp(wrapper)
993{
994  deqBeforeDly.zipWithIndex.foreach{ case (deq, i) => {
995    deq.bits.common.fpu.foreach(_ := deqEntryVec(i).bits.payload.fpu)
996    deq.bits.common.vpu.foreach(_ := deqEntryVec(i).bits.payload.vpu)
997    deq.bits.common.vpu.foreach(_.vuopIdx := deqEntryVec(i).bits.payload.uopIdx)
998    deq.bits.common.vpu.foreach(_.lastUop := deqEntryVec(i).bits.payload.lastUop)
999  }}
1000}
1001
1002class IssueQueueFpImp(override val wrapper: IssueQueue)(implicit p: Parameters, iqParams: IssueBlockParams)
1003  extends IssueQueueImp(wrapper)
1004{
1005  deqBeforeDly.zipWithIndex.foreach{ case (deq, i) => {
1006    deq.bits.common.fpu.foreach(_ := deqEntryVec(i).bits.payload.fpu)
1007    deq.bits.common.vpu.foreach(_ := deqEntryVec(i).bits.payload.vpu)
1008    deq.bits.common.vpu.foreach(_.vuopIdx := deqEntryVec(i).bits.payload.uopIdx)
1009    deq.bits.common.vpu.foreach(_.lastUop := deqEntryVec(i).bits.payload.lastUop)
1010  }}
1011}
1012
1013class IssueQueueMemBundle(implicit p: Parameters, params: IssueBlockParams) extends Bundle {
1014  val feedbackIO = Flipped(Vec(params.numDeq, new MemRSFeedbackIO(params.isVecMemIQ)))
1015
1016  // TODO: is still needed?
1017  val checkWait = new Bundle {
1018    val stIssuePtr = Input(new SqPtr)
1019    val memWaitUpdateReq = Flipped(new MemWaitUpdateReq)
1020  }
1021  val loadFastMatch = Output(Vec(params.LdExuCnt, new IssueQueueLoadBundle))
1022
1023  // load wakeup
1024  val loadWakeUp = Input(Vec(params.LdExuCnt, ValidIO(new DynInst())))
1025
1026  // vector
1027  val sqDeqPtr = OptionWrapper(params.isVecMemIQ, Input(new SqPtr))
1028  val lqDeqPtr = OptionWrapper(params.isVecMemIQ, Input(new LqPtr))
1029}
1030
1031class IssueQueueMemIO(implicit p: Parameters, params: IssueBlockParams) extends IssueQueueIO {
1032  val memIO = Some(new IssueQueueMemBundle)
1033}
1034
1035class IssueQueueMemAddrImp(override val wrapper: IssueQueue)(implicit p: Parameters, params: IssueBlockParams)
1036  extends IssueQueueImp(wrapper) with HasCircularQueuePtrHelper {
1037
1038  require(params.StdCnt == 0 && (params.LduCnt + params.StaCnt + params.HyuCnt) > 0, "IssueQueueMemAddrImp can only be instance of MemAddr IQ, " +
1039    s"StdCnt: ${params.StdCnt}, LduCnt: ${params.LduCnt}, StaCnt: ${params.StaCnt}, HyuCnt: ${params.HyuCnt}")
1040  println(s"[IssueQueueMemAddrImp] StdCnt: ${params.StdCnt}, LduCnt: ${params.LduCnt}, StaCnt: ${params.StaCnt}, HyuCnt: ${params.HyuCnt}")
1041
1042  io.suggestName("none")
1043  override lazy val io = IO(new IssueQueueMemIO).suggestName("io")
1044  private val memIO = io.memIO.get
1045
1046  memIO.loadFastMatch := 0.U.asTypeOf(memIO.loadFastMatch) // TODO: is still needed?
1047
1048  entries.io.fromMem.get.slowResp.zipWithIndex.foreach { case (slowResp, i) =>
1049    slowResp.valid       := memIO.feedbackIO(i).feedbackSlow.valid
1050    slowResp.bits.robIdx := memIO.feedbackIO(i).feedbackSlow.bits.robIdx
1051    slowResp.bits.resp   := Mux(memIO.feedbackIO(i).feedbackSlow.bits.hit, RespType.success, RespType.block)
1052    slowResp.bits.fuType := DontCare
1053  }
1054
1055  entries.io.fromMem.get.fastResp.zipWithIndex.foreach { case (fastResp, i) =>
1056    fastResp.valid       := memIO.feedbackIO(i).feedbackFast.valid
1057    fastResp.bits.robIdx := memIO.feedbackIO(i).feedbackFast.bits.robIdx
1058    fastResp.bits.resp   := Mux(memIO.feedbackIO(i).feedbackFast.bits.hit, RespType.success, RespType.block)
1059    fastResp.bits.fuType := DontCare
1060  }
1061
1062  // load wakeup
1063  val loadWakeUpIter = memIO.loadWakeUp.iterator
1064  io.wakeupToIQ.zip(params.exuBlockParams).zipWithIndex.foreach { case ((wakeup, param), i) =>
1065    if (param.hasLoadExu) {
1066      require(wakeUpQueues(i).isEmpty)
1067      val uop = loadWakeUpIter.next()
1068
1069      wakeup.valid := GatedValidRegNext(uop.fire)
1070      wakeup.bits.rfWen  := (if (params.writeIntRf) GatedValidRegNext(uop.bits.rfWen  && uop.fire) else false.B)
1071      wakeup.bits.fpWen  := (if (params.writeFpRf)  GatedValidRegNext(uop.bits.fpWen  && uop.fire) else false.B)
1072      wakeup.bits.vecWen := (if (params.writeVecRf) GatedValidRegNext(uop.bits.vecWen && uop.fire) else false.B)
1073      wakeup.bits.v0Wen  := (if (params.writeV0Rf)  GatedValidRegNext(uop.bits.v0Wen  && uop.fire) else false.B)
1074      wakeup.bits.vlWen  := (if (params.writeVlRf)  GatedValidRegNext(uop.bits.vlWen  && uop.fire) else false.B)
1075      wakeup.bits.pdest  := RegEnable(uop.bits.pdest, uop.fire)
1076      wakeup.bits.loadDependency.foreach(_ := 0.U) // this is correct for load only
1077
1078      wakeup.bits.rfWenCopy .foreach(_.foreach(_ := (if (params.writeIntRf) GatedValidRegNext(uop.bits.rfWen  && uop.fire) else false.B)))
1079      wakeup.bits.fpWenCopy .foreach(_.foreach(_ := (if (params.writeFpRf)  GatedValidRegNext(uop.bits.fpWen  && uop.fire) else false.B)))
1080      wakeup.bits.vecWenCopy.foreach(_.foreach(_ := (if (params.writeVecRf) GatedValidRegNext(uop.bits.vecWen && uop.fire) else false.B)))
1081      wakeup.bits.v0WenCopy .foreach(_.foreach(_ := (if (params.writeV0Rf)  GatedValidRegNext(uop.bits.v0Wen  && uop.fire) else false.B)))
1082      wakeup.bits.vlWenCopy .foreach(_.foreach(_ := (if (params.writeVlRf)  GatedValidRegNext(uop.bits.vlWen  && uop.fire) else false.B)))
1083      wakeup.bits.pdestCopy .foreach(_.foreach(_ := RegEnable(uop.bits.pdest, uop.fire)))
1084      wakeup.bits.loadDependencyCopy.foreach(x => x := 0.U.asTypeOf(x)) // this is correct for load only
1085
1086      wakeup.bits.is0Lat := 0.U
1087    }
1088  }
1089  require(!loadWakeUpIter.hasNext)
1090
1091  deqBeforeDly.zipWithIndex.foreach { case (deq, i) =>
1092    deq.bits.common.loadWaitBit.foreach(_ := deqEntryVec(i).bits.payload.loadWaitBit)
1093    deq.bits.common.waitForRobIdx.foreach(_ := deqEntryVec(i).bits.payload.waitForRobIdx)
1094    deq.bits.common.storeSetHit.foreach(_ := deqEntryVec(i).bits.payload.storeSetHit)
1095    deq.bits.common.loadWaitStrict.foreach(_ := deqEntryVec(i).bits.payload.loadWaitStrict)
1096    deq.bits.common.ssid.foreach(_ := deqEntryVec(i).bits.payload.ssid)
1097    deq.bits.common.sqIdx.get := deqEntryVec(i).bits.payload.sqIdx
1098    deq.bits.common.lqIdx.get := deqEntryVec(i).bits.payload.lqIdx
1099    deq.bits.common.ftqIdx.foreach(_ := deqEntryVec(i).bits.payload.ftqPtr)
1100    deq.bits.common.ftqOffset.foreach(_ := deqEntryVec(i).bits.payload.ftqOffset)
1101  }
1102}
1103
1104class IssueQueueVecMemImp(override val wrapper: IssueQueue)(implicit p: Parameters, params: IssueBlockParams)
1105  extends IssueQueueImp(wrapper) with HasCircularQueuePtrHelper {
1106
1107  require((params.VlduCnt + params.VstuCnt) > 0, "IssueQueueVecMemImp can only be instance of VecMem IQ")
1108  println(s"[IssueQueueVecMemImp] VlduCnt: ${params.VlduCnt}, VstuCnt: ${params.VstuCnt}")
1109
1110  io.suggestName("none")
1111  override lazy val io = IO(new IssueQueueMemIO).suggestName("io")
1112  private val memIO = io.memIO.get
1113
1114  require(params.numExu == 1, "VecMem IssueQueue has not supported more than 1 deq ports")
1115
1116  for (i <- entries.io.enq.indices) {
1117    entries.io.enq(i).bits.status match { case enqData =>
1118      enqData.vecMem.get.sqIdx := s0_enqBits(i).sqIdx
1119      enqData.vecMem.get.lqIdx := s0_enqBits(i).lqIdx
1120      // MemAddrIQ also handle vector insts
1121      enqData.vecMem.get.numLsElem := s0_enqBits(i).numLsElem
1122      enqData.blocked          := false.B
1123    }
1124  }
1125
1126  entries.io.fromMem.get.slowResp.zipWithIndex.foreach { case (slowResp, i) =>
1127    slowResp.valid                 := memIO.feedbackIO(i).feedbackSlow.valid
1128    slowResp.bits.robIdx           := memIO.feedbackIO(i).feedbackSlow.bits.robIdx
1129    slowResp.bits.resp             := Mux(memIO.feedbackIO(i).feedbackSlow.bits.hit, RespType.success, RespType.block)
1130    slowResp.bits.fuType           := DontCare
1131    slowResp.bits.uopIdx.get       := memIO.feedbackIO(i).feedbackSlow.bits.uopIdx.get
1132  }
1133
1134  entries.io.fromMem.get.fastResp.zipWithIndex.foreach { case (fastResp, i) =>
1135    fastResp.valid                 := memIO.feedbackIO(i).feedbackFast.valid
1136    fastResp.bits.robIdx           := memIO.feedbackIO(i).feedbackFast.bits.robIdx
1137    fastResp.bits.resp             := Mux(memIO.feedbackIO(i).feedbackFast.bits.hit, RespType.success, RespType.block)
1138    fastResp.bits.fuType           := DontCare
1139    fastResp.bits.uopIdx.get       := memIO.feedbackIO(i).feedbackFast.bits.uopIdx.get
1140  }
1141
1142  entries.io.vecMemIn.get.sqDeqPtr := memIO.sqDeqPtr.get
1143  entries.io.vecMemIn.get.lqDeqPtr := memIO.lqDeqPtr.get
1144
1145  deqBeforeDly.zipWithIndex.foreach { case (deq, i) =>
1146    deq.bits.common.sqIdx.foreach(_ := deqEntryVec(i).bits.status.vecMem.get.sqIdx)
1147    deq.bits.common.lqIdx.foreach(_ := deqEntryVec(i).bits.status.vecMem.get.lqIdx)
1148    deq.bits.common.numLsElem.foreach(_ := deqEntryVec(i).bits.status.vecMem.get.numLsElem)
1149    if (params.isVecLduIQ) {
1150      deq.bits.common.ftqIdx.get := deqEntryVec(i).bits.payload.ftqPtr
1151      deq.bits.common.ftqOffset.get := deqEntryVec(i).bits.payload.ftqOffset
1152    }
1153    deq.bits.common.fpu.foreach(_ := deqEntryVec(i).bits.payload.fpu)
1154    deq.bits.common.vpu.foreach(_ := deqEntryVec(i).bits.payload.vpu)
1155    deq.bits.common.vpu.foreach(_.vuopIdx := deqEntryVec(i).bits.payload.uopIdx)
1156    deq.bits.common.vpu.foreach(_.lastUop := deqEntryVec(i).bits.payload.lastUop)
1157  }
1158
1159  io.vecLoadIssueResp.foreach(dontTouch(_))
1160}
1161