1package xiangshan.backend.issue 2 3import chisel3._ 4import chisel3.util._ 5import xiangshan._ 6import xiangshan.backend.rename.FreeListPtr 7import xiangshan.utils._ 8 9trait IQConst{ 10 val iqSize = 8 11 val iqIdxWidth = log2Up(iqSize) 12} 13 14sealed abstract class IQBundle extends XSBundle with IQConst 15sealed abstract class IQModule extends XSModule with IQConst //with NeedImpl 16 17sealed class CmpInputBundle extends IQBundle{ 18 val instRdy = Input(Bool()) 19 val roqIdx = Input(UInt(RoqIdxWidth.W)) 20 val iqIdx = Input(UInt(iqIdxWidth.W)) 21 22 def apply(instRdy: Bool,roqIdx: UInt,iqIdx: UInt ) = { 23 this.instRdy := instRdy 24 this.roqIdx := roqIdx 25 this.iqIdx := iqIdx 26 this 27 } 28} 29 30 31sealed class CompareCircuitUnit extends IQModule { 32 val io = IO(new Bundle(){ 33 val in1 = new CmpInputBundle 34 val in2 = new CmpInputBundle 35 val out = Flipped(new CmpInputBundle) 36 }) 37 38 val roqIdx1 = io.in1.roqIdx 39 val roqIdx2 = io.in2.roqIdx 40 val iqIdx1 = io.in1.iqIdx 41 val iqIdx2 = io.in2.iqIdx 42 43 val inst1Rdy = io.in1.instRdy 44 val inst2Rdy = io.in2.instRdy 45 46 io.out.instRdy := inst1Rdy | inst2Rdy 47 io.out.roqIdx := roqIdx2 48 io.out.iqIdx := iqIdx2 49 50 when((inst1Rdy && !inst2Rdy) || (inst1Rdy && inst2Rdy && (roqIdx1 < roqIdx2))){ 51 io.out.roqIdx := roqIdx1 52 io.out.iqIdx := iqIdx1 53 } 54 55} 56 57object CCU{ 58 def apply(in1: CmpInputBundle, in2: CmpInputBundle) = { 59 val CCU = Module(new CompareCircuitUnit) 60 CCU.io.in1 <> in1 61 CCU.io.in2 <> in2 62 CCU.io.out 63 } 64} 65 66object ParallelSel { 67 def apply(iq: Seq[CmpInputBundle]): CmpInputBundle = { 68 iq match { 69 case Seq(a) => a 70 case Seq(a, b) => CCU(a, b) 71 case _ => 72 apply(Seq(apply(iq take iq.size/2), apply(iq drop iq.size/2))) 73 } 74 } 75} 76 77class IssueQueue(val fuTypeInt: BigInt, val wakeupCnt: Int, val bypassCnt: Int = 0, val fixedDelay: Int = 1) extends IQModule { 78 79 val useBypass = bypassCnt > 0 80 81 val io = IO(new Bundle() { 82 // flush Issue Queue 83 val redirect = Flipped(ValidIO(new Redirect)) 84 85 // enq Ctrl sigs at dispatch-2 86 val enqCtrl = Flipped(DecoupledIO(new MicroOp)) 87 // enq Data at next cycle (regfile has 1 cycle latency) 88 val enqData = Flipped(ValidIO(new ExuInput)) 89 90 // broadcast selected uop to other issue queues which has bypasses 91 val selectedUop = if(useBypass) ValidIO(new MicroOp) else null 92 93 // send to exu 94 val deq = DecoupledIO(new ExuInput) 95 96 // listen to write back bus 97 val wakeUpPorts = Vec(wakeupCnt, Flipped(ValidIO(new ExuOutput))) 98 99 // use bypass uops to speculative wake-up 100 val bypassUops = if(useBypass) Vec(bypassCnt, Flipped(ValidIO(new MicroOp))) else null 101 val bypassData = if(useBypass) Vec(bypassCnt, Flipped(ValidIO(new ExuOutput))) else null 102 }) 103 //--------------------------------------------------------- 104 // Issue Queue 105 //--------------------------------------------------------- 106 107 //Tag Queue 108 val ctrlFlow = Mem(iqSize,new CtrlFlow) 109 val ctrlSig = Mem(iqSize,new CtrlSignals) 110 val brMask = Reg(Vec(iqSize, UInt(BrqSize.W))) 111 val brTag = Reg(Vec(iqSize, UInt(BrTagWidth.W))) 112 val validReg = RegInit(VecInit(Seq.fill(iqSize)(false.B))) 113 val validWillFalse= WireInit(VecInit(Seq.fill(iqSize)(false.B))) 114 val valid = validReg.asUInt & ~validWillFalse.asUInt 115 val src1Rdy = Reg(Vec(iqSize, Bool())) 116 val src2Rdy = Reg(Vec(iqSize, Bool())) 117 val src3Rdy = Reg(Vec(iqSize, Bool())) 118 val prfSrc1 = Reg(Vec(iqSize, UInt(PhyRegIdxWidth.W))) 119 val prfSrc2 = Reg(Vec(iqSize, UInt(PhyRegIdxWidth.W))) 120 val prfSrc3 = Reg(Vec(iqSize, UInt(PhyRegIdxWidth.W))) 121 val prfDest = Reg(Vec(iqSize, UInt(PhyRegIdxWidth.W))) 122 val oldPDest = Reg(Vec(iqSize, UInt(PhyRegIdxWidth.W))) 123 val freelistAllocPtr = Reg(Vec(iqSize, new FreeListPtr)) 124 val roqIdx = Reg(Vec(iqSize, UInt(RoqIdxWidth.W))) 125 126 val instRdy = WireInit(VecInit(List.tabulate(iqSize)(i => src1Rdy(i) && src2Rdy(i) && src3Rdy(i)&& valid(i)))) 127 128 129 //tag enqueue 130 val iqEmty = !valid.asUInt.orR 131 val iqFull = valid.asUInt.andR 132 val iqAllowIn = !iqFull 133 io.enqCtrl.ready := iqAllowIn 134 135 //enqueue pointer 136 val emptySlot = ~valid.asUInt 137 val enqueueSelect = PriorityEncoder(emptySlot) 138 //assert(!(io.enqCtrl.valid && io.redirect.valid),"enqueue valid should be false when redirect valid") 139 XSError(io.enqCtrl.valid && io.redirect.valid,"enqueue valid should be false when redirect valid") 140 val srcEnqRdy = WireInit(VecInit(false.B, false.B, false.B)) 141 142 srcEnqRdy(0) := Mux(io.enqCtrl.bits.ctrl.src1Type =/= SrcType.reg , true.B ,io.enqCtrl.bits.src1State === SrcState.rdy) 143 srcEnqRdy(1) := Mux(io.enqCtrl.bits.ctrl.src2Type =/= SrcType.reg , true.B ,io.enqCtrl.bits.src2State === SrcState.rdy) 144 //TODO: 145 if(fuTypeInt != FuType.fmac.litValue()){ srcEnqRdy(2) := true.B} 146 else{srcEnqRdy(2) := Mux(io.enqCtrl.bits.ctrl.src3Type =/= SrcType.reg , true.B ,io.enqCtrl.bits.src3State === SrcState.rdy)} 147 148 when (io.enqCtrl.fire()) { 149 ctrlFlow(enqueueSelect) := io.enqCtrl.bits.cf 150 ctrlSig(enqueueSelect) := io.enqCtrl.bits.ctrl 151 brMask(enqueueSelect) := io.enqCtrl.bits.brMask 152 brTag(enqueueSelect) := io.enqCtrl.bits.brTag 153 validReg(enqueueSelect) := true.B 154 src1Rdy(enqueueSelect) := srcEnqRdy(0) 155 src2Rdy(enqueueSelect) := srcEnqRdy(1) 156 src3Rdy(enqueueSelect) := srcEnqRdy(2) 157 prfSrc1(enqueueSelect) := io.enqCtrl.bits.psrc1 158 prfSrc2(enqueueSelect) := io.enqCtrl.bits.psrc2 159 prfSrc3(enqueueSelect) := io.enqCtrl.bits.psrc3 160 prfDest(enqueueSelect) := io.enqCtrl.bits.pdest 161 oldPDest(enqueueSelect) := io.enqCtrl.bits.old_pdest 162 freelistAllocPtr(enqueueSelect) := io.enqCtrl.bits.freelistAllocPtr 163 roqIdx(enqueueSelect) := io.enqCtrl.bits.roqIdx 164 XSDebug("[IQ enq]: enqSelect:%d | s1Rd:%d s2Rd:%d s3Rd:%d\n",enqueueSelect.asUInt, 165 (io.enqCtrl.bits.src1State === SrcState.rdy), 166 (io.enqCtrl.bits.src2State === SrcState.rdy), 167 (io.enqCtrl.bits.src3State === SrcState.rdy)) 168 169 } 170 171 //Data Queue 172 val src1Data = Reg(Vec(iqSize, UInt(XLEN.W))) 173 val src2Data = Reg(Vec(iqSize, UInt(XLEN.W))) 174 val src3Data = Reg(Vec(iqSize, UInt(XLEN.W))) 175 176 177 val enqSelNext = RegNext(enqueueSelect) 178 val enqFireNext = RegNext(io.enqCtrl.fire()) 179 180 // Read RegFile 181 //Ready data will written at next cycle 182 when (enqFireNext) { 183 when(src1Rdy(enqSelNext)){src1Data(enqSelNext) := io.enqData.bits.src1} 184 when(src2Rdy(enqSelNext)){src2Data(enqSelNext) := io.enqData.bits.src2} 185 when(src3Rdy(enqSelNext)){src3Data(enqSelNext) := io.enqData.bits.src3} 186 } 187 188 189 XSDebug("[Reg info-ENQ] enqSelNext:%d | enqFireNext:%d \n",enqSelNext,enqFireNext) 190 XSDebug("[IQ content] valid vr vf| pc insruction | src1rdy src1 | src2Rdy src2 | src3Rdy src3 | pdest \n") 191 for(i <- 0 to (iqSize -1)) { 192 val ins = ctrlFlow(i).instr 193 val pc = ctrlFlow(i).pc 194 XSDebug(valid(i), 195 "[IQ content][%d] %d%d%d |%x %x| %x %x | %x %x | %x %x | %d valid|\n", 196 i.asUInt, valid(i), validReg(i), validWillFalse(i), pc,ins,src1Rdy(i), src1Data(i), 197 src2Rdy(i), src2Data(i),src3Rdy(i), src3Data(i),prfDest(i)) 198 XSDebug(validReg(i) && validWillFalse(i), 199 "[IQ content][%d] %d%d%d |%x %x| %x %x | %x %x | %x %x | %d valid will be False|\n", 200 i.asUInt, valid(i), validReg(i), validWillFalse(i),pc,ins, src1Rdy(i), src1Data(i), 201 src2Rdy(i), src2Data(i),src3Rdy(i), src3Data(i),prfDest(i)) 202 XSDebug("[IQ content][%d] %d%d%d |%x %x| %x %x | %x %x | %x %x | %d\n", 203 i.asUInt, valid(i), validReg(i), validWillFalse(i),pc,ins, src1Rdy(i), src1Data(i), 204 src2Rdy(i), src2Data(i),src3Rdy(i), src3Data(i),prfDest(i)) 205 } 206 // From Common Data Bus(wakeUpPort) 207 // chisel claims that firrtl will optimize Mux1H to and/or tree 208 // TODO: ignore ALU'cdb srcRdy, for byPass has done it 209 if(wakeupCnt > 0) { 210 val cdbValid = List.tabulate(wakeupCnt)(i => io.wakeUpPorts(i).valid) 211 val cdbData = List.tabulate(wakeupCnt)(i => io.wakeUpPorts(i).bits.data) 212 val cdbPdest = List.tabulate(wakeupCnt)(i => io.wakeUpPorts(i).bits.uop.pdest) 213 214 val srcNum = 3 215 val prfSrc = List(prfSrc1, prfSrc2, prfSrc3) 216 val srcRdy = List(src1Rdy, src2Rdy, src3Rdy) 217 val srcData = List(src1Data, src2Data, src3Data) 218 val srcHitVec = List.tabulate(srcNum)(k => 219 List.tabulate(iqSize)(i => 220 List.tabulate(wakeupCnt)(j => 221 (prfSrc(k)(i) === cdbPdest(j)) && cdbValid(j)))) 222 val srcHit = List.tabulate(srcNum)(k => 223 List.tabulate(iqSize)(i => 224 ParallelOR(srcHitVec(k)(i)).asBool())) 225 // VecInit(srcHitVec(k)(i)).asUInt.orR)) 226 for(k <- 0 until srcNum){ 227 for(i <- 0 until iqSize)( when (valid(i)) { 228 when(!srcRdy(k)(i) && srcHit(k)(i)) { 229 srcRdy(k)(i) := true.B 230 // srcData(k)(i) := Mux1H(srcHitVec(k)(i), cdbData) 231 srcData(k)(i) := ParallelMux(srcHitVec(k)(i) zip cdbData) 232 } 233 }) 234 } 235 // From byPass [speculative] (just for ALU to listen to other ALU's res, include itself) 236 // just need Tag(Ctrl). send out Tag when Tag is decided. other ALUIQ listen to them and decide Tag 237 // byPassUops is one cycle before byPassDatas 238 if (bypassCnt > 0) { 239 val bypassPdest = List.tabulate(bypassCnt)(i => io.bypassUops(i).bits.pdest) 240 val bypassValid = List.tabulate(bypassCnt)(i => io.bypassUops(i).valid) // may only need valid not fire() 241 val bypassData = List.tabulate(bypassCnt)(i => io.bypassData(i).bits.data) 242 val srcBpHitVec = List.tabulate(srcNum)(k => 243 List.tabulate(iqSize)(i => 244 List.tabulate(bypassCnt)(j => 245 (prfSrc(k)(i) === bypassPdest(j)) && bypassValid(j)))) 246 val srcBpHit = List.tabulate(srcNum)(k => 247 List.tabulate(iqSize)(i => 248 ParallelOR(srcBpHitVec(k)(i)).asBool())) 249 // VecInit(srcBpHitVec(k)(i)).asUInt.orR)) 250 val srcBpHitVecNext = List.tabulate(srcNum)(k => 251 List.tabulate(iqSize)(i => 252 List.tabulate(bypassCnt)(j => RegNext(srcBpHitVec(k)(i)(j))))) 253 val srcBpHitNext = List.tabulate(srcNum)(k => 254 List.tabulate(iqSize)(i => 255 RegNext(srcBpHit(k)(i)))) 256 val srcBpData = List.tabulate(srcNum)(k => 257 List.tabulate(iqSize)(i => 258 ParallelMux(srcBpHitVecNext(k)(i) zip bypassData))) 259 // Mux1H(srcBpHitVecNext(k)(i), bypassData))) 260 for(k <- 0 until srcNum){ 261 for(i <- 0 until iqSize){ when (valid(i)) { 262 when(valid(i) && !srcRdy(k)(i) && srcBpHit(k)(i)) { srcRdy(k)(i) := true.B } 263 when(srcBpHitNext(k)(i)) { srcData(k)(i) := srcBpData(k)(i)} 264 }} 265 } 266 267 // Enqueue Bypass 268 val enqBypass = WireInit(VecInit(false.B, false.B, false.B)) 269 val enqBypassHitVec = List(List.tabulate(bypassCnt)(j => io.enqCtrl.bits.psrc1 === bypassPdest(j) && bypassValid(j) && io.enqCtrl.fire()), 270 List.tabulate(bypassCnt)(j => io.enqCtrl.bits.psrc2 === bypassPdest(j) && bypassValid(j) && io.enqCtrl.fire()), 271 List.tabulate(bypassCnt)(j => io.enqCtrl.bits.psrc3 === bypassPdest(j) && bypassValid(j) && io.enqCtrl.fire())) 272 val enqBypassHitVecNext = enqBypassHitVec.map(i => i.map(j => RegNext(j))) 273 enqBypass(0) := ParallelOR(enqBypassHitVec(0)) 274 enqBypass(1) := ParallelOR(enqBypassHitVec(1)) 275 enqBypass(2) := ParallelOR(enqBypassHitVec(2)) 276 when(enqBypass(0)) { src1Rdy(enqueueSelect) := true.B } 277 when(enqBypass(1)) { src2Rdy(enqueueSelect) := true.B } 278 when(enqBypass(2)) { src3Rdy(enqueueSelect) := true.B } 279 when(RegNext(enqBypass(0))) { src1Data(enqSelNext) := ParallelMux(enqBypassHitVecNext(0) zip bypassData)} 280 when(RegNext(enqBypass(1))) { src2Data(enqSelNext) := ParallelMux(enqBypassHitVecNext(1) zip bypassData)} 281 when(RegNext(enqBypass(2))) { src3Data(enqSelNext) := ParallelMux(enqBypassHitVecNext(2) zip bypassData)} 282 } 283 284 } 285 286 287 //--------------------------------------------------------- 288 // Select Circuit 289 //--------------------------------------------------------- 290 val selVec = List.tabulate(iqSize){ i => 291 Wire(new CmpInputBundle).apply(instRdy(i),roqIdx(i),i.U) 292 } 293 val selResult = ParallelSel(selVec) 294 XSDebug("[Sel Result] ResReady:%d || ResultId:%d\n",selResult.instRdy,selResult.iqIdx.asUInt) 295 //--------------------------------------------------------- 296 // Redirect Logic 297 //--------------------------------------------------------- 298 val expRedirect = io.redirect.valid && io.redirect.bits.isException 299 val brRedirect = io.redirect.valid && !io.redirect.bits.isException 300 301 List.tabulate(iqSize)( i => 302 when(brRedirect && (UIntToOH(io.redirect.bits.brTag) & brMask(i)).orR && validReg(i) ){ 303 validReg(i) := false.B 304 validWillFalse(i) := true.B 305 306 } .elsewhen(expRedirect) { 307 validReg(i) := false.B 308 validWillFalse(i) := true.B 309 } 310 ) 311 //--------------------------------------------------------- 312 // Dequeue Logic 313 //--------------------------------------------------------- 314 //hold the sel-index to wait for data 315 val selInstIdx = RegInit(0.U(iqIdxWidth.W)) 316 val selInstRdy = RegInit(false.B) 317 318 //issue the select instruction 319 val dequeueSelect = Wire(UInt(iqIdxWidth.W)) 320 dequeueSelect := selInstIdx 321 322 val brRedirectMaskMatch = (UIntToOH(io.redirect.bits.brTag) & brMask(dequeueSelect)).orR 323 val IQreadyGo = selInstRdy && !expRedirect && (!brRedirect || !brRedirectMaskMatch) 324 325 io.deq.valid := IQreadyGo 326 327 io.deq.bits.uop.cf := ctrlFlow(dequeueSelect) 328 io.deq.bits.uop.ctrl := ctrlSig(dequeueSelect) 329 io.deq.bits.uop.brMask := brMask(dequeueSelect) 330 io.deq.bits.uop.brTag := brTag(dequeueSelect) 331 332 io.deq.bits.uop.psrc1 := prfSrc1(dequeueSelect) 333 io.deq.bits.uop.psrc2 := prfSrc2(dequeueSelect) 334 io.deq.bits.uop.psrc3 := prfSrc3(dequeueSelect) 335 io.deq.bits.uop.pdest := prfDest(dequeueSelect) 336 io.deq.bits.uop.old_pdest := oldPDest(dequeueSelect) 337 io.deq.bits.uop.src1State := SrcState.rdy 338 io.deq.bits.uop.src2State := SrcState.rdy 339 io.deq.bits.uop.src3State := SrcState.rdy 340 io.deq.bits.uop.freelistAllocPtr := freelistAllocPtr(dequeueSelect) 341 io.deq.bits.uop.roqIdx := roqIdx(dequeueSelect) 342 343 io.deq.bits.src1 := src1Data(dequeueSelect) 344 io.deq.bits.src2 := src2Data(dequeueSelect) 345 io.deq.bits.src3 := src3Data(dequeueSelect) 346 347 XSDebug("[Reg Info-Sel] selInstRdy:%d || selIdx:%d\n",selInstRdy,selInstIdx.asUInt) 348 XSDebug(IQreadyGo,"[IQ dequeue] **dequeue fire:%d** roqIdx:%d dequeueSel:%d | src1Rd:%d src1:%d | src2Rd:%d src2:%d\n", io.deq.fire(), io.deq.bits.uop.roqIdx, dequeueSelect.asUInt, 349 (io.deq.bits.uop.src1State === SrcState.rdy), io.deq.bits.uop.psrc1, 350 (io.deq.bits.uop.src2State === SrcState.rdy), io.deq.bits.uop.psrc2 351 ) 352 353 //update the index register of instruction that can be issue, unless function unit not allow in 354 //then the issue will be stopped to wait the function unit 355 //clear the validBit of dequeued instruction in issuequeue 356 when(io.deq.fire()){ 357 validReg(dequeueSelect) := false.B 358 validWillFalse(dequeueSelect) := true.B 359 } 360 361 val selRegflush = expRedirect || (brRedirect && brRedirectMaskMatch) 362 363 selInstRdy := Mux(selRegflush,false.B,selResult.instRdy) 364 selInstIdx := Mux(selRegflush,0.U,selResult.iqIdx) 365 // SelectedUop (bypass / speculative) 366 if(useBypass) { 367 assert(fixedDelay==1) // only support fixedDelay is 1 now 368 def DelayPipe[T <: Data](a: T, delay: Int = 0) = { 369 // println(delay) 370 if(delay == 0) a 371 else { 372 val storage = Wire(VecInit(Seq.fill(delay+1)(a))) 373 // storage(0) := a 374 for(i <- 1 until delay) { 375 storage(i) := RegNext(storage(i-1)) 376 } 377 storage(delay) 378 } 379 } 380 val sel = io.selectedUop 381 val selIQIdx = selResult.iqIdx 382 val delayPipe = DelayPipe(VecInit(selResult.instRdy, prfDest(selIQIdx)), fixedDelay-1) 383 sel.bits := DontCare 384 sel.bits.pdest := delayPipe(fixedDelay-1)(1) 385 } 386} 387