1package xiangshan.backend.issue 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import utils.SeqUtils 7import xiangshan.backend.BackendParams 8import xiangshan.backend.Bundles._ 9import xiangshan.backend.datapath.DataConfig.DataConfig 10import xiangshan.backend.datapath.WbConfig.PregWB 11import xiangshan.backend.datapath.{WakeUpConfig, WakeUpSource} 12import xiangshan.backend.exu.{ExeUnit, ExeUnitParams} 13import xiangshan.backend.fu.{FuConfig, FuType} 14 15case class IssueBlockParams( 16 // top down 17 private val exuParams: Seq[ExeUnitParams], 18 numEntries : Int, 19 numEnq : Int, 20 numDeqOutside : Int = 0, 21 numWakeupFromOthers : Int = 0, 22 XLEN : Int = 64, 23 VLEN : Int = 128, 24 vaddrBits : Int = 39, 25 // calculate in scheduler 26 var idxInSchBlk : Int = 0, 27)( 28 implicit 29 val schdType: SchedulerType, 30) { 31 var backendParam: BackendParams = null 32 33 val exuBlockParams: Seq[ExeUnitParams] = exuParams.filterNot(_.fakeUnit) 34 35 val allExuParams = exuParams 36 37 def updateIdx(idx: Int): Unit = { 38 this.idxInSchBlk = idx 39 } 40 41 def inMemSchd: Boolean = schdType == MemScheduler() 42 43 def inIntSchd: Boolean = schdType == IntScheduler() 44 45 def inVfSchd: Boolean = schdType == VfScheduler() 46 47 def isMemAddrIQ: Boolean = inMemSchd && StdCnt == 0 48 49 def isLdAddrIQ: Boolean = inMemSchd && LduCnt > 0 50 51 def isStAddrIQ: Boolean = inMemSchd && StaCnt > 0 52 53 def isHyAddrIQ: Boolean = inMemSchd && HyuCnt > 0 54 55 def numExu: Int = exuBlockParams.count(!_.fakeUnit) 56 57 def numIntSrc: Int = exuBlockParams.map(_.numIntSrc).max 58 59 def numFpSrc: Int = exuBlockParams.map(_.numFpSrc).max 60 61 def numVecSrc: Int = exuBlockParams.map(_.numVecSrc).max 62 63 def numVfSrc: Int = exuBlockParams.map(_.numVfSrc).max 64 65 def numRegSrc: Int = exuBlockParams.map(_.numRegSrc).max 66 67 def numSrc: Int = exuBlockParams.map(_.numSrc).max 68 69 def readIntRf: Boolean = numIntSrc > 0 70 71 def readFpRf: Boolean = numFpSrc > 0 72 73 def readVecRf: Boolean = numVecSrc > 0 74 75 def readVfRf: Boolean = numVfSrc > 0 76 77 def writeIntRf: Boolean = exuBlockParams.map(_.writeIntRf).reduce(_ || _) 78 79 def writeFpRf: Boolean = exuBlockParams.map(_.writeFpRf).reduce(_ || _) 80 81 def writeVecRf: Boolean = exuBlockParams.map(_.writeVecRf).reduce(_ || _) 82 83 def exceptionOut: Seq[Int] = exuBlockParams.map(_.exceptionOut).reduce(_ ++ _).distinct.sorted 84 85 def hasLoadError: Boolean = exuBlockParams.map(_.hasLoadError).reduce(_ || _) 86 87 def flushPipe: Boolean = exuBlockParams.map(_.flushPipe).reduce(_ || _) 88 89 def replayInst: Boolean = exuBlockParams.map(_.replayInst).reduce(_ || _) 90 91 def trigger: Boolean = exuBlockParams.map(_.trigger).reduce(_ || _) 92 93 def needExceptionGen: Boolean = exceptionOut.nonEmpty || flushPipe || replayInst || trigger 94 95 def needPc: Boolean = JmpCnt + BrhCnt + FenceCnt > 0 96 97 def needSrcFrm: Boolean = exuBlockParams.map(_.needSrcFrm).reduce(_ || _) 98 99 def numPcReadPort: Int = (if (needPc) 1 else 0) * numEnq 100 101 def numWriteIntRf: Int = exuBlockParams.count(_.writeIntRf) 102 103 def numWriteFpRf: Int = exuBlockParams.count(_.writeFpRf) 104 105 def numWriteVecRf: Int = exuBlockParams.count(_.writeVecRf) 106 107 def numWriteVfRf: Int = exuBlockParams.count(_.writeVfRf) 108 109 def numNoDataWB: Int = exuBlockParams.count(_.hasNoDataWB) 110 111 def dataBitsMax: Int = if (numVecSrc > 0) VLEN else XLEN 112 113 def numDeq: Int = numDeqOutside + exuBlockParams.length 114 115 def JmpCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.jmp)).sum 116 117 def BrhCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.brh)).sum 118 119 def I2fCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.i2f)).sum 120 121 def CsrCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.csr)).sum 122 123 def AluCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.alu)).sum 124 125 def MulCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.mul)).sum 126 127 def DivCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.div)).sum 128 129 def FenceCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.fence)).sum 130 131 def BkuCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.bku)).sum 132 133 def VsetCnt: Int = exuBlockParams.map(_.fuConfigs.count(x => x.fuType == FuType.vsetiwi || x.fuType == FuType.vsetiwf || x.fuType == FuType.vsetfwf)).sum 134 135 def FmacCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.fmac)).sum 136 137 def FmiscCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.fmisc)).sum 138 139 def fDivSqrtCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.fDivSqrt)).sum 140 141 def LduCnt: Int = exuBlockParams.count(x => x.hasLoadFu && !x.hasStoreAddrFu) 142 143 def StaCnt: Int = exuBlockParams.count(x => !x.hasLoadFu && x.hasStoreAddrFu) 144 145 def MouCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.mou)).sum 146 147 def StdCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.name == "std")).sum 148 149 def HyuCnt: Int = exuBlockParams.count(_.hasHyldaFu) // only count hylda, since it equals to hysta 150 151 def LdExuCnt = LduCnt + HyuCnt 152 153 def VipuCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.vipu)).sum 154 155 def VfpuCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.vfpu)).sum 156 157 def VlduCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.vldu)).sum 158 159 def VstuCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.vstu)).sum 160 161 def numRedirect: Int = exuBlockParams.count(_.hasRedirect) 162 163 /** 164 * Get the regfile type that this issue queue need to read 165 */ 166 def pregReadSet: Set[DataConfig] = exuBlockParams.map(_.pregRdDataCfgSet).fold(Set())(_ union _) 167 168 /** 169 * Get the regfile type that this issue queue need to read 170 */ 171 def pregWriteSet: Set[DataConfig] = exuBlockParams.map(_.pregWbDataCfgSet).fold(Set())(_ union _) 172 173 /** 174 * Get the max width of psrc 175 */ 176 def rdPregIdxWidth = { 177 this.pregReadSet.map(cfg => backendParam.getPregParams(cfg).addrWidth).fold(0)(_ max _) 178 } 179 180 /** 181 * Get the max width of pdest 182 */ 183 def wbPregIdxWidth = { 184 this.pregWriteSet.map(cfg => backendParam.getPregParams(cfg).addrWidth).fold(0)(_ max _) 185 } 186 187 def iqWakeUpSourcePairs: Seq[WakeUpConfig] = exuBlockParams.flatMap(_.iqWakeUpSourcePairs) 188 189 /** Get exu source wake up 190 * @todo replace with 191 * exuBlockParams 192 * .flatMap(_.iqWakeUpSinkPairs) 193 * .map(_.source) 194 * .distinctBy(_.name) 195 * when xiangshan is updated to 2.13.11 196 */ 197 def wakeUpInExuSources: Seq[WakeUpSource] = { 198 SeqUtils.distinctBy( 199 exuBlockParams 200 .flatMap(_.iqWakeUpSinkPairs) 201 .map(_.source) 202 )(_.name) 203 } 204 205 def wakeUpOutExuSources: Seq[WakeUpSource] = { 206 SeqUtils.distinctBy( 207 exuBlockParams 208 .flatMap(_.iqWakeUpSourcePairs) 209 .map(_.source) 210 )(_.name) 211 } 212 213 def wakeUpToExuSinks = exuBlockParams 214 .flatMap(_.iqWakeUpSourcePairs) 215 .map(_.sink).distinct 216 217 def numWakeupFromIQ: Int = wakeUpInExuSources.size 218 219 def numAllWakeUp: Int = numWakeupFromWB + numWakeupFromIQ + numWakeupFromOthers 220 221 def numWakeupFromWB = { 222 val pregSet = this.pregReadSet 223 pregSet.map(cfg => backendParam.getRfWriteSize(cfg)).sum 224 } 225 226 def hasIQWakeUp: Boolean = numWakeupFromIQ > 0 && numRegSrc > 0 227 228 def getFuCfgs: Seq[FuConfig] = exuBlockParams.flatMap(_.fuConfigs).distinct 229 230 // cfgs(exuIdx)(set of exu's wb) 231 232 /** 233 * Get [[PregWB]] of this IssueBlock 234 * @return set of [[PregWB]] of [[ExeUnit]] 235 */ 236 def getWbCfgs: Seq[Set[PregWB]] = { 237 exuBlockParams.map(exu => exu.wbPortConfigs.toSet) 238 } 239 240 def canAccept(fuType: UInt): Bool = { 241 Cat(getFuCfgs.map(_.fuType.U === fuType)).orR 242 } 243 244 def bindBackendParam(param: BackendParams): Unit = { 245 backendParam = param 246 } 247 248 def genExuInputDecoupledBundle(implicit p: Parameters): MixedVec[DecoupledIO[ExuInput]] = { 249 MixedVec(this.exuBlockParams.map(x => DecoupledIO(x.genExuInputBundle))) 250 } 251 252 def genExuOutputDecoupledBundle(implicit p: Parameters): MixedVec[DecoupledIO[ExuOutput]] = { 253 MixedVec(this.exuParams.map(x => DecoupledIO(x.genExuOutputBundle))) 254 } 255 256 def genExuOutputValidBundle(implicit p: Parameters): MixedVec[ValidIO[ExuOutput]] = { 257 MixedVec(this.exuParams.map(x => ValidIO(x.genExuOutputBundle))) 258 } 259 260 def genExuBypassValidBundle(implicit p: Parameters): MixedVec[ValidIO[ExuBypassBundle]] = { 261 MixedVec(this.exuParams.filterNot(_.fakeUnit).map(x => ValidIO(x.genExuBypassBundle))) 262 } 263 264 def genIssueDecoupledBundle(implicit p: Parameters): MixedVec[DecoupledIO[IssueQueueIssueBundle]] = { 265 MixedVec(exuBlockParams.filterNot(_.fakeUnit).map(x => DecoupledIO(new IssueQueueIssueBundle(this, x)))) 266 } 267 268 def genWBWakeUpSinkValidBundle: MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = { 269 val intBundle: Seq[ValidIO[IssueQueueWBWakeUpBundle]] = schdType match { 270 case IntScheduler() | MemScheduler() => backendParam.getIntWBExeGroup.map(x => ValidIO(new IssueQueueWBWakeUpBundle(x._2.map(_.exuIdx), backendParam))).toSeq 271 case _ => Seq() 272 } 273 val vfBundle = schdType match { 274 case VfScheduler() | MemScheduler() => backendParam.getVfWBExeGroup.map(x => ValidIO(new IssueQueueWBWakeUpBundle(x._2.map(_.exuIdx), backendParam))).toSeq 275 case _ => Seq() 276 } 277 MixedVec(intBundle ++ vfBundle) 278 } 279 280 def genIQWakeUpSourceValidBundle(implicit p: Parameters): MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = { 281 MixedVec(exuBlockParams.map(x => ValidIO(new IssueQueueIQWakeUpBundle(x.exuIdx, backendParam)))) 282 } 283 284 def genIQWakeUpSinkValidBundle(implicit p: Parameters): MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = { 285 MixedVec(this.wakeUpInExuSources.map(x => ValidIO(new IssueQueueIQWakeUpBundle(backendParam.getExuIdx(x.name), backendParam)))) 286 } 287 288 def genOGRespBundle(implicit p: Parameters) = { 289 implicit val issueBlockParams = this 290 MixedVec(exuBlockParams.map(_ => new OGRespBundle)) 291 } 292 293 def genWbFuBusyTableWriteBundle()(implicit p: Parameters) = { 294 implicit val issueBlockParams = this 295 MixedVec(exuBlockParams.map(x => new WbFuBusyTableWriteBundle(x))) 296 } 297 298 def genWbFuBusyTableReadBundle()(implicit p: Parameters) = { 299 implicit val issueBlockParams = this 300 MixedVec(exuBlockParams.map{ x => 301 new WbFuBusyTableReadBundle(x) 302 }) 303 } 304 305 def genWbConflictBundle()(implicit p: Parameters) = { 306 implicit val issueBlockParams = this 307 MixedVec(exuBlockParams.map { x => 308 new WbConflictBundle(x) 309 }) 310 } 311 312 def getIQName = { 313 "IssueQueue" ++ getFuCfgs.map(_.name).distinct.map(_.capitalize).reduce(_ ++ _) 314 } 315} 316