1package xiangshan.backend.issue 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import utils.SeqUtils 7import xiangshan.backend.BackendParams 8import xiangshan.backend.Bundles._ 9import xiangshan.backend.datapath.DataConfig.DataConfig 10import xiangshan.backend.datapath.WbConfig.PregWB 11import xiangshan.backend.datapath.{WakeUpConfig, WakeUpSource} 12import xiangshan.backend.exu.{ExeUnit, ExeUnitParams} 13import xiangshan.backend.fu.{FuConfig, FuType} 14 15case class IssueBlockParams( 16 // top down 17 private val exuParams: Seq[ExeUnitParams], 18 numEntries : Int, 19 numEnq : Int, 20 numDeqOutside : Int = 0, 21 numWakeupFromOthers : Int = 0, 22 XLEN : Int = 64, 23 VLEN : Int = 128, 24 vaddrBits : Int = 39, 25 // calculate in scheduler 26 var idxInSchBlk : Int = 0, 27)( 28 implicit 29 val schdType: SchedulerType, 30) { 31 var backendParam: BackendParams = null 32 33 val exuBlockParams: Seq[ExeUnitParams] = exuParams.filterNot(_.fakeUnit) 34 35 val allExuParams = exuParams 36 37 def updateIdx(idx: Int): Unit = { 38 this.idxInSchBlk = idx 39 } 40 41 def inMemSchd: Boolean = schdType == MemScheduler() 42 43 def inIntSchd: Boolean = schdType == IntScheduler() 44 45 def inVfSchd: Boolean = schdType == VfScheduler() 46 47 def isMemAddrIQ: Boolean = inMemSchd && StdCnt == 0 48 49 def isLdAddrIQ: Boolean = inMemSchd && LduCnt > 0 50 51 def isStAddrIQ: Boolean = inMemSchd && StaCnt > 0 52 53 def numExu: Int = exuBlockParams.count(!_.fakeUnit) 54 55 def numIntSrc: Int = exuBlockParams.map(_.numIntSrc).max 56 57 def numFpSrc: Int = exuBlockParams.map(_.numFpSrc).max 58 59 def numVecSrc: Int = exuBlockParams.map(_.numVecSrc).max 60 61 def numVfSrc: Int = exuBlockParams.map(_.numVfSrc).max 62 63 def numRegSrc: Int = exuBlockParams.map(_.numRegSrc).max 64 65 def numSrc: Int = exuBlockParams.map(_.numSrc).max 66 67 def readIntRf: Boolean = numIntSrc > 0 68 69 def readFpRf: Boolean = numFpSrc > 0 70 71 def readVecRf: Boolean = numVecSrc > 0 72 73 def readVfRf: Boolean = numVfSrc > 0 74 75 def writeIntRf: Boolean = exuBlockParams.map(_.writeIntRf).reduce(_ || _) 76 77 def writeFpRf: Boolean = exuBlockParams.map(_.writeFpRf).reduce(_ || _) 78 79 def writeVecRf: Boolean = exuBlockParams.map(_.writeVecRf).reduce(_ || _) 80 81 def exceptionOut: Seq[Int] = exuBlockParams.map(_.exceptionOut).reduce(_ ++ _).distinct.sorted 82 83 def hasLoadError: Boolean = exuBlockParams.map(_.hasLoadError).reduce(_ || _) 84 85 def flushPipe: Boolean = exuBlockParams.map(_.flushPipe).reduce(_ || _) 86 87 def replayInst: Boolean = exuBlockParams.map(_.replayInst).reduce(_ || _) 88 89 def trigger: Boolean = exuBlockParams.map(_.trigger).reduce(_ || _) 90 91 def needExceptionGen: Boolean = exceptionOut.nonEmpty || flushPipe || replayInst || trigger 92 93 def needPc: Boolean = JmpCnt + BrhCnt + FenceCnt > 0 94 95 def needSrcFrm: Boolean = exuBlockParams.map(_.needSrcFrm).reduce(_ || _) 96 97 def numPcReadPort: Int = (if (needPc) 1 else 0) * numEnq 98 99 def numWriteIntRf: Int = exuBlockParams.count(_.writeIntRf) 100 101 def numWriteFpRf: Int = exuBlockParams.count(_.writeFpRf) 102 103 def numWriteVecRf: Int = exuBlockParams.count(_.writeVecRf) 104 105 def numWriteVfRf: Int = exuBlockParams.count(_.writeVfRf) 106 107 def numNoDataWB: Int = exuBlockParams.count(_.hasNoDataWB) 108 109 def dataBitsMax: Int = if (numVecSrc > 0) VLEN else XLEN 110 111 def numDeq: Int = numDeqOutside + exuBlockParams.length 112 113 def JmpCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.jmp)).sum 114 115 def BrhCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.brh)).sum 116 117 def I2fCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.i2f)).sum 118 119 def CsrCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.csr)).sum 120 121 def AluCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.alu)).sum 122 123 def MulCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.mul)).sum 124 125 def DivCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.div)).sum 126 127 def FenceCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.fence)).sum 128 129 def BkuCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.bku)).sum 130 131 def VsetCnt: Int = exuBlockParams.map(_.fuConfigs.count(x => x.fuType == FuType.vsetiwi || x.fuType == FuType.vsetiwf || x.fuType == FuType.vsetfwf)).sum 132 133 def FmacCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.fmac)).sum 134 135 def FmiscCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.fmisc)).sum 136 137 def fDivSqrtCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.fDivSqrt)).sum 138 139 def LduCnt: Int = exuBlockParams.count(x => x.hasLoadFu && !x.hasStoreAddrFu) 140 141 def StaCnt: Int = exuBlockParams.count(x => !x.hasLoadFu && x.hasStoreAddrFu) 142 143 def MouCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.mou)).sum 144 145 def StdCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.name == "std")).sum 146 147 def HyuCnt: Int = exuBlockParams.count(_.hasHyldaFu) // only count hylda, since it equals to hysta 148 149 def VipuCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.vipu)).sum 150 151 def VfpuCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.vfpu)).sum 152 153 def VlduCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.vldu)).sum 154 155 def VstuCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.vstu)).sum 156 157 def numRedirect: Int = exuBlockParams.count(_.hasRedirect) 158 159 /** 160 * Get the regfile type that this issue queue need to read 161 */ 162 def pregReadSet: Set[DataConfig] = exuBlockParams.map(_.pregRdDataCfgSet).fold(Set())(_ union _) 163 164 /** 165 * Get the regfile type that this issue queue need to read 166 */ 167 def pregWriteSet: Set[DataConfig] = exuBlockParams.map(_.pregWbDataCfgSet).fold(Set())(_ union _) 168 169 /** 170 * Get the max width of psrc 171 */ 172 def rdPregIdxWidth = { 173 this.pregReadSet.map(cfg => backendParam.getPregParams(cfg).addrWidth).fold(0)(_ max _) 174 } 175 176 /** 177 * Get the max width of pdest 178 */ 179 def wbPregIdxWidth = { 180 this.pregWriteSet.map(cfg => backendParam.getPregParams(cfg).addrWidth).fold(0)(_ max _) 181 } 182 183 def iqWakeUpSourcePairs: Seq[WakeUpConfig] = exuBlockParams.flatMap(_.iqWakeUpSourcePairs) 184 185 /** Get exu source wake up 186 * @todo replace with 187 * exuBlockParams 188 * .flatMap(_.iqWakeUpSinkPairs) 189 * .map(_.source) 190 * .distinctBy(_.name) 191 * when xiangshan is updated to 2.13.11 192 */ 193 def wakeUpInExuSources: Seq[WakeUpSource] = { 194 SeqUtils.distinctBy( 195 exuBlockParams 196 .flatMap(_.iqWakeUpSinkPairs) 197 .map(_.source) 198 )(_.name) 199 } 200 201 def wakeUpOutExuSources: Seq[WakeUpSource] = { 202 SeqUtils.distinctBy( 203 exuBlockParams 204 .flatMap(_.iqWakeUpSourcePairs) 205 .map(_.source) 206 )(_.name) 207 } 208 209 def wakeUpToExuSinks = exuBlockParams 210 .flatMap(_.iqWakeUpSourcePairs) 211 .map(_.sink).distinct 212 213 def numWakeupFromIQ: Int = wakeUpInExuSources.size 214 215 def numAllWakeUp: Int = numWakeupFromWB + numWakeupFromIQ + numWakeupFromOthers 216 217 def numWakeupFromWB = { 218 val pregSet = this.pregReadSet 219 pregSet.map(cfg => backendParam.getRfWriteSize(cfg)).sum 220 } 221 222 def hasIQWakeUp: Boolean = numWakeupFromIQ > 0 && numRegSrc > 0 223 224 def getFuCfgs: Seq[FuConfig] = exuBlockParams.flatMap(_.fuConfigs).distinct 225 226 // cfgs(exuIdx)(set of exu's wb) 227 228 /** 229 * Get [[PregWB]] of this IssueBlock 230 * @return set of [[PregWB]] of [[ExeUnit]] 231 */ 232 def getWbCfgs: Seq[Set[PregWB]] = { 233 exuBlockParams.map(exu => exu.wbPortConfigs.toSet) 234 } 235 236 def canAccept(fuType: UInt): Bool = { 237 Cat(getFuCfgs.map(_.fuType.U === fuType)).orR 238 } 239 240 def bindBackendParam(param: BackendParams): Unit = { 241 backendParam = param 242 } 243 244 def genExuInputDecoupledBundle(implicit p: Parameters): MixedVec[DecoupledIO[ExuInput]] = { 245 MixedVec(this.exuBlockParams.map(x => DecoupledIO(x.genExuInputBundle))) 246 } 247 248 def genExuOutputDecoupledBundle(implicit p: Parameters): MixedVec[DecoupledIO[ExuOutput]] = { 249 MixedVec(this.exuParams.map(x => DecoupledIO(x.genExuOutputBundle))) 250 } 251 252 def genExuOutputValidBundle(implicit p: Parameters): MixedVec[ValidIO[ExuOutput]] = { 253 MixedVec(this.exuParams.map(x => ValidIO(x.genExuOutputBundle))) 254 } 255 256 def genExuBypassValidBundle(implicit p: Parameters): MixedVec[ValidIO[ExuBypassBundle]] = { 257 MixedVec(this.exuParams.filterNot(_.fakeUnit).map(x => ValidIO(x.genExuBypassBundle))) 258 } 259 260 def genIssueDecoupledBundle(implicit p: Parameters): MixedVec[DecoupledIO[IssueQueueIssueBundle]] = { 261 MixedVec(exuBlockParams.filterNot(_.fakeUnit).map(x => DecoupledIO(new IssueQueueIssueBundle(this, x)))) 262 } 263 264 def genWBWakeUpSinkValidBundle: MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = { 265 val intBundle: Seq[ValidIO[IssueQueueWBWakeUpBundle]] = schdType match { 266 case IntScheduler() | MemScheduler() => backendParam.getIntWBExeGroup.map(x => ValidIO(new IssueQueueWBWakeUpBundle(x._2.map(_.exuIdx), backendParam))).toSeq 267 case _ => Seq() 268 } 269 val vfBundle = schdType match { 270 case VfScheduler() | MemScheduler() => backendParam.getVfWBExeGroup.map(x => ValidIO(new IssueQueueWBWakeUpBundle(x._2.map(_.exuIdx), backendParam))).toSeq 271 case _ => Seq() 272 } 273 MixedVec(intBundle ++ vfBundle) 274 } 275 276 def genIQWakeUpSourceValidBundle(implicit p: Parameters): MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = { 277 MixedVec(exuBlockParams.map(x => ValidIO(new IssueQueueIQWakeUpBundle(x.exuIdx, backendParam)))) 278 } 279 280 def genIQWakeUpSinkValidBundle(implicit p: Parameters): MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = { 281 MixedVec(this.wakeUpInExuSources.map(x => ValidIO(new IssueQueueIQWakeUpBundle(backendParam.getExuIdx(x.name), backendParam)))) 282 } 283 284 def genOGRespBundle(implicit p: Parameters) = { 285 implicit val issueBlockParams = this 286 MixedVec(exuBlockParams.map(_ => new OGRespBundle)) 287 } 288 289 def genWbFuBusyTableWriteBundle()(implicit p: Parameters) = { 290 implicit val issueBlockParams = this 291 MixedVec(exuBlockParams.map(x => new WbFuBusyTableWriteBundle(x))) 292 } 293 294 def genWbFuBusyTableReadBundle()(implicit p: Parameters) = { 295 implicit val issueBlockParams = this 296 MixedVec(exuBlockParams.map{ x => 297 new WbFuBusyTableReadBundle(x) 298 }) 299 } 300 301 def genWbConflictBundle()(implicit p: Parameters) = { 302 implicit val issueBlockParams = this 303 MixedVec(exuBlockParams.map { x => 304 new WbConflictBundle(x) 305 }) 306 } 307 308 def getIQName = { 309 "IssueQueue" ++ getFuCfgs.map(_.name).distinct.map(_.capitalize).reduce(_ ++ _) 310 } 311} 312