1package xiangshan.backend.issue 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import utils.SeqUtils 7import xiangshan.backend.BackendParams 8import xiangshan.backend.Bundles._ 9import xiangshan.backend.datapath.DataConfig.DataConfig 10import xiangshan.backend.datapath.WbConfig.PregWB 11import xiangshan.backend.datapath.{WakeUpConfig, WakeUpSource} 12import xiangshan.backend.exu.{ExeUnit, ExeUnitParams} 13import xiangshan.backend.fu.{FuConfig, FuType} 14 15case class IssueBlockParams( 16 // top down 17 private val exuParams: Seq[ExeUnitParams], 18 numEntries : Int, 19 numEnq : Int, 20 numDeqOutside : Int = 0, 21 numWakeupFromOthers : Int = 0, 22 XLEN : Int = 64, 23 VLEN : Int = 128, 24 vaddrBits : Int = 39, 25 // calculate in scheduler 26 var idxInSchBlk : Int = 0, 27)( 28 implicit 29 val schdType: SchedulerType, 30) { 31 var backendParam: BackendParams = null 32 33 val exuBlockParams: Seq[ExeUnitParams] = exuParams.filterNot(_.fakeUnit) 34 35 val allExuParams = exuParams 36 37 def updateIdx(idx: Int): Unit = { 38 this.idxInSchBlk = idx 39 } 40 41 def inMemSchd: Boolean = schdType == MemScheduler() 42 43 def inIntSchd: Boolean = schdType == IntScheduler() 44 45 def inVfSchd: Boolean = schdType == VfScheduler() 46 47 def isMemAddrIQ: Boolean = inMemSchd && StdCnt == 0 48 49 def isLdAddrIQ: Boolean = inMemSchd && LduCnt > 0 50 51 def isStAddrIQ: Boolean = inMemSchd && StaCnt > 0 52 53 def isHyAddrIQ: Boolean = inMemSchd && HyuCnt > 0 54 55 def numExu: Int = exuBlockParams.count(!_.fakeUnit) 56 57 def numIntSrc: Int = exuBlockParams.map(_.numIntSrc).max 58 59 def numFpSrc: Int = exuBlockParams.map(_.numFpSrc).max 60 61 def numVecSrc: Int = exuBlockParams.map(_.numVecSrc).max 62 63 def numVfSrc: Int = exuBlockParams.map(_.numVfSrc).max 64 65 def numRegSrc: Int = exuBlockParams.map(_.numRegSrc).max 66 67 def numSrc: Int = exuBlockParams.map(_.numSrc).max 68 69 def readIntRf: Boolean = numIntSrc > 0 70 71 def readFpRf: Boolean = numFpSrc > 0 72 73 def readVecRf: Boolean = numVecSrc > 0 74 75 def readVfRf: Boolean = numVfSrc > 0 76 77 def writeIntRf: Boolean = exuBlockParams.map(_.writeIntRf).reduce(_ || _) 78 79 def writeFpRf: Boolean = exuBlockParams.map(_.writeFpRf).reduce(_ || _) 80 81 def writeVecRf: Boolean = exuBlockParams.map(_.writeVecRf).reduce(_ || _) 82 83 def exceptionOut: Seq[Int] = exuBlockParams.map(_.exceptionOut).reduce(_ ++ _).distinct.sorted 84 85 def hasLoadError: Boolean = exuBlockParams.map(_.hasLoadError).reduce(_ || _) 86 87 def flushPipe: Boolean = exuBlockParams.map(_.flushPipe).reduce(_ || _) 88 89 def replayInst: Boolean = exuBlockParams.map(_.replayInst).reduce(_ || _) 90 91 def trigger: Boolean = exuBlockParams.map(_.trigger).reduce(_ || _) 92 93 def needExceptionGen: Boolean = exceptionOut.nonEmpty || flushPipe || replayInst || trigger 94 95 def needPc: Boolean = JmpCnt + BrhCnt + FenceCnt > 0 96 97 def needSrcFrm: Boolean = exuBlockParams.map(_.needSrcFrm).reduce(_ || _) 98 99 def numPcReadPort: Int = (if (needPc) 1 else 0) * numEnq 100 101 def numWriteIntRf: Int = exuBlockParams.count(_.writeIntRf) 102 103 def numWriteFpRf: Int = exuBlockParams.count(_.writeFpRf) 104 105 def numWriteVecRf: Int = exuBlockParams.count(_.writeVecRf) 106 107 def numWriteVfRf: Int = exuBlockParams.count(_.writeVfRf) 108 109 def numNoDataWB: Int = exuBlockParams.count(_.hasNoDataWB) 110 111 def dataBitsMax: Int = if (numVecSrc > 0) VLEN else XLEN 112 113 def numDeq: Int = numDeqOutside + exuBlockParams.length 114 115 def JmpCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.jmp)).sum 116 117 def BrhCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.brh)).sum 118 119 def I2fCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.i2f)).sum 120 121 def CsrCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.csr)).sum 122 123 def AluCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.alu)).sum 124 125 def MulCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.mul)).sum 126 127 def DivCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.div)).sum 128 129 def FenceCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.fence)).sum 130 131 def BkuCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.bku)).sum 132 133 def VsetCnt: Int = exuBlockParams.map(_.fuConfigs.count(x => x.fuType == FuType.vsetiwi || x.fuType == FuType.vsetiwf || x.fuType == FuType.vsetfwf)).sum 134 135 def FmacCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.fmac)).sum 136 137 def FmiscCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.fmisc)).sum 138 139 def fDivSqrtCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.fDivSqrt)).sum 140 141 def LduCnt: Int = exuBlockParams.count(x => x.hasLoadFu && !x.hasStoreAddrFu) 142 143 def StaCnt: Int = exuBlockParams.count(x => !x.hasLoadFu && x.hasStoreAddrFu) 144 145 def MouCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.mou)).sum 146 147 def StdCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.name == "std")).sum 148 149 def HyuCnt: Int = exuBlockParams.count(_.hasHyldaFu) // only count hylda, since it equals to hysta 150 151 def VipuCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.vipu)).sum 152 153 def VfpuCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.vfpu)).sum 154 155 def VlduCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.vldu)).sum 156 157 def VstuCnt: Int = exuBlockParams.map(_.fuConfigs.count(_.fuType == FuType.vstu)).sum 158 159 def numRedirect: Int = exuBlockParams.count(_.hasRedirect) 160 161 /** 162 * Get the regfile type that this issue queue need to read 163 */ 164 def pregReadSet: Set[DataConfig] = exuBlockParams.map(_.pregRdDataCfgSet).fold(Set())(_ union _) 165 166 /** 167 * Get the regfile type that this issue queue need to read 168 */ 169 def pregWriteSet: Set[DataConfig] = exuBlockParams.map(_.pregWbDataCfgSet).fold(Set())(_ union _) 170 171 /** 172 * Get the max width of psrc 173 */ 174 def rdPregIdxWidth = { 175 this.pregReadSet.map(cfg => backendParam.getPregParams(cfg).addrWidth).fold(0)(_ max _) 176 } 177 178 /** 179 * Get the max width of pdest 180 */ 181 def wbPregIdxWidth = { 182 this.pregWriteSet.map(cfg => backendParam.getPregParams(cfg).addrWidth).fold(0)(_ max _) 183 } 184 185 def iqWakeUpSourcePairs: Seq[WakeUpConfig] = exuBlockParams.flatMap(_.iqWakeUpSourcePairs) 186 187 /** Get exu source wake up 188 * @todo replace with 189 * exuBlockParams 190 * .flatMap(_.iqWakeUpSinkPairs) 191 * .map(_.source) 192 * .distinctBy(_.name) 193 * when xiangshan is updated to 2.13.11 194 */ 195 def wakeUpInExuSources: Seq[WakeUpSource] = { 196 SeqUtils.distinctBy( 197 exuBlockParams 198 .flatMap(_.iqWakeUpSinkPairs) 199 .map(_.source) 200 )(_.name) 201 } 202 203 def wakeUpOutExuSources: Seq[WakeUpSource] = { 204 SeqUtils.distinctBy( 205 exuBlockParams 206 .flatMap(_.iqWakeUpSourcePairs) 207 .map(_.source) 208 )(_.name) 209 } 210 211 def wakeUpToExuSinks = exuBlockParams 212 .flatMap(_.iqWakeUpSourcePairs) 213 .map(_.sink).distinct 214 215 def numWakeupFromIQ: Int = wakeUpInExuSources.size 216 217 def numAllWakeUp: Int = numWakeupFromWB + numWakeupFromIQ + numWakeupFromOthers 218 219 def numWakeupFromWB = { 220 val pregSet = this.pregReadSet 221 pregSet.map(cfg => backendParam.getRfWriteSize(cfg)).sum 222 } 223 224 def hasIQWakeUp: Boolean = numWakeupFromIQ > 0 && numRegSrc > 0 225 226 def getFuCfgs: Seq[FuConfig] = exuBlockParams.flatMap(_.fuConfigs).distinct 227 228 // cfgs(exuIdx)(set of exu's wb) 229 230 /** 231 * Get [[PregWB]] of this IssueBlock 232 * @return set of [[PregWB]] of [[ExeUnit]] 233 */ 234 def getWbCfgs: Seq[Set[PregWB]] = { 235 exuBlockParams.map(exu => exu.wbPortConfigs.toSet) 236 } 237 238 def canAccept(fuType: UInt): Bool = { 239 Cat(getFuCfgs.map(_.fuType.U === fuType)).orR 240 } 241 242 def bindBackendParam(param: BackendParams): Unit = { 243 backendParam = param 244 } 245 246 def genExuInputDecoupledBundle(implicit p: Parameters): MixedVec[DecoupledIO[ExuInput]] = { 247 MixedVec(this.exuBlockParams.map(x => DecoupledIO(x.genExuInputBundle))) 248 } 249 250 def genExuOutputDecoupledBundle(implicit p: Parameters): MixedVec[DecoupledIO[ExuOutput]] = { 251 MixedVec(this.exuParams.map(x => DecoupledIO(x.genExuOutputBundle))) 252 } 253 254 def genExuOutputValidBundle(implicit p: Parameters): MixedVec[ValidIO[ExuOutput]] = { 255 MixedVec(this.exuParams.map(x => ValidIO(x.genExuOutputBundle))) 256 } 257 258 def genExuBypassValidBundle(implicit p: Parameters): MixedVec[ValidIO[ExuBypassBundle]] = { 259 MixedVec(this.exuParams.filterNot(_.fakeUnit).map(x => ValidIO(x.genExuBypassBundle))) 260 } 261 262 def genIssueDecoupledBundle(implicit p: Parameters): MixedVec[DecoupledIO[IssueQueueIssueBundle]] = { 263 MixedVec(exuBlockParams.filterNot(_.fakeUnit).map(x => DecoupledIO(new IssueQueueIssueBundle(this, x)))) 264 } 265 266 def genWBWakeUpSinkValidBundle: MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = { 267 val intBundle: Seq[ValidIO[IssueQueueWBWakeUpBundle]] = schdType match { 268 case IntScheduler() | MemScheduler() => backendParam.getIntWBExeGroup.map(x => ValidIO(new IssueQueueWBWakeUpBundle(x._2.map(_.exuIdx), backendParam))).toSeq 269 case _ => Seq() 270 } 271 val vfBundle = schdType match { 272 case VfScheduler() | MemScheduler() => backendParam.getVfWBExeGroup.map(x => ValidIO(new IssueQueueWBWakeUpBundle(x._2.map(_.exuIdx), backendParam))).toSeq 273 case _ => Seq() 274 } 275 MixedVec(intBundle ++ vfBundle) 276 } 277 278 def genIQWakeUpSourceValidBundle(implicit p: Parameters): MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = { 279 MixedVec(exuBlockParams.map(x => ValidIO(new IssueQueueIQWakeUpBundle(x.exuIdx, backendParam)))) 280 } 281 282 def genIQWakeUpSinkValidBundle(implicit p: Parameters): MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = { 283 MixedVec(this.wakeUpInExuSources.map(x => ValidIO(new IssueQueueIQWakeUpBundle(backendParam.getExuIdx(x.name), backendParam)))) 284 } 285 286 def genOGRespBundle(implicit p: Parameters) = { 287 implicit val issueBlockParams = this 288 MixedVec(exuBlockParams.map(_ => new OGRespBundle)) 289 } 290 291 def genWbFuBusyTableWriteBundle()(implicit p: Parameters) = { 292 implicit val issueBlockParams = this 293 MixedVec(exuBlockParams.map(x => new WbFuBusyTableWriteBundle(x))) 294 } 295 296 def genWbFuBusyTableReadBundle()(implicit p: Parameters) = { 297 implicit val issueBlockParams = this 298 MixedVec(exuBlockParams.map{ x => 299 new WbFuBusyTableReadBundle(x) 300 }) 301 } 302 303 def genWbConflictBundle()(implicit p: Parameters) = { 304 implicit val issueBlockParams = this 305 MixedVec(exuBlockParams.map { x => 306 new WbConflictBundle(x) 307 }) 308 } 309 310 def getIQName = { 311 "IssueQueue" ++ getFuCfgs.map(_.name).distinct.map(_.capitalize).reduce(_ ++ _) 312 } 313} 314