xref: /XiangShan/src/main/scala/xiangshan/backend/issue/FuBusyTableRead.scala (revision de93b50824dbba16b462d31c87da7274fadafdf3) 
1package xiangshan.backend.issue
2
3import chipsalliance.rocketchip.config.Parameters
4import chisel3._
5import chisel3.util._
6import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
7import utility.HasCircularQueuePtrHelper
8import xiangshan._
9import xiangshan.backend.fu.{FuConfig, FuType}
10import xiangshan.mem.{MemWaitUpdateReq, SqPtr}
11import xiangshan.backend.Bundles.{DynInst, IssueQueueIssueBundle, IssueQueueWakeUpBundle}
12import xiangshan.backend.datapath.DataConfig._
13import xiangshan.backend.exu.ExeUnitParams
14
15class FuBusyTableRead(val idx: Int, isWb: Boolean, isVf: Boolean = false)(implicit p: Parameters, iqParams: IssueBlockParams) extends XSModule {
16  val io = IO(new FuBusyTableReadIO(idx, isWb, isVf))
17
18  val fuBusyTableSplit = if (!isWb) io.in.fuBusyTable.asBools.reverse else io.in.fuBusyTable.asBools
19  val latencyMap = if (!isWb) iqParams.exuBlockParams(idx).fuLatencyMap
20                   else if (isVf) iqParams.exuBlockParams(idx).vfFuLatencyMap
21                   else iqParams.exuBlockParams(idx).intFuLatencyMap
22  val fuTypeRegVec = io.in.fuTypeRegVec
23
24
25  val isReadLatencyNumVec2 = fuBusyTableSplit.zipWithIndex.map { case (en, latencyIdx) =>
26    val latencyHitVec = WireInit(0.U(iqParams.numEntries.W))
27    when(en) {
28      latencyHitVec := VecInit(fuTypeRegVec.map { case futype =>
29        val latencyHitFuType = latencyMap.get.filter(_._2 == latencyIdx).map(_._1)
30        val isLatencyNum = Cat(latencyHitFuType.map(_.U === futype)).asUInt.orR
31        isLatencyNum
32      }).asUInt
33    }
34    latencyHitVec
35  }
36
37  io.out.fuBusyTableMask := isReadLatencyNumVec2.fold(0.U(iqParams.numEntries.W))(_ | _)
38}
39
40class FuBusyTableReadIO(val idx: Int, isWb: Boolean, isVf: Boolean)(implicit p: Parameters, iqParams: IssueBlockParams) extends XSBundle {
41  val in = new Bundle {
42    val fuBusyTable = if (!isWb) Input(UInt(iqParams.exuBlockParams(idx).latencyValMax.get.W))
43                      else if (isVf) Input(UInt((iqParams.exuBlockParams(idx).vfLatencyValMax.get + 1).W))
44                      else Input(UInt((iqParams.exuBlockParams(idx).intLatencyValMax.get + 1).W))
45    val fuTypeRegVec = Input(Vec(iqParams.numEntries, FuType()))
46  }
47  val out = new Bundle {
48    val fuBusyTableMask = Output(UInt(iqParams.numEntries.W))
49  }
50}