xref: /XiangShan/src/main/scala/xiangshan/backend/issue/EntryBundles.scala (revision f08a822fa3aea4169d21b5e03e5db3b29c8f5574)
1package xiangshan.backend.issue
2
3import org.chipsalliance.cde.config.Parameters
4import chisel3._
5import chisel3.util._
6import utils.{MathUtils, OptionWrapper}
7import utility.HasCircularQueuePtrHelper
8import xiangshan._
9import xiangshan.backend.Bundles._
10import xiangshan.backend.datapath.DataSource
11import xiangshan.backend.fu.FuType
12import xiangshan.backend.rob.RobPtr
13import xiangshan.mem.{MemWaitUpdateReq, SqPtr, LqPtr}
14
15object EntryBundles extends HasCircularQueuePtrHelper {
16
17  class Status(implicit p: Parameters, params: IssueBlockParams) extends XSBundle {
18    //basic status
19    val robIdx                = new RobPtr
20    val fuType                = IQFuType()
21    //src status
22    val srcStatus             = Vec(params.numRegSrc, new SrcStatus)
23    //issue status
24    val blocked               = Bool()
25    val issued                = Bool()
26    val firstIssue            = Bool()
27    val issueTimer            = UInt(2.W)
28    val deqPortIdx            = UInt(1.W)
29    //mem status
30    val mem                   = OptionWrapper(params.isMemAddrIQ, new StatusMemPart)
31    //vector mem status
32    val vecMem                = OptionWrapper(params.isVecMemIQ, new StatusVecMemPart)
33
34    def srcReady: Bool        = {
35      VecInit(srcStatus.map(_.srcState).map(SrcState.isReady)).asUInt.andR
36    }
37
38    def canIssue: Bool        = {
39      srcReady && !issued && !blocked
40    }
41
42    def mergedLoadDependency: Vec[UInt] = {
43      srcStatus.map(_.srcLoadDependency).reduce({
44        case (l: Vec[UInt], r: Vec[UInt]) => VecInit(l.zip(r).map(x => x._1 | x._2))
45      }: (Vec[UInt], Vec[UInt]) => Vec[UInt])
46    }
47  }
48
49  class SrcStatus(implicit p: Parameters, params: IssueBlockParams) extends XSBundle {
50    val psrc                  = UInt(params.rdPregIdxWidth.W)
51    val srcType               = SrcType()
52    val srcState              = SrcState()
53    val dataSources           = DataSource()
54    val srcLoadDependency     = Vec(LoadPipelineWidth, UInt(3.W))
55    val srcTimer              = OptionWrapper(params.hasIQWakeUp, UInt(3.W))
56    val srcWakeUpL1ExuOH      = OptionWrapper(params.hasIQWakeUp, ExuVec())
57  }
58
59  class StatusMemPart(implicit p:Parameters) extends Bundle {
60    val waitForSqIdx          = new SqPtr // generated by store data valid check
61    val waitForRobIdx         = new RobPtr // generated by store set
62    val waitForStd            = Bool()
63    val strictWait            = Bool()
64    val sqIdx                 = new SqPtr
65  }
66
67  class StatusVecMemPart(implicit p:Parameters, params: IssueBlockParams) extends Bundle {
68    val sqIdx = new SqPtr
69    val lqIdx = new LqPtr
70    val uopIdx = UopIdx()
71  }
72
73  class EntryDeqRespBundle(implicit p: Parameters, params: IssueBlockParams) extends Bundle {
74    val robIdx                = new RobPtr
75    val resp                  = RespType()
76    val fuType                = FuType()
77    val uopIdx                = OptionWrapper(params.isVecMemIQ, Output(UopIdx()))
78  }
79
80  object RespType {
81    def apply() = UInt(2.W)
82
83    def isBlocked(resp: UInt) = {
84      resp === block
85    }
86
87    def succeed(resp: UInt) = {
88      resp === success
89    }
90
91    val block = "b00".U
92    val uncertain = "b01".U
93    val success = "b11".U
94  }
95
96  class EntryBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle {
97    val status                = new Status()
98    val imm                   = OptionWrapper(params.needImm, UInt((params.deqImmTypesMaxLen).W))
99    val payload               = new DynInst()
100  }
101
102  class CommonInBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle {
103    val flush                 = Flipped(ValidIO(new Redirect))
104    val enq                   = Flipped(ValidIO(new EntryBundle))
105    //wakeup
106    val wakeUpFromWB: MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = Flipped(params.genWBWakeUpSinkValidBundle)
107    val wakeUpFromIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(params.genIQWakeUpSinkValidBundle)
108    //cancel
109    val og0Cancel             = Input(ExuOH(backendParams.numExu))
110    val og1Cancel             = Input(ExuOH(backendParams.numExu))
111    val ldCancel              = Vec(backendParams.LdExuCnt, Flipped(new LoadCancelIO))
112    //deq sel
113    val deqSel                = Input(Bool())
114    val deqPortIdxWrite       = Input(UInt(1.W))
115    val issueResp             = Flipped(ValidIO(new EntryDeqRespBundle))
116    //trans sel
117    val transSel              = Input(Bool())
118    // mem only
119    val fromMem = OptionWrapper(params.isMemAddrIQ, new Bundle {
120      val stIssuePtr          = Input(new SqPtr)
121      val memWaitUpdateReq    = Flipped(new MemWaitUpdateReq)
122    })
123    // vector mem only
124    val fromLsq = OptionWrapper(params.isVecMemIQ, new Bundle {
125      val sqDeqPtr = Input(new SqPtr)
126      val lqDeqPtr = Input(new LqPtr)
127    })
128  }
129
130  class CommonOutBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle {
131    //status
132    val valid                 = Output(Bool())
133    val canIssue              = Output(Bool())
134    val fuType                = Output(FuType())
135    val robIdx                = Output(new RobPtr)
136    val uopIdx                = OptionWrapper(params.isVecMemIQ, Output(UopIdx()))
137    //src
138    val dataSource            = Vec(params.numRegSrc, Output(DataSource()))
139    val srcLoadDependency     = Vec(params.numRegSrc, Output(Vec(LoadPipelineWidth, UInt(3.W))))
140    val srcWakeUpL1ExuOH      = OptionWrapper(params.hasIQWakeUp, Vec(params.numRegSrc, Output(ExuVec())))
141    val srcTimer              = OptionWrapper(params.hasIQWakeUp, Vec(params.numRegSrc, Output(UInt(3.W))))
142    //deq
143    val isFirstIssue          = Output(Bool())
144    val entry                 = ValidIO(new EntryBundle)
145    val deqPortIdxRead        = Output(UInt(1.W))
146    val issueTimerRead        = Output(UInt(2.W))
147    //trans
148    val enqReady              = Output(Bool())
149    val transEntry            = ValidIO(new EntryBundle)
150    // debug
151    val cancel                = OptionWrapper(params.hasIQWakeUp, Output(Bool()))
152  }
153
154  class CommonWireBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle {
155    val validRegNext          = Bool()
156    val flushed               = Bool()
157    val clear                 = Bool()
158    val canIssue              = Bool()
159    val enqReady              = Bool()
160    val deqSuccess            = Bool()
161    val srcWakeup             = Vec(params.numRegSrc, Bool())
162    val srcWakeupByWB         = Vec(params.numRegSrc, Bool())
163    val srcLoadDependencyOut  = Vec(params.numRegSrc, Vec(LoadPipelineWidth, UInt(3.W)))
164    val srcCancelVec          = Vec(params.numRegSrc, Bool())
165    val srcLoadCancelVec      = Vec(params.numRegSrc, Bool())
166  }
167
168  def CommonWireConnect(common: CommonWireBundle, hasIQWakeup: Option[CommonIQWakeupBundle], validReg: Bool, status: Status, commonIn: CommonInBundle, isEnq: Boolean)(implicit p: Parameters, params: IssueBlockParams) = {
169    val hasIQWakeupGet        = hasIQWakeup.getOrElse(0.U.asTypeOf(new CommonIQWakeupBundle))
170    common.flushed            := status.robIdx.needFlush(commonIn.flush)
171    common.deqSuccess         := commonIn.issueResp.valid && RespType.succeed(commonIn.issueResp.bits.resp) && !common.srcLoadCancelVec.asUInt.orR
172    common.srcWakeup          := common.srcWakeupByWB.zip(hasIQWakeupGet.srcWakeupByIQ).map { case (x, y) => x || y.asUInt.orR }
173    common.srcWakeupByWB      := commonIn.wakeUpFromWB.map(bundle => bundle.bits.wakeUp(status.srcStatus.map(_.psrc) zip status.srcStatus.map(_.srcType), bundle.valid)).transpose.map(x => VecInit(x.toSeq).asUInt.orR).toSeq
174    common.canIssue           := validReg && status.canIssue
175    common.enqReady           := !validReg || common.clear
176    common.clear              := common.flushed || common.deqSuccess || commonIn.transSel
177    common.srcCancelVec.zip(common.srcLoadCancelVec).zip(hasIQWakeupGet.srcWakeupByIQWithoutCancel).zipWithIndex.foreach { case (((srcCancel, srcLoadCancel), wakeUpByIQVec), srcIdx) =>
178      val ldTransCancel = if(params.hasIQWakeUp) Mux1H(wakeUpByIQVec, hasIQWakeupGet.wakeupLoadDependencyByIQVec.map(dep => LoadShouldCancel(Some(dep), commonIn.ldCancel))) else false.B
179      srcLoadCancel := LoadShouldCancel(Some(status.srcStatus(srcIdx).srcLoadDependency), commonIn.ldCancel)
180      srcCancel := srcLoadCancel || ldTransCancel
181    }
182    common.srcLoadDependencyOut.zip(hasIQWakeupGet.srcWakeupByIQ).zip(status.srcStatus.map(_.srcLoadDependency)).foreach {
183      case ((loadDependencyOut, wakeUpByIQVec), loadDependency) =>
184        if(params.hasIQWakeUp) {
185          loadDependencyOut := Mux(wakeUpByIQVec.asUInt.orR, Mux1H(wakeUpByIQVec, hasIQWakeupGet.shiftedWakeupLoadDependencyByIQBypassVec), loadDependency)
186        } else {
187          loadDependencyOut := loadDependency
188        }
189
190    }
191    if(isEnq) {
192      common.validRegNext     := Mux(commonIn.enq.valid && common.enqReady, true.B, Mux(common.clear, false.B, validReg))
193    } else {
194      common.validRegNext     := Mux(commonIn.enq.valid, true.B, Mux(common.clear, false.B, validReg))
195    }
196  }
197
198  class CommonIQWakeupBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle {
199    val srcWakeupByIQ                             = Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool()))
200    val srcWakeupByIQWithoutCancel                = Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool()))
201    val srcWakeupByIQButCancel                    = Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool()))
202    val regSrcWakeupL1ExuOH                       = Vec(params.numRegSrc, ExuVec())
203    val srcWakeupL1ExuOHOut                       = Vec(params.numRegSrc, ExuVec())
204    val wakeupLoadDependencyByIQVec               = Vec(params.numWakeupFromIQ, Vec(LoadPipelineWidth, UInt(3.W)))
205    val shiftedWakeupLoadDependencyByIQVec        = Vec(params.numWakeupFromIQ, Vec(LoadPipelineWidth, UInt(3.W)))
206    val shiftedWakeupLoadDependencyByIQBypassVec  = Vec(params.numWakeupFromIQ, Vec(LoadPipelineWidth, UInt(3.W)))
207    val cancelVec                                 = Vec(params.numRegSrc, Bool())
208    val canIssueBypass                            = Bool()
209  }
210
211  def CommonIQWakeupConnect(common: CommonWireBundle, hasIQWakeupGet: CommonIQWakeupBundle, validReg: Bool, status: Status, commonIn: CommonInBundle, isEnq: Boolean)(implicit p: Parameters, params: IssueBlockParams) = {
212    val wakeupVec: Seq[Seq[Bool]] = commonIn.wakeUpFromIQ.map((bundle: ValidIO[IssueQueueIQWakeUpBundle]) =>
213      bundle.bits.wakeUpFromIQ(status.srcStatus.map(_.psrc) zip status.srcStatus.map(_.srcType))
214    ).toSeq.transpose
215    val cancelSel = params.wakeUpSourceExuIdx.zip(commonIn.wakeUpFromIQ).map { case (x, y) => commonIn.og0Cancel(x) && y.bits.is0Lat }
216
217    hasIQWakeupGet.cancelVec                        := common.srcCancelVec
218    hasIQWakeupGet.srcWakeupByIQ                    := wakeupVec.map(x => VecInit(x.zip(cancelSel).map { case (wakeup, cancel) => wakeup && !cancel }))
219    hasIQWakeupGet.srcWakeupByIQButCancel           := wakeupVec.map(x => VecInit(x.zip(cancelSel).map { case (wakeup, cancel) => wakeup && cancel }))
220    hasIQWakeupGet.srcWakeupByIQWithoutCancel       := wakeupVec.map(x => VecInit(x))
221    hasIQWakeupGet.wakeupLoadDependencyByIQVec      := commonIn.wakeUpFromIQ.map(_.bits.loadDependency).toSeq
222    hasIQWakeupGet.regSrcWakeupL1ExuOH.zip(status.srcStatus.map(_.srcWakeUpL1ExuOH.get)).foreach {
223      case (exuOH, regExuOH) =>
224        exuOH                                       := 0.U.asTypeOf(exuOH)
225        params.wakeUpSourceExuIdx.foreach(x => exuOH(x) := regExuOH(x))
226    }
227    hasIQWakeupGet.srcWakeupL1ExuOHOut.zip(hasIQWakeupGet.srcWakeupByIQWithoutCancel).zip(common.srcWakeup).zipWithIndex.foreach {
228      case (((exuOH: Vec[Bool], wakeUpByIQOH: Vec[Bool]), wakeUp: Bool), srcIdx) =>
229        if(isEnq) {
230          ExuOHGen(exuOH, wakeUpByIQOH, wakeUp, status.srcStatus(srcIdx).srcWakeUpL1ExuOH.get)
231        } else {
232          ExuOHGen(exuOH, wakeUpByIQOH, wakeUp, hasIQWakeupGet.regSrcWakeupL1ExuOH(srcIdx))
233        }
234    }
235    hasIQWakeupGet.canIssueBypass                   := validReg && !status.issued && !status.blocked &&
236      VecInit(status.srcStatus.map(_.srcState).zip(hasIQWakeupGet.srcWakeupByIQWithoutCancel).zipWithIndex.map { case ((state, wakeupVec), srcIdx) =>
237        wakeupVec.asUInt.orR | state
238      }).asUInt.andR
239  }
240
241
242  def ShiftLoadDependency(hasIQWakeupGet: CommonIQWakeupBundle)(implicit p: Parameters, params: IssueBlockParams) = {
243    hasIQWakeupGet.shiftedWakeupLoadDependencyByIQVec
244      .zip(hasIQWakeupGet.wakeupLoadDependencyByIQVec)
245      .zip(params.wakeUpInExuSources.map(_.name)).foreach {
246      case ((deps, originalDeps), name) => deps.zip(originalDeps).zipWithIndex.foreach {
247        case ((dep, originalDep), deqPortIdx) =>
248          if (name.contains("LDU") && name.replace("LDU", "").toInt == deqPortIdx)
249            dep := (originalDep << 2).asUInt | 2.U
250          else
251            dep := originalDep << 1
252      }
253    }
254    hasIQWakeupGet.shiftedWakeupLoadDependencyByIQBypassVec
255      .zip(hasIQWakeupGet.wakeupLoadDependencyByIQVec)
256      .zip(params.wakeUpInExuSources.map(_.name)).foreach {
257      case ((deps, originalDeps), name) => deps.zip(originalDeps).zipWithIndex.foreach {
258        case ((dep, originalDep), deqPortIdx) =>
259          if (name.contains("LDU") && name.replace("LDU", "").toInt == deqPortIdx)
260            dep := (originalDep << 1).asUInt | 1.U
261          else
262            dep := originalDep
263      }
264    }
265  }
266
267  def EntryRegCommonConnect(common: CommonWireBundle, hasIQWakeup: Option[CommonIQWakeupBundle], validReg: Bool, entryUpdate: EntryBundle, entryReg: EntryBundle, status: Status, commonIn: CommonInBundle, isEnq: Boolean)(implicit p: Parameters, params: IssueBlockParams) = {
268    val hasIQWakeupGet                                 = hasIQWakeup.getOrElse(0.U.asTypeOf(new CommonIQWakeupBundle))
269    val cancelByLd                                     = common.srcCancelVec.asUInt.orR
270    val cancelWhenWakeup                               = VecInit(hasIQWakeupGet.srcWakeupByIQButCancel.map(_.asUInt.orR)).asUInt.orR
271    val respIssueFail                                  = commonIn.issueResp.valid && RespType.isBlocked(commonIn.issueResp.bits.resp)
272    val srcWakeupExuOH                                 = if(isEnq) status.srcStatus.map(_.srcWakeUpL1ExuOH.getOrElse(0.U.asTypeOf(ExuVec()))) else hasIQWakeupGet.regSrcWakeupL1ExuOH
273    entryUpdate.status.robIdx                         := status.robIdx
274    entryUpdate.status.fuType                         := IQFuType.readFuType(status.fuType, params.getFuCfgs.map(_.fuType))
275    entryUpdate.status.srcStatus.zip(status.srcStatus).zipWithIndex.foreach { case ((srcStatusNext, srcStatus), srcIdx) =>
276      val cancel = common.srcCancelVec(srcIdx)
277      val wakeupByIQ = hasIQWakeupGet.srcWakeupByIQ(srcIdx).asUInt.orR
278      val wakeupByIQOH = hasIQWakeupGet.srcWakeupByIQ(srcIdx)
279      val wakeup = common.srcWakeup(srcIdx)
280      srcStatusNext.psrc                              := srcStatus.psrc
281      srcStatusNext.srcType                           := srcStatus.srcType
282      srcStatusNext.srcState                          := Mux(cancel, false.B, wakeup | srcStatus.srcState)
283      srcStatusNext.dataSources.value                 := Mux(wakeupByIQ, DataSource.bypass, DataSource.reg)
284      if(params.hasIQWakeUp) {
285        srcStatusNext.srcTimer.get                    := MuxCase(3.U, Seq(
286          // T0: waked up by IQ, T1: reset timer as 1
287          wakeupByIQ                                  -> 2.U,
288          // do not overflow
289          srcStatus.srcTimer.get.andR                 -> srcStatus.srcTimer.get,
290          // T2+: increase if the entry is valid, the src is ready, and the src is woken up by iq
291          (validReg && SrcState.isReady(srcStatus.srcState) && srcWakeupExuOH(srcIdx).asUInt.orR) -> (srcStatus.srcTimer.get + 1.U)
292        ))
293        ExuOHGen(srcStatusNext.srcWakeUpL1ExuOH.get, wakeupByIQOH, wakeup, srcWakeupExuOH(srcIdx))
294        srcStatusNext.srcLoadDependency               :=
295          Mux(wakeup,
296            Mux1H(wakeupByIQOH, hasIQWakeupGet.shiftedWakeupLoadDependencyByIQVec),
297            Mux(validReg && srcStatus.srcLoadDependency.asUInt.orR, VecInit(srcStatus.srcLoadDependency.map(i => i(i.getWidth - 2, 0) << 1)), srcStatus.srcLoadDependency))
298      } else {
299        srcStatusNext.srcLoadDependency               := Mux(validReg && srcStatus.srcLoadDependency.asUInt.orR, VecInit(srcStatus.srcLoadDependency.map(i => i(i.getWidth - 2, 0) << 1)), srcStatus.srcLoadDependency)
300      }
301    }
302    entryUpdate.status.blocked                        := false.B
303    entryUpdate.status.issued                         := MuxCase(status.issued, Seq(
304      (cancelByLd || cancelWhenWakeup || respIssueFail) -> false.B,
305      commonIn.deqSel                                   -> true.B,
306      !status.srcReady                                  -> false.B,
307    ))
308    entryUpdate.status.firstIssue                     := commonIn.deqSel || status.firstIssue
309    entryUpdate.status.issueTimer                     := Mux(commonIn.deqSel, 0.U, Mux(status.issued, status.issueTimer + 1.U, "b10".U))
310    entryUpdate.status.deqPortIdx                     := Mux(commonIn.deqSel, commonIn.deqPortIdxWrite, Mux(status.issued, status.deqPortIdx, 0.U))
311    entryUpdate.imm.foreach(_                         := entryReg.imm.get)
312    entryUpdate.payload                               := entryReg.payload
313    if (params.isVecMemIQ) {
314      entryUpdate.status.vecMem.get := entryReg.status.vecMem.get
315    }
316  }
317
318  def CommonOutConnect(commonOut: CommonOutBundle, common: CommonWireBundle, hasIQWakeup: Option[CommonIQWakeupBundle], validReg: Bool, entryUpdate: EntryBundle, entryReg: EntryBundle, status: Status, commonIn: CommonInBundle, isEnq: Boolean, isComp: Boolean)(implicit p: Parameters, params: IssueBlockParams) = {
319    val hasIQWakeupGet                                 = hasIQWakeup.getOrElse(0.U.asTypeOf(new CommonIQWakeupBundle))
320    val srcWakeupExuOH                                 = if(isEnq) status.srcStatus.map(_.srcWakeUpL1ExuOH.getOrElse(0.U.asTypeOf(ExuVec()))) else hasIQWakeupGet.regSrcWakeupL1ExuOH
321    commonOut.valid                                   := validReg
322    commonOut.canIssue                                := (if (isComp) (common.canIssue || hasIQWakeupGet.canIssueBypass) && !common.flushed
323                                                          else common.canIssue && !common.flushed)
324    commonOut.fuType                                  := IQFuType.readFuType(status.fuType, params.getFuCfgs.map(_.fuType)).asUInt
325    commonOut.robIdx                                  := status.robIdx
326    commonOut.dataSource.zipWithIndex.foreach{ case (dataSourceOut, srcIdx) =>
327      dataSourceOut.value                             := Mux(hasIQWakeupGet.srcWakeupByIQ(srcIdx).asUInt.orR, DataSource.forward, status.srcStatus(srcIdx).dataSources.value)
328    }
329    commonOut.isFirstIssue                            := !status.firstIssue
330    commonOut.entry.valid                             := validReg
331    commonOut.entry.bits                              := entryReg
332    if(isEnq) {
333      commonOut.entry.bits.status                     := status
334    }
335    commonOut.issueTimerRead                          := status.issueTimer
336    commonOut.deqPortIdxRead                          := status.deqPortIdx
337    if(params.hasIQWakeUp) {
338      val wakeupSrcLoadDependency                      = hasIQWakeupGet.srcWakeupByIQWithoutCancel.map(x => Mux1H(x, hasIQWakeupGet.wakeupLoadDependencyByIQVec))
339      commonOut.srcWakeUpL1ExuOH.get                  := (if (isComp) Mux(hasIQWakeupGet.canIssueBypass && !common.canIssue, hasIQWakeupGet.srcWakeupL1ExuOHOut, VecInit(srcWakeupExuOH))
340                                                          else VecInit(srcWakeupExuOH))
341      commonOut.srcTimer.get.zipWithIndex.foreach { case (srcTimerOut, srcIdx) =>
342        val wakeupByIQOH                               = hasIQWakeupGet.srcWakeupByIQWithoutCancel(srcIdx)
343        srcTimerOut                                   := Mux(wakeupByIQOH.asUInt.orR, Mux1H(wakeupByIQOH, commonIn.wakeUpFromIQ.map(_.bits.is0Lat).toSeq).asUInt, status.srcStatus(srcIdx).srcTimer.get)
344      }
345      commonOut.srcLoadDependency.zipWithIndex.foreach { case (srcLoadDependencyOut, srcIdx) =>
346        srcLoadDependencyOut                          := (if (isComp) Mux(hasIQWakeupGet.canIssueBypass && !common.canIssue,
347                                                                      VecInit(status.srcStatus(srcIdx).srcLoadDependency.zip(wakeupSrcLoadDependency(srcIdx)).map(x => x._1 | x._2)),
348                                                                      status.srcStatus(srcIdx).srcLoadDependency)
349                                                          else status.srcStatus(srcIdx).srcLoadDependency)
350      }
351    } else {
352      commonOut.srcLoadDependency.zipWithIndex.foreach { case (srcLoadDependencyOut, srcIdx) =>
353        srcLoadDependencyOut                          := status.srcStatus(srcIdx).srcLoadDependency
354      }
355    }
356    commonOut.entry.bits.status.srcStatus.map(_.srcLoadDependency).zipWithIndex.foreach { case (srcLoadDependencyOut, srcIdx) =>
357      srcLoadDependencyOut                            := (if (isComp) Mux(hasIQWakeupGet.canIssueBypass && !common.canIssue,
358                                                                      common.srcLoadDependencyOut(srcIdx),
359                                                                      status.srcStatus(srcIdx).srcLoadDependency)
360                                                          else status.srcStatus(srcIdx).srcLoadDependency)
361    }
362    commonOut.enqReady                                := common.enqReady
363    commonOut.transEntry.valid                        := validReg && !common.flushed && !common.deqSuccess
364    commonOut.transEntry.bits                         := entryUpdate
365    commonOut.cancel.foreach(_                        := hasIQWakeupGet.cancelVec.asUInt.orR)
366    if (params.isVecMemIQ) {
367      commonOut.uopIdx.get                            := status.vecMem.get.uopIdx
368    }
369  }
370
371  def EntryMemConnect(commonIn: CommonInBundle, common: CommonWireBundle, validReg: Bool, entryReg: EntryBundle, entryRegNext: EntryBundle, entryUpdate: EntryBundle, isEnq: Boolean)(implicit p: Parameters, params: IssueBlockParams) = {
372    val enqValid                                       = if(isEnq) commonIn.enq.valid && common.enqReady
373                                                         else commonIn.enq.valid
374    val fromMem                                        = commonIn.fromMem.get
375    val memStatus                                      = entryReg.status.mem.get
376    val memStatusNext                                  = entryRegNext.status.mem.get
377    val memStatusUpdate                                = entryUpdate.status.mem.get
378
379    when(enqValid) {
380      memStatusNext.waitForSqIdx                      := commonIn.enq.bits.status.mem.get.waitForSqIdx
381      // update by lfst at dispatch stage
382      memStatusNext.waitForRobIdx                     := commonIn.enq.bits.status.mem.get.waitForRobIdx
383      // new load inst don't known if it is blocked by store data ahead of it
384      memStatusNext.waitForStd                        := false.B
385      // update by ssit at rename stage
386      memStatusNext.strictWait                        := commonIn.enq.bits.status.mem.get.strictWait
387      memStatusNext.sqIdx                             := commonIn.enq.bits.status.mem.get.sqIdx
388    }.otherwise {
389      memStatusNext := memStatusUpdate
390    }
391
392    // load cannot be issued before older store, unless meet some condition
393    val blockedByOlderStore                            = isAfter(memStatusNext.sqIdx, fromMem.stIssuePtr)
394
395
396    val staWaitedReleased = Cat(
397      fromMem.memWaitUpdateReq.robIdx.map(x => x.valid && x.bits.value === memStatusNext.waitForRobIdx.value)
398    ).orR
399    val stdWaitedReleased = Cat(
400      fromMem.memWaitUpdateReq.sqIdx.map(x => x.valid && x.bits.value === memStatusNext.waitForSqIdx.value)
401    ).orR
402    val olderStaNotViolate                             = staWaitedReleased && !memStatusNext.strictWait
403    val olderStdReady                                  = stdWaitedReleased && memStatusNext.waitForStd
404    val waitStd                                        = !olderStdReady
405    val waitSta                                        = !olderStaNotViolate
406
407    memStatusUpdate                                   := memStatus
408
409    val shouldBlock                                    = Mux(enqValid, commonIn.enq.bits.status.blocked, entryReg.status.blocked)
410    val blockNotReleased                               = waitStd || waitSta
411    entryUpdate.status.blocked                        := shouldBlock && blockNotReleased && blockedByOlderStore
412    entryRegNext.status.blocked                       := entryUpdate.status.blocked
413  }
414
415  def ExuOHGen(exuOH: Vec[Bool], wakeupByIQOH: Vec[Bool], wakeup: Bool, regSrcExuOH: Vec[Bool])(implicit p: Parameters, params: IssueBlockParams) = {
416    val origExuOH = 0.U.asTypeOf(exuOH)
417    when(wakeupByIQOH.asUInt.orR) {
418      origExuOH := Mux1H(wakeupByIQOH, params.wakeUpSourceExuIdx.map(x => MathUtils.IntToOH(x).U(p(XSCoreParamsKey).backendParams.numExu.W)).toSeq).asBools
419    }.elsewhen(wakeup) {
420      origExuOH := 0.U.asTypeOf(origExuOH)
421    }.otherwise {
422      origExuOH := regSrcExuOH
423    }
424    exuOH := 0.U.asTypeOf(exuOH)
425    params.wakeUpSourceExuIdx.foreach(x => exuOH(x) := origExuOH(x))
426  }
427
428  object IQFuType {
429    def num = FuType.num
430
431    def apply() = Vec(num, Bool())
432
433    def readFuType(fuType: Vec[Bool], fus: Seq[FuType.OHType]): Vec[Bool] = {
434      val res = 0.U.asTypeOf(fuType)
435      fus.foreach(x => res(x.id) := fuType(x.id))
436      res
437    }
438  }
439}
440