1package xiangshan.backend.issue 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import utils.{MathUtils, OptionWrapper} 7import utility.HasCircularQueuePtrHelper 8import xiangshan._ 9import xiangshan.backend.Bundles._ 10import xiangshan.backend.datapath.DataSource 11import xiangshan.backend.fu.FuType 12import xiangshan.backend.rob.RobPtr 13import xiangshan.mem.{MemWaitUpdateReq, SqPtr, LqPtr} 14 15object EntryBundles extends HasCircularQueuePtrHelper { 16 17 class Status(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 18 //basic status 19 val robIdx = new RobPtr 20 val fuType = IQFuType() 21 //src status 22 val srcStatus = Vec(params.numRegSrc, new SrcStatus) 23 //issue status 24 val blocked = Bool() 25 val issued = Bool() 26 val firstIssue = Bool() 27 val issueTimer = UInt(2.W) 28 val deqPortIdx = UInt(1.W) 29 //mem status 30 val mem = OptionWrapper(params.isMemAddrIQ, new StatusMemPart) 31 //vector mem status 32 val vecMem = OptionWrapper(params.isVecMemIQ, new StatusVecMemPart) 33 34 def srcReady: Bool = { 35 VecInit(srcStatus.map(_.srcState).map(SrcState.isReady)).asUInt.andR 36 } 37 38 def canIssue: Bool = { 39 srcReady && !issued && !blocked 40 } 41 42 def mergedLoadDependency: Vec[UInt] = { 43 srcStatus.map(_.srcLoadDependency).reduce({ 44 case (l: Vec[UInt], r: Vec[UInt]) => VecInit(l.zip(r).map(x => x._1 | x._2)) 45 }: (Vec[UInt], Vec[UInt]) => Vec[UInt]) 46 } 47 } 48 49 class SrcStatus(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 50 val psrc = UInt(params.rdPregIdxWidth.W) 51 val srcType = SrcType() 52 val srcState = SrcState() 53 val dataSources = DataSource() 54 val srcLoadDependency = Vec(LoadPipelineWidth, UInt(3.W)) 55 val srcTimer = OptionWrapper(params.hasIQWakeUp, UInt(3.W)) 56 val srcWakeUpL1ExuOH = OptionWrapper(params.hasIQWakeUp, ExuVec()) 57 } 58 59 class StatusMemPart(implicit p:Parameters) extends Bundle { 60 val waitForSqIdx = new SqPtr // generated by store data valid check 61 val waitForRobIdx = new RobPtr // generated by store set 62 val waitForStd = Bool() 63 val strictWait = Bool() 64 val sqIdx = new SqPtr 65 } 66 67 class StatusVecMemPart(implicit p:Parameters, params: IssueBlockParams) extends Bundle { 68 val sqIdx = new SqPtr 69 val lqIdx = new LqPtr 70 val uopIdx = UopIdx() 71 } 72 73 class EntryDeqRespBundle(implicit p: Parameters, params: IssueBlockParams) extends Bundle { 74 val robIdx = new RobPtr 75 val respType = RSFeedbackType() // update credit if needs replay 76 val dataInvalidSqIdx = new SqPtr 77 val rfWen = Bool() 78 val fuType = FuType() 79 val uopIdx = OptionWrapper(params.isVecMemIQ, Output(UopIdx())) 80 } 81 82 class EntryBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 83 val status = new Status() 84 val imm = OptionWrapper(params.needImm, UInt((params.deqImmTypesMaxLen).W)) 85 val payload = new DynInst() 86 } 87 88 class CommonInBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 89 val flush = Flipped(ValidIO(new Redirect)) 90 val enq = Flipped(ValidIO(new EntryBundle)) 91 //wakeup 92 val wakeUpFromWB: MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = Flipped(params.genWBWakeUpSinkValidBundle) 93 val wakeUpFromIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(params.genIQWakeUpSinkValidBundle) 94 //cancel 95 val og0Cancel = Input(ExuOH(backendParams.numExu)) 96 val og1Cancel = Input(ExuOH(backendParams.numExu)) 97 val ldCancel = Vec(backendParams.LdExuCnt, Flipped(new LoadCancelIO)) 98 //deq sel 99 val deqSel = Input(Bool()) 100 val deqPortIdxWrite = Input(UInt(1.W)) 101 val issueResp = Flipped(ValidIO(new EntryDeqRespBundle)) 102 //trans sel 103 val transSel = Input(Bool()) 104 // mem only 105 val fromMem = OptionWrapper(params.isMemAddrIQ, new Bundle { 106 val stIssuePtr = Input(new SqPtr) 107 val memWaitUpdateReq = Flipped(new MemWaitUpdateReq) 108 }) 109 // vector mem only 110 val fromLsq = OptionWrapper(params.isVecMemIQ, new Bundle { 111 val sqDeqPtr = Input(new SqPtr) 112 val lqDeqPtr = Input(new LqPtr) 113 }) 114 } 115 116 class CommonOutBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 117 //status 118 val valid = Output(Bool()) 119 val canIssue = Output(Bool()) 120 val fuType = Output(FuType()) 121 val robIdx = Output(new RobPtr) 122 val uopIdx = OptionWrapper(params.isVecMemIQ, Output(UopIdx())) 123 //src 124 val dataSource = Vec(params.numRegSrc, Output(DataSource())) 125 val srcLoadDependency = Vec(params.numRegSrc, Output(Vec(LoadPipelineWidth, UInt(3.W)))) 126 val srcWakeUpL1ExuOH = OptionWrapper(params.hasIQWakeUp, Vec(params.numRegSrc, Output(ExuVec()))) 127 val srcTimer = OptionWrapper(params.hasIQWakeUp, Vec(params.numRegSrc, Output(UInt(3.W)))) 128 //deq 129 val isFirstIssue = Output(Bool()) 130 val entry = ValidIO(new EntryBundle) 131 val deqPortIdxRead = Output(UInt(1.W)) 132 val issueTimerRead = Output(UInt(2.W)) 133 //trans 134 val enqReady = Output(Bool()) 135 val transEntry = ValidIO(new EntryBundle) 136 // debug 137 val cancel = OptionWrapper(params.hasIQWakeUp, Output(Bool())) 138 } 139 140 class CommonWireBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 141 val validRegNext = Bool() 142 val flushed = Bool() 143 val clear = Bool() 144 val canIssue = Bool() 145 val enqReady = Bool() 146 val deqSuccess = Bool() 147 val srcWakeup = Vec(params.numRegSrc, Bool()) 148 val srcWakeupByWB = Vec(params.numRegSrc, Bool()) 149 val srcLoadDependencyOut = Vec(params.numRegSrc, Vec(LoadPipelineWidth, UInt(3.W))) 150 val srcCancelVec = Vec(params.numRegSrc, Bool()) 151 val srcLoadCancelVec = Vec(params.numRegSrc, Bool()) 152 } 153 154 def CommonWireConnect(common: CommonWireBundle, hasIQWakeup: Option[CommonIQWakeupBundle], validReg: Bool, status: Status, commonIn: CommonInBundle, isEnq: Boolean)(implicit p: Parameters, params: IssueBlockParams) = { 155 val hasIQWakeupGet = hasIQWakeup.getOrElse(0.U.asTypeOf(new CommonIQWakeupBundle)) 156 common.flushed := status.robIdx.needFlush(commonIn.flush) 157 common.deqSuccess := commonIn.issueResp.valid && commonIn.issueResp.bits.respType === RSFeedbackType.fuIdle && !common.srcLoadCancelVec.asUInt.orR 158 common.srcWakeup := common.srcWakeupByWB.zip(hasIQWakeupGet.srcWakeupByIQ).map { case (x, y) => x || y.asUInt.orR } 159 common.srcWakeupByWB := commonIn.wakeUpFromWB.map(bundle => bundle.bits.wakeUp(status.srcStatus.map(_.psrc) zip status.srcStatus.map(_.srcType), bundle.valid)).transpose.map(x => VecInit(x.toSeq).asUInt.orR).toSeq 160 common.canIssue := validReg && status.canIssue 161 common.enqReady := !validReg || common.clear 162 common.clear := common.flushed || common.deqSuccess || commonIn.transSel 163 common.srcCancelVec.zip(common.srcLoadCancelVec).zip(hasIQWakeupGet.srcWakeupByIQWithoutCancel).zipWithIndex.foreach { case (((srcCancel, srcLoadCancel), wakeUpByIQVec), srcIdx) => 164 val ldTransCancel = if(params.hasIQWakeUp) Mux1H(wakeUpByIQVec, hasIQWakeupGet.wakeupLoadDependencyByIQVec.map(dep => LoadShouldCancel(Some(dep), commonIn.ldCancel))) else false.B 165 srcLoadCancel := LoadShouldCancel(Some(status.srcStatus(srcIdx).srcLoadDependency), commonIn.ldCancel) 166 srcCancel := srcLoadCancel || ldTransCancel 167 } 168 common.srcLoadDependencyOut.zip(hasIQWakeupGet.srcWakeupByIQ).zip(status.srcStatus.map(_.srcLoadDependency)).foreach { 169 case ((loadDependencyOut, wakeUpByIQVec), loadDependency) => 170 if(params.hasIQWakeUp) { 171 loadDependencyOut := Mux(wakeUpByIQVec.asUInt.orR, Mux1H(wakeUpByIQVec, hasIQWakeupGet.shiftedWakeupLoadDependencyByIQBypassVec), loadDependency) 172 } else { 173 loadDependencyOut := loadDependency 174 } 175 176 } 177 if(isEnq) { 178 common.validRegNext := Mux(commonIn.enq.valid && common.enqReady, true.B, Mux(common.clear, false.B, validReg)) 179 } else { 180 common.validRegNext := Mux(commonIn.enq.valid, true.B, Mux(common.clear, false.B, validReg)) 181 } 182 } 183 184 class CommonIQWakeupBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 185 val srcWakeupByIQ = Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool())) 186 val srcWakeupByIQWithoutCancel = Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool())) 187 val srcWakeupByIQButCancel = Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool())) 188 val regSrcWakeupL1ExuOH = Vec(params.numRegSrc, ExuVec()) 189 val srcWakeupL1ExuOHOut = Vec(params.numRegSrc, ExuVec()) 190 val wakeupLoadDependencyByIQVec = Vec(params.numWakeupFromIQ, Vec(LoadPipelineWidth, UInt(3.W))) 191 val shiftedWakeupLoadDependencyByIQVec = Vec(params.numWakeupFromIQ, Vec(LoadPipelineWidth, UInt(3.W))) 192 val shiftedWakeupLoadDependencyByIQBypassVec = Vec(params.numWakeupFromIQ, Vec(LoadPipelineWidth, UInt(3.W))) 193 val cancelVec = Vec(params.numRegSrc, Bool()) 194 val canIssueBypass = Bool() 195 } 196 197 def CommonIQWakeupConnect(common: CommonWireBundle, hasIQWakeupGet: CommonIQWakeupBundle, validReg: Bool, status: Status, commonIn: CommonInBundle, isEnq: Boolean)(implicit p: Parameters, params: IssueBlockParams) = { 198 val wakeupVec: Seq[Seq[Bool]] = commonIn.wakeUpFromIQ.map((bundle: ValidIO[IssueQueueIQWakeUpBundle]) => 199 bundle.bits.wakeUpFromIQ(status.srcStatus.map(_.psrc) zip status.srcStatus.map(_.srcType)) 200 ).toSeq.transpose 201 val cancelSel = params.wakeUpSourceExuIdx.zip(commonIn.wakeUpFromIQ).map { case (x, y) => commonIn.og0Cancel(x) && y.bits.is0Lat } 202 203 hasIQWakeupGet.cancelVec := common.srcCancelVec 204 hasIQWakeupGet.srcWakeupByIQ := wakeupVec.map(x => VecInit(x.zip(cancelSel).map { case (wakeup, cancel) => wakeup && !cancel })) 205 hasIQWakeupGet.srcWakeupByIQButCancel := wakeupVec.map(x => VecInit(x.zip(cancelSel).map { case (wakeup, cancel) => wakeup && cancel })) 206 hasIQWakeupGet.srcWakeupByIQWithoutCancel := wakeupVec.map(x => VecInit(x)) 207 hasIQWakeupGet.wakeupLoadDependencyByIQVec := commonIn.wakeUpFromIQ.map(_.bits.loadDependency).toSeq 208 hasIQWakeupGet.regSrcWakeupL1ExuOH.zip(status.srcStatus.map(_.srcWakeUpL1ExuOH.get)).foreach { 209 case (exuOH, regExuOH) => 210 exuOH := 0.U.asTypeOf(exuOH) 211 params.wakeUpSourceExuIdx.foreach(x => exuOH(x) := regExuOH(x)) 212 } 213 hasIQWakeupGet.srcWakeupL1ExuOHOut.zip(hasIQWakeupGet.srcWakeupByIQWithoutCancel).zip(common.srcWakeup).zipWithIndex.foreach { 214 case (((exuOH: Vec[Bool], wakeUpByIQOH: Vec[Bool]), wakeUp: Bool), srcIdx) => 215 if(isEnq) { 216 ExuOHGen(exuOH, wakeUpByIQOH, wakeUp, status.srcStatus(srcIdx).srcWakeUpL1ExuOH.get) 217 } else { 218 ExuOHGen(exuOH, wakeUpByIQOH, wakeUp, hasIQWakeupGet.regSrcWakeupL1ExuOH(srcIdx)) 219 } 220 } 221 hasIQWakeupGet.canIssueBypass := validReg && !status.issued && !status.blocked && 222 VecInit(status.srcStatus.map(_.srcState).zip(hasIQWakeupGet.srcWakeupByIQWithoutCancel).zipWithIndex.map { case ((state, wakeupVec), srcIdx) => 223 wakeupVec.asUInt.orR | state 224 }).asUInt.andR 225 } 226 227 228 def ShiftLoadDependency(hasIQWakeupGet: CommonIQWakeupBundle)(implicit p: Parameters, params: IssueBlockParams) = { 229 hasIQWakeupGet.shiftedWakeupLoadDependencyByIQVec 230 .zip(hasIQWakeupGet.wakeupLoadDependencyByIQVec) 231 .zip(params.wakeUpInExuSources.map(_.name)).foreach { 232 case ((deps, originalDeps), name) => deps.zip(originalDeps).zipWithIndex.foreach { 233 case ((dep, originalDep), deqPortIdx) => 234 if (name.contains("LDU") && name.replace("LDU", "").toInt == deqPortIdx) 235 dep := (originalDep << 2).asUInt | 2.U 236 else 237 dep := originalDep << 1 238 } 239 } 240 hasIQWakeupGet.shiftedWakeupLoadDependencyByIQBypassVec 241 .zip(hasIQWakeupGet.wakeupLoadDependencyByIQVec) 242 .zip(params.wakeUpInExuSources.map(_.name)).foreach { 243 case ((deps, originalDeps), name) => deps.zip(originalDeps).zipWithIndex.foreach { 244 case ((dep, originalDep), deqPortIdx) => 245 if (name.contains("LDU") && name.replace("LDU", "").toInt == deqPortIdx) 246 dep := (originalDep << 1).asUInt | 1.U 247 else 248 dep := originalDep 249 } 250 } 251 } 252 253 def EntryRegCommonConnect(common: CommonWireBundle, hasIQWakeup: Option[CommonIQWakeupBundle], validReg: Bool, entryUpdate: EntryBundle, entryReg: EntryBundle, status: Status, commonIn: CommonInBundle, isEnq: Boolean)(implicit p: Parameters, params: IssueBlockParams) = { 254 val hasIQWakeupGet = hasIQWakeup.getOrElse(0.U.asTypeOf(new CommonIQWakeupBundle)) 255 val cancelByLd = common.srcCancelVec.asUInt.orR 256 val cancelWhenWakeup = VecInit(hasIQWakeupGet.srcWakeupByIQButCancel.map(_.asUInt.orR)).asUInt.orR 257 val respIssueFail = commonIn.issueResp.valid && RSFeedbackType.isBlocked(commonIn.issueResp.bits.respType) 258 val srcWakeupExuOH = if(isEnq) status.srcStatus.map(_.srcWakeUpL1ExuOH.getOrElse(0.U.asTypeOf(ExuVec()))) else hasIQWakeupGet.regSrcWakeupL1ExuOH 259 entryUpdate.status.robIdx := status.robIdx 260 entryUpdate.status.fuType := IQFuType.readFuType(status.fuType, params.getFuCfgs.map(_.fuType)) 261 entryUpdate.status.srcStatus.zip(status.srcStatus).zipWithIndex.foreach { case ((srcStatusNext, srcStatus), srcIdx) => 262 val cancel = common.srcCancelVec(srcIdx) 263 val wakeupByIQ = hasIQWakeupGet.srcWakeupByIQ(srcIdx).asUInt.orR 264 val wakeupByIQOH = hasIQWakeupGet.srcWakeupByIQ(srcIdx) 265 val wakeup = common.srcWakeup(srcIdx) 266 srcStatusNext.psrc := srcStatus.psrc 267 srcStatusNext.srcType := srcStatus.srcType 268 srcStatusNext.srcState := Mux(cancel, false.B, wakeup | srcStatus.srcState) 269 srcStatusNext.dataSources.value := Mux(wakeupByIQ, DataSource.bypass, DataSource.reg) 270 if(params.hasIQWakeUp) { 271 srcStatusNext.srcTimer.get := MuxCase(3.U, Seq( 272 // T0: waked up by IQ, T1: reset timer as 1 273 wakeupByIQ -> 2.U, 274 // do not overflow 275 srcStatus.srcTimer.get.andR -> srcStatus.srcTimer.get, 276 // T2+: increase if the entry is valid, the src is ready, and the src is woken up by iq 277 (validReg && SrcState.isReady(srcStatus.srcState) && srcWakeupExuOH(srcIdx).asUInt.orR) -> (srcStatus.srcTimer.get + 1.U) 278 )) 279 ExuOHGen(srcStatusNext.srcWakeUpL1ExuOH.get, wakeupByIQOH, wakeup, srcWakeupExuOH(srcIdx)) 280 srcStatusNext.srcLoadDependency := 281 Mux(wakeup, 282 Mux1H(wakeupByIQOH, hasIQWakeupGet.shiftedWakeupLoadDependencyByIQVec), 283 Mux(validReg && srcStatus.srcLoadDependency.asUInt.orR, VecInit(srcStatus.srcLoadDependency.map(i => i(i.getWidth - 2, 0) << 1)), srcStatus.srcLoadDependency)) 284 } else { 285 srcStatusNext.srcLoadDependency := Mux(validReg && srcStatus.srcLoadDependency.asUInt.orR, VecInit(srcStatus.srcLoadDependency.map(i => i(i.getWidth - 2, 0) << 1)), srcStatus.srcLoadDependency) 286 } 287 } 288 entryUpdate.status.blocked := false.B 289 entryUpdate.status.issued := MuxCase(status.issued, Seq( 290 (cancelByLd || cancelWhenWakeup || respIssueFail) -> false.B, 291 commonIn.deqSel -> true.B, 292 !status.srcReady -> false.B, 293 )) 294 entryUpdate.status.firstIssue := commonIn.deqSel || status.firstIssue 295 entryUpdate.status.issueTimer := Mux(commonIn.deqSel, 0.U, Mux(status.issued, status.issueTimer + 1.U, "b10".U)) 296 entryUpdate.status.deqPortIdx := Mux(commonIn.deqSel, commonIn.deqPortIdxWrite, Mux(status.issued, status.deqPortIdx, 0.U)) 297 entryUpdate.imm.foreach(_ := entryReg.imm.get) 298 entryUpdate.payload := entryReg.payload 299 if (params.isVecMemIQ) { 300 entryUpdate.status.vecMem.get := entryReg.status.vecMem.get 301 } 302 } 303 304 def CommonOutConnect(commonOut: CommonOutBundle, common: CommonWireBundle, hasIQWakeup: Option[CommonIQWakeupBundle], validReg: Bool, entryUpdate: EntryBundle, entryReg: EntryBundle, status: Status, commonIn: CommonInBundle, isEnq: Boolean, isComp: Boolean)(implicit p: Parameters, params: IssueBlockParams) = { 305 val hasIQWakeupGet = hasIQWakeup.getOrElse(0.U.asTypeOf(new CommonIQWakeupBundle)) 306 val srcWakeupExuOH = if(isEnq) status.srcStatus.map(_.srcWakeUpL1ExuOH.getOrElse(0.U.asTypeOf(ExuVec()))) else hasIQWakeupGet.regSrcWakeupL1ExuOH 307 commonOut.valid := validReg 308 commonOut.canIssue := (if (isComp) (common.canIssue || hasIQWakeupGet.canIssueBypass) && !common.flushed 309 else common.canIssue && !common.flushed) 310 commonOut.fuType := IQFuType.readFuType(status.fuType, params.getFuCfgs.map(_.fuType)).asUInt 311 commonOut.robIdx := status.robIdx 312 commonOut.dataSource.zipWithIndex.foreach{ case (dataSourceOut, srcIdx) => 313 dataSourceOut.value := Mux(hasIQWakeupGet.srcWakeupByIQ(srcIdx).asUInt.orR, DataSource.forward, status.srcStatus(srcIdx).dataSources.value) 314 } 315 commonOut.isFirstIssue := !status.firstIssue 316 commonOut.entry.valid := validReg 317 commonOut.entry.bits := entryReg 318 if(isEnq) { 319 commonOut.entry.bits.status := status 320 } 321 commonOut.issueTimerRead := status.issueTimer 322 commonOut.deqPortIdxRead := status.deqPortIdx 323 if(params.hasIQWakeUp) { 324 val wakeupSrcLoadDependency = hasIQWakeupGet.srcWakeupByIQWithoutCancel.map(x => Mux1H(x, hasIQWakeupGet.wakeupLoadDependencyByIQVec)) 325 commonOut.srcWakeUpL1ExuOH.get := (if (isComp) Mux(hasIQWakeupGet.canIssueBypass && !common.canIssue, hasIQWakeupGet.srcWakeupL1ExuOHOut, VecInit(srcWakeupExuOH)) 326 else VecInit(srcWakeupExuOH)) 327 commonOut.srcTimer.get.zipWithIndex.foreach { case (srcTimerOut, srcIdx) => 328 val wakeupByIQOH = hasIQWakeupGet.srcWakeupByIQWithoutCancel(srcIdx) 329 srcTimerOut := Mux(wakeupByIQOH.asUInt.orR, Mux1H(wakeupByIQOH, commonIn.wakeUpFromIQ.map(_.bits.is0Lat).toSeq).asUInt, status.srcStatus(srcIdx).srcTimer.get) 330 } 331 commonOut.srcLoadDependency.zipWithIndex.foreach { case (srcLoadDependencyOut, srcIdx) => 332 srcLoadDependencyOut := (if (isComp) Mux(hasIQWakeupGet.canIssueBypass && !common.canIssue, 333 VecInit(status.srcStatus(srcIdx).srcLoadDependency.zip(wakeupSrcLoadDependency(srcIdx)).map(x => x._1 | x._2)), 334 status.srcStatus(srcIdx).srcLoadDependency) 335 else status.srcStatus(srcIdx).srcLoadDependency) 336 } 337 } else { 338 commonOut.srcLoadDependency.zipWithIndex.foreach { case (srcLoadDependencyOut, srcIdx) => 339 srcLoadDependencyOut := status.srcStatus(srcIdx).srcLoadDependency 340 } 341 } 342 commonOut.entry.bits.status.srcStatus.map(_.srcLoadDependency).zipWithIndex.foreach { case (srcLoadDependencyOut, srcIdx) => 343 srcLoadDependencyOut := (if (isComp) Mux(hasIQWakeupGet.canIssueBypass && !common.canIssue, 344 common.srcLoadDependencyOut(srcIdx), 345 status.srcStatus(srcIdx).srcLoadDependency) 346 else status.srcStatus(srcIdx).srcLoadDependency) 347 } 348 commonOut.enqReady := common.enqReady 349 commonOut.transEntry.valid := validReg && !common.flushed && !common.deqSuccess 350 commonOut.transEntry.bits := entryUpdate 351 commonOut.cancel.foreach(_ := hasIQWakeupGet.cancelVec.asUInt.orR) 352 if (params.isVecMemIQ) { 353 commonOut.uopIdx.get := status.vecMem.get.uopIdx 354 } 355 } 356 357 def EntryMemConnect(commonIn: CommonInBundle, common: CommonWireBundle, validReg: Bool, entryReg: EntryBundle, entryRegNext: EntryBundle, entryUpdate: EntryBundle, isEnq: Boolean)(implicit p: Parameters, params: IssueBlockParams) = { 358 val enqValid = if(isEnq) commonIn.enq.valid && common.enqReady 359 else commonIn.enq.valid 360 val fromMem = commonIn.fromMem.get 361 val memStatus = entryReg.status.mem.get 362 val memStatusNext = entryRegNext.status.mem.get 363 val memStatusUpdate = entryUpdate.status.mem.get 364 365 when(enqValid) { 366 memStatusNext.waitForSqIdx := commonIn.enq.bits.status.mem.get.waitForSqIdx 367 // update by lfst at dispatch stage 368 memStatusNext.waitForRobIdx := commonIn.enq.bits.status.mem.get.waitForRobIdx 369 // new load inst don't known if it is blocked by store data ahead of it 370 memStatusNext.waitForStd := false.B 371 // update by ssit at rename stage 372 memStatusNext.strictWait := commonIn.enq.bits.status.mem.get.strictWait 373 memStatusNext.sqIdx := commonIn.enq.bits.status.mem.get.sqIdx 374 }.otherwise { 375 memStatusNext := memStatusUpdate 376 } 377 378 // load cannot be issued before older store, unless meet some condition 379 val blockedByOlderStore = isAfter(memStatusNext.sqIdx, fromMem.stIssuePtr) 380 381 val deqFailedForStdInvalid = commonIn.issueResp.valid && commonIn.issueResp.bits.respType === RSFeedbackType.dataInvalid 382 383 val staWaitedReleased = Cat( 384 fromMem.memWaitUpdateReq.robIdx.map(x => x.valid && x.bits.value === memStatusNext.waitForRobIdx.value) 385 ).orR 386 val stdWaitedReleased = Cat( 387 fromMem.memWaitUpdateReq.sqIdx.map(x => x.valid && x.bits.value === memStatusNext.waitForSqIdx.value) 388 ).orR 389 val olderStaNotViolate = staWaitedReleased && !memStatusNext.strictWait 390 val olderStdReady = stdWaitedReleased && memStatusNext.waitForStd 391 val waitStd = !olderStdReady 392 val waitSta = !olderStaNotViolate 393 394 memStatusUpdate := memStatus 395 when(deqFailedForStdInvalid) { 396 memStatusUpdate.waitForSqIdx := commonIn.issueResp.bits.dataInvalidSqIdx 397 memStatusUpdate.waitForStd := true.B 398 } 399 400 val shouldBlock = Mux(enqValid, commonIn.enq.bits.status.blocked, entryReg.status.blocked) 401 val blockNotReleased = waitStd || waitSta 402 val respBlock = deqFailedForStdInvalid 403 entryUpdate.status.blocked := shouldBlock && blockNotReleased && blockedByOlderStore || respBlock 404 entryRegNext.status.blocked := entryUpdate.status.blocked 405 } 406 407 def ExuOHGen(exuOH: Vec[Bool], wakeupByIQOH: Vec[Bool], wakeup: Bool, regSrcExuOH: Vec[Bool])(implicit p: Parameters, params: IssueBlockParams) = { 408 val origExuOH = 0.U.asTypeOf(exuOH) 409 when(wakeupByIQOH.asUInt.orR) { 410 origExuOH := Mux1H(wakeupByIQOH, params.wakeUpSourceExuIdx.map(x => MathUtils.IntToOH(x).U(p(XSCoreParamsKey).backendParams.numExu.W)).toSeq).asBools 411 }.elsewhen(wakeup) { 412 origExuOH := 0.U.asTypeOf(origExuOH) 413 }.otherwise { 414 origExuOH := regSrcExuOH 415 } 416 exuOH := 0.U.asTypeOf(exuOH) 417 params.wakeUpSourceExuIdx.foreach(x => exuOH(x) := origExuOH(x)) 418 } 419 420 object IQFuType { 421 def num = FuType.num 422 423 def apply() = Vec(num, Bool()) 424 425 def readFuType(fuType: Vec[Bool], fus: Seq[FuType.OHType]): Vec[Bool] = { 426 val res = 0.U.asTypeOf(fuType) 427 fus.foreach(x => res(x.id) := fuType(x.id)) 428 res 429 } 430 } 431} 432