1package xiangshan.backend.issue 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import utils.{MathUtils, OptionWrapper} 7import utility.HasCircularQueuePtrHelper 8import xiangshan._ 9import xiangshan.backend.Bundles._ 10import xiangshan.backend.datapath.DataSource 11import xiangshan.backend.fu.FuType 12import xiangshan.backend.rob.RobPtr 13import xiangshan.mem.{MemWaitUpdateReq, SqPtr, LqPtr} 14 15object EntryBundles extends HasCircularQueuePtrHelper { 16 17 class Status(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 18 //basic status 19 val robIdx = new RobPtr 20 val fuType = IQFuType() 21 //src status 22 val srcStatus = Vec(params.numRegSrc, new SrcStatus) 23 //issue status 24 val blocked = Bool() 25 val issued = Bool() 26 val firstIssue = Bool() 27 val issueTimer = UInt(2.W) 28 val deqPortIdx = UInt(1.W) 29 //mem status 30 val mem = OptionWrapper(params.isMemAddrIQ, new StatusMemPart) 31 //vector mem status 32 val vecMem = OptionWrapper(params.isVecMemIQ, new StatusVecMemPart) 33 34 def srcReady: Bool = { 35 VecInit(srcStatus.map(_.srcState).map(SrcState.isReady)).asUInt.andR 36 } 37 38 def canIssue: Bool = { 39 srcReady && !issued && !blocked 40 } 41 42 def mergedLoadDependency: Option[Vec[UInt]] = { 43 OptionWrapper(params.hasIQWakeUp, srcStatus.map(_.srcLoadDependency.get).reduce({ 44 case (l: Vec[UInt], r: Vec[UInt]) => VecInit(l.zip(r).map(x => x._1 | x._2)) 45 }: (Vec[UInt], Vec[UInt]) => Vec[UInt])) 46 } 47 } 48 49 class SrcStatus(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 50 val psrc = UInt(params.rdPregIdxWidth.W) 51 val srcType = SrcType() 52 val srcState = SrcState() 53 val dataSources = DataSource() 54 val srcTimer = OptionWrapper(params.hasIQWakeUp, UInt(3.W)) 55 val srcWakeUpL1ExuOH = OptionWrapper(params.hasIQWakeUp, ExuVec()) 56 val srcLoadDependency = OptionWrapper(params.hasIQWakeUp, Vec(LoadPipelineWidth, UInt(3.W))) 57 } 58 59 class StatusMemPart(implicit p:Parameters) extends Bundle { 60 val waitForSqIdx = new SqPtr // generated by store data valid check 61 val waitForRobIdx = new RobPtr // generated by store set 62 val waitForStd = Bool() 63 val strictWait = Bool() 64 val sqIdx = new SqPtr 65 } 66 67 class StatusVecMemPart(implicit p:Parameters, params: IssueBlockParams) extends Bundle { 68 val sqIdx = new SqPtr 69 val lqIdx = new LqPtr 70 val uopIdx = UopIdx() 71 } 72 73 class EntryDeqRespBundle(implicit p: Parameters, params: IssueBlockParams) extends Bundle { 74 val robIdx = new RobPtr 75 val respType = RSFeedbackType() // update credit if needs replay 76 val dataInvalidSqIdx = new SqPtr 77 val rfWen = Bool() 78 val fuType = FuType() 79 val uopIdx = OptionWrapper(params.isVecMemIQ, Output(UopIdx())) 80 } 81 82 class EntryBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 83 val status = new Status() 84 val imm = OptionWrapper(params.needImm, UInt((params.deqImmTypesMaxLen).W)) 85 val payload = new DynInst() 86 } 87 88 class CommonInBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 89 val flush = Flipped(ValidIO(new Redirect)) 90 val enq = Flipped(ValidIO(new EntryBundle)) 91 //wakeup 92 val wakeUpFromWB: MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = Flipped(params.genWBWakeUpSinkValidBundle) 93 val wakeUpFromIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(params.genIQWakeUpSinkValidBundle) 94 //cancel 95 val og0Cancel = Input(ExuOH(backendParams.numExu)) 96 val og1Cancel = Input(ExuOH(backendParams.numExu)) 97 val ldCancel = Vec(backendParams.LdExuCnt, Flipped(new LoadCancelIO)) 98 //deq sel 99 val deqSel = Input(Bool()) 100 val deqPortIdxWrite = Input(UInt(1.W)) 101 val issueResp = Flipped(ValidIO(new EntryDeqRespBundle)) 102 //trans sel 103 val transSel = Input(Bool()) 104 // mem only 105 val fromMem = OptionWrapper(params.isMemAddrIQ, new Bundle { 106 val stIssuePtr = Input(new SqPtr) 107 val memWaitUpdateReq = Flipped(new MemWaitUpdateReq) 108 }) 109 // vector mem only 110 val fromLsq = OptionWrapper(params.isVecMemIQ, new Bundle { 111 val sqDeqPtr = Input(new SqPtr) 112 val lqDeqPtr = Input(new LqPtr) 113 }) 114 } 115 116 class CommonOutBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 117 //status 118 val valid = Output(Bool()) 119 val canIssue = Output(Bool()) 120 val fuType = Output(FuType()) 121 val robIdx = Output(new RobPtr) 122 val uopIdx = OptionWrapper(params.isVecMemIQ, Output(UopIdx())) 123 //src 124 val dataSource = Vec(params.numRegSrc, Output(DataSource())) 125 val srcWakeUpL1ExuOH = OptionWrapper(params.hasIQWakeUp, Vec(params.numRegSrc, Output(ExuVec()))) 126 val srcTimer = OptionWrapper(params.hasIQWakeUp, Vec(params.numRegSrc, Output(UInt(3.W)))) 127 val srcLoadDependency = OptionWrapper(params.hasIQWakeUp, Vec(params.numRegSrc, Output(Vec(LoadPipelineWidth, UInt(3.W))))) 128 //deq 129 val isFirstIssue = Output(Bool()) 130 val entry = ValidIO(new EntryBundle) 131 val deqPortIdxRead = Output(UInt(1.W)) 132 val issueTimerRead = Output(UInt(2.W)) 133 //trans 134 val enqReady = Output(Bool()) 135 val transEntry = ValidIO(new EntryBundle) 136 // debug 137 val cancel = OptionWrapper(params.hasIQWakeUp, Output(Bool())) 138 } 139 140 class CommonWireBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 141 val validRegNext = Bool() 142 val flushed = Bool() 143 val clear = Bool() 144 val canIssue = Bool() 145 val enqReady = Bool() 146 val deqSuccess = Bool() 147 val srcWakeup = Vec(params.numRegSrc, Bool()) 148 val srcWakeupByWB = Vec(params.numRegSrc, Bool()) 149 } 150 151 def CommonWireConnect(common: CommonWireBundle, hasIQWakeup: Option[CommonIQWakeupBundle], validReg: Bool, status: Status, commonIn: CommonInBundle, isEnq: Boolean)(implicit p: Parameters, params: IssueBlockParams) = { 152 val hasIQWakeupGet = hasIQWakeup.getOrElse(0.U.asTypeOf(new CommonIQWakeupBundle)) 153 common.flushed := status.robIdx.needFlush(commonIn.flush) 154 common.deqSuccess := commonIn.issueResp.valid && commonIn.issueResp.bits.respType === RSFeedbackType.fuIdle && !hasIQWakeupGet.srcLoadCancelVec.asUInt.orR 155 common.srcWakeup := common.srcWakeupByWB.zip(hasIQWakeupGet.srcWakeupByIQ).map { case (x, y) => x || y.asUInt.orR } 156 common.srcWakeupByWB := commonIn.wakeUpFromWB.map(bundle => bundle.bits.wakeUp(status.srcStatus.map(_.psrc) zip status.srcStatus.map(_.srcType), bundle.valid)).transpose.map(x => VecInit(x.toSeq).asUInt.orR).toSeq 157 common.canIssue := validReg && status.canIssue 158 common.enqReady := !validReg || common.clear 159 if(isEnq) { 160 common.validRegNext := Mux(commonIn.enq.valid && common.enqReady, true.B, Mux(common.clear, false.B, validReg)) 161 common.clear := common.flushed || common.deqSuccess || commonIn.transSel 162 } else { 163 common.validRegNext := Mux(commonIn.enq.valid && commonIn.transSel, true.B, Mux(common.clear, false.B, validReg)) 164 common.clear := common.flushed || common.deqSuccess 165 } 166 } 167 168 class CommonIQWakeupBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 169 val srcWakeupByIQ = Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool())) 170 val srcWakeupByIQWithoutCancel = Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool())) 171 val srcWakeupByIQButCancel = Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool())) 172 val regSrcWakeupL1ExuOH = Vec(params.numRegSrc, ExuVec()) 173 val srcWakeupL1ExuOHOut = Vec(params.numRegSrc, ExuVec()) 174 val srcLoadDependencyOut = Vec(params.numRegSrc, Vec(LoadPipelineWidth, UInt(3.W))) 175 val wakeupLoadDependencyByIQVec = Vec(params.numWakeupFromIQ, Vec(LoadPipelineWidth, UInt(3.W))) 176 val shiftedWakeupLoadDependencyByIQVec = Vec(params.numWakeupFromIQ, Vec(LoadPipelineWidth, UInt(3.W))) 177 val shiftedWakeupLoadDependencyByIQBypassVec = Vec(params.numWakeupFromIQ, Vec(LoadPipelineWidth, UInt(3.W))) 178 val cancelVec = Vec(params.numRegSrc, Bool()) 179 val srcCancelVec = Vec(params.numRegSrc, Bool()) 180 val srcLoadCancelVec = Vec(params.numRegSrc, Bool()) 181 val canIssueBypass = Bool() 182 } 183 184 def CommonIQWakeupConnect(common: CommonWireBundle, hasIQWakeupGet: CommonIQWakeupBundle, validReg: Bool, status: Status, commonIn: CommonInBundle, isEnq: Boolean)(implicit p: Parameters, params: IssueBlockParams) = { 185 val wakeupVec: Seq[Seq[Bool]] = commonIn.wakeUpFromIQ.map((bundle: ValidIO[IssueQueueIQWakeUpBundle]) => 186 bundle.bits.wakeUpFromIQ(status.srcStatus.map(_.psrc) zip status.srcStatus.map(_.srcType)) 187 ).toSeq.transpose 188 val cancelSel = params.wakeUpSourceExuIdx.zip(commonIn.wakeUpFromIQ).map { case (x, y) => commonIn.og0Cancel(x) && y.bits.is0Lat } 189 190 hasIQWakeupGet.srcCancelVec.zip(hasIQWakeupGet.srcLoadCancelVec).zip(hasIQWakeupGet.srcWakeupByIQWithoutCancel).zipWithIndex.foreach { case (((srcCancel, srcLoadCancel), wakeUpByIQVec), srcIdx) => 191 val ldTransCancel = Mux1H(wakeUpByIQVec, hasIQWakeupGet.wakeupLoadDependencyByIQVec.map(dep => LoadShouldCancel(Some(dep), commonIn.ldCancel))) 192 srcLoadCancel := LoadShouldCancel(status.srcStatus(srcIdx).srcLoadDependency, commonIn.ldCancel) 193 srcCancel := srcLoadCancel || ldTransCancel 194 } 195 hasIQWakeupGet.cancelVec := hasIQWakeupGet.srcCancelVec 196 hasIQWakeupGet.srcWakeupByIQ := wakeupVec.map(x => VecInit(x.zip(cancelSel).map { case (wakeup, cancel) => wakeup && !cancel })) 197 hasIQWakeupGet.srcWakeupByIQButCancel := wakeupVec.map(x => VecInit(x.zip(cancelSel).map { case (wakeup, cancel) => wakeup && cancel })) 198 hasIQWakeupGet.srcWakeupByIQWithoutCancel := wakeupVec.map(x => VecInit(x)) 199 hasIQWakeupGet.wakeupLoadDependencyByIQVec := commonIn.wakeUpFromIQ.map(_.bits.loadDependency).toSeq 200 hasIQWakeupGet.regSrcWakeupL1ExuOH.zip(status.srcStatus.map(_.srcWakeUpL1ExuOH.get)).foreach { 201 case (exuOH, regExuOH) => 202 exuOH := 0.U.asTypeOf(exuOH) 203 params.wakeUpSourceExuIdx.foreach(x => exuOH(x) := regExuOH(x)) 204 } 205 hasIQWakeupGet.srcWakeupL1ExuOHOut.zip(hasIQWakeupGet.srcWakeupByIQWithoutCancel).zip(common.srcWakeup).zipWithIndex.foreach { 206 case (((exuOH: Vec[Bool], wakeUpByIQOH: Vec[Bool]), wakeUp: Bool), srcIdx) => 207 if(isEnq) { 208 ExuOHGen(exuOH, wakeUpByIQOH, wakeUp, status.srcStatus(srcIdx).srcWakeUpL1ExuOH.get) 209 } else { 210 ExuOHGen(exuOH, wakeUpByIQOH, wakeUp, hasIQWakeupGet.regSrcWakeupL1ExuOH(srcIdx)) 211 } 212 } 213 hasIQWakeupGet.srcLoadDependencyOut.zip(hasIQWakeupGet.srcWakeupByIQ).foreach { 214 case (loadDependencyOut, wakeUpByIQVec) => 215 loadDependencyOut := Mux1H(wakeUpByIQVec, hasIQWakeupGet.shiftedWakeupLoadDependencyByIQBypassVec) 216 } 217 hasIQWakeupGet.canIssueBypass := validReg && !status.issued && !status.blocked && 218 VecInit(status.srcStatus.map(_.srcState).zip(hasIQWakeupGet.srcWakeupByIQWithoutCancel).zipWithIndex.map { case ((state, wakeupVec), srcIdx) => 219 wakeupVec.asUInt.orR | state 220 }).asUInt.andR 221 } 222 223 224 def ShiftLoadDependency(hasIQWakeupGet: CommonIQWakeupBundle)(implicit p: Parameters, params: IssueBlockParams) = { 225 hasIQWakeupGet.shiftedWakeupLoadDependencyByIQVec 226 .zip(hasIQWakeupGet.wakeupLoadDependencyByIQVec) 227 .zip(params.wakeUpInExuSources.map(_.name)).foreach { 228 case ((deps, originalDeps), name) => deps.zip(originalDeps).zipWithIndex.foreach { 229 case ((dep, originalDep), deqPortIdx) => 230 if (name.contains("LDU") && name.replace("LDU", "").toInt == deqPortIdx) 231 dep := (originalDep << 2).asUInt | 2.U 232 else 233 dep := originalDep << 1 234 } 235 } 236 hasIQWakeupGet.shiftedWakeupLoadDependencyByIQBypassVec 237 .zip(hasIQWakeupGet.wakeupLoadDependencyByIQVec) 238 .zip(params.wakeUpInExuSources.map(_.name)).foreach { 239 case ((deps, originalDeps), name) => deps.zip(originalDeps).zipWithIndex.foreach { 240 case ((dep, originalDep), deqPortIdx) => 241 if (name.contains("LDU") && name.replace("LDU", "").toInt == deqPortIdx) 242 dep := (originalDep << 1).asUInt | 1.U 243 else 244 dep := originalDep 245 } 246 } 247 } 248 249 def EntryRegCommonConnect(common: CommonWireBundle, hasIQWakeup: Option[CommonIQWakeupBundle], validReg: Bool, entryUpdate: EntryBundle, entryReg: EntryBundle, status: Status, commonIn: CommonInBundle, isEnq: Boolean)(implicit p: Parameters, params: IssueBlockParams) = { 250 val hasIQWakeupGet = hasIQWakeup.getOrElse(0.U.asTypeOf(new CommonIQWakeupBundle)) 251 val cancelByLd = hasIQWakeupGet.srcCancelVec.asUInt.orR 252 val cancelWhenWakeup = VecInit(hasIQWakeupGet.srcWakeupByIQButCancel.map(_.asUInt.orR)).asUInt.orR 253 val respIssueFail = commonIn.issueResp.valid && RSFeedbackType.isBlocked(commonIn.issueResp.bits.respType) 254 val srcWakeupExuOH = if(isEnq) status.srcStatus.map(_.srcWakeUpL1ExuOH.getOrElse(0.U.asTypeOf(ExuVec()))) else hasIQWakeupGet.regSrcWakeupL1ExuOH 255 entryUpdate.status.robIdx := status.robIdx 256 entryUpdate.status.fuType := IQFuType.readFuType(status.fuType, params.getFuCfgs.map(_.fuType)) 257 entryUpdate.status.srcStatus.zip(status.srcStatus).zipWithIndex.foreach { case ((srcStatusNext, srcStatus), srcIdx) => 258 val cancel = hasIQWakeupGet.srcCancelVec(srcIdx) 259 val wakeupByIQ = hasIQWakeupGet.srcWakeupByIQ(srcIdx).asUInt.orR 260 val wakeupByIQOH = hasIQWakeupGet.srcWakeupByIQ(srcIdx) 261 val wakeup = common.srcWakeup(srcIdx) 262 srcStatusNext.psrc := srcStatus.psrc 263 srcStatusNext.srcType := srcStatus.srcType 264 srcStatusNext.srcState := Mux(cancel, false.B, wakeup | srcStatus.srcState) 265 srcStatusNext.dataSources.value := Mux(wakeupByIQ, DataSource.bypass, DataSource.reg) 266 if(params.hasIQWakeUp) { 267 srcStatusNext.srcTimer.get := MuxCase(3.U, Seq( 268 // T0: waked up by IQ, T1: reset timer as 1 269 wakeupByIQ -> 2.U, 270 // do not overflow 271 srcStatus.srcTimer.get.andR -> srcStatus.srcTimer.get, 272 // T2+: increase if the entry is valid, the src is ready, and the src is woken up by iq 273 (validReg && SrcState.isReady(srcStatus.srcState) && srcWakeupExuOH(srcIdx).asUInt.orR) -> (srcStatus.srcTimer.get + 1.U) 274 )) 275 ExuOHGen(srcStatusNext.srcWakeUpL1ExuOH.get, wakeupByIQOH, wakeup, srcWakeupExuOH(srcIdx)) 276 srcStatusNext.srcLoadDependency.get := 277 Mux(wakeup, 278 Mux1H(wakeupByIQOH, hasIQWakeupGet.shiftedWakeupLoadDependencyByIQVec), 279 Mux(validReg && srcStatus.srcLoadDependency.get.asUInt.orR, VecInit(srcStatus.srcLoadDependency.get.map(i => i(i.getWidth - 2, 0) << 1)), srcStatus.srcLoadDependency.get)) 280 } 281 } 282 entryUpdate.status.blocked := false.B 283 entryUpdate.status.issued := MuxCase(status.issued, Seq( 284 (cancelByLd || cancelWhenWakeup || respIssueFail) -> false.B, 285 commonIn.deqSel -> true.B, 286 !status.srcReady -> false.B, 287 )) 288 entryUpdate.status.firstIssue := commonIn.deqSel || status.firstIssue 289 entryUpdate.status.issueTimer := Mux(commonIn.deqSel, 0.U, Mux(status.issued, status.issueTimer + 1.U, "b10".U)) 290 entryUpdate.status.deqPortIdx := Mux(commonIn.deqSel, commonIn.deqPortIdxWrite, Mux(status.issued, status.deqPortIdx, 0.U)) 291 entryUpdate.imm.foreach(_ := entryReg.imm.get) 292 entryUpdate.payload := entryReg.payload 293 if (params.isVecMemIQ) { 294 entryUpdate.status.vecMem.get := entryReg.status.vecMem.get 295 } 296 } 297 298 def CommonOutConnect(commonOut: CommonOutBundle, common: CommonWireBundle, hasIQWakeup: Option[CommonIQWakeupBundle], validReg: Bool, entryUpdate: EntryBundle, entryReg: EntryBundle, status: Status, commonIn: CommonInBundle, isEnq: Boolean, isComp: Boolean)(implicit p: Parameters, params: IssueBlockParams) = { 299 val hasIQWakeupGet = hasIQWakeup.getOrElse(0.U.asTypeOf(new CommonIQWakeupBundle)) 300 val srcWakeupExuOH = if(isEnq) status.srcStatus.map(_.srcWakeUpL1ExuOH.getOrElse(0.U.asTypeOf(ExuVec()))) else hasIQWakeupGet.regSrcWakeupL1ExuOH 301 commonOut.valid := validReg 302 commonOut.canIssue := (if (isComp) (common.canIssue || hasIQWakeupGet.canIssueBypass) && !common.flushed 303 else common.canIssue && !common.flushed) 304 commonOut.fuType := IQFuType.readFuType(status.fuType, params.getFuCfgs.map(_.fuType)).asUInt 305 commonOut.robIdx := status.robIdx 306 commonOut.dataSource.zipWithIndex.foreach{ case (dataSourceOut, srcIdx) => 307 dataSourceOut.value := Mux(hasIQWakeupGet.srcWakeupByIQ(srcIdx).asUInt.orR, DataSource.forward, status.srcStatus(srcIdx).dataSources.value) 308 } 309 commonOut.isFirstIssue := !status.firstIssue 310 commonOut.entry.valid := validReg 311 commonOut.entry.bits := entryReg 312 if(isEnq) { 313 commonOut.entry.bits.status := status 314 } 315 commonOut.issueTimerRead := status.issueTimer 316 commonOut.deqPortIdxRead := status.deqPortIdx 317 if(params.hasIQWakeUp) { 318 val wakeupSrcLoadDependency = hasIQWakeupGet.srcWakeupByIQWithoutCancel.map(x => Mux1H(x, hasIQWakeupGet.wakeupLoadDependencyByIQVec)) 319 commonOut.srcWakeUpL1ExuOH.get := (if (isComp) Mux(hasIQWakeupGet.canIssueBypass && !common.canIssue, hasIQWakeupGet.srcWakeupL1ExuOHOut, VecInit(srcWakeupExuOH)) 320 else VecInit(srcWakeupExuOH)) 321 commonOut.srcTimer.get.zipWithIndex.foreach { case (srcTimerOut, srcIdx) => 322 val wakeupByIQOH = hasIQWakeupGet.srcWakeupByIQWithoutCancel(srcIdx) 323 srcTimerOut := Mux(wakeupByIQOH.asUInt.orR, Mux1H(wakeupByIQOH, commonIn.wakeUpFromIQ.map(_.bits.is0Lat).toSeq).asUInt, status.srcStatus(srcIdx).srcTimer.get) 324 } 325 commonOut.entry.bits.status.srcStatus.map(_.srcLoadDependency.get).zipWithIndex.foreach { case (srcLoadDependencyOut, srcIdx) => 326 srcLoadDependencyOut := (if (isComp) Mux(hasIQWakeupGet.canIssueBypass && !common.canIssue, 327 hasIQWakeupGet.srcLoadDependencyOut(srcIdx), 328 status.srcStatus(srcIdx).srcLoadDependency.get) 329 else status.srcStatus(srcIdx).srcLoadDependency.get) 330 } 331 commonOut.srcLoadDependency.get.zipWithIndex.foreach { case (srcLoadDependencyOut, srcIdx) => 332 srcLoadDependencyOut := (if (isComp) Mux(hasIQWakeupGet.canIssueBypass && !common.canIssue, 333 VecInit(status.srcStatus(srcIdx).srcLoadDependency.get.zip(wakeupSrcLoadDependency(srcIdx)).map(x => x._1 | x._2)), 334 status.srcStatus(srcIdx).srcLoadDependency.get) 335 else status.srcStatus(srcIdx).srcLoadDependency.get) 336 } 337 } 338 commonOut.enqReady := common.enqReady 339 commonOut.transEntry.valid := validReg && !common.flushed && !common.deqSuccess 340 commonOut.transEntry.bits := entryUpdate 341 commonOut.cancel.foreach(_ := hasIQWakeupGet.cancelVec.asUInt.orR) 342 if (params.isVecMemIQ) { 343 commonOut.uopIdx.get := status.vecMem.get.uopIdx 344 } 345 } 346 347 def EntryMemConnect(commonIn: CommonInBundle, common: CommonWireBundle, validReg: Bool, entryReg: EntryBundle, entryRegNext: EntryBundle, entryUpdate: EntryBundle, isEnq: Boolean)(implicit p: Parameters, params: IssueBlockParams) = { 348 val enqValid = if(isEnq) commonIn.enq.valid && common.enqReady 349 else commonIn.enq.valid && commonIn.transSel 350 val fromMem = commonIn.fromMem.get 351 val memStatus = entryReg.status.mem.get 352 val memStatusNext = entryRegNext.status.mem.get 353 val memStatusUpdate = entryUpdate.status.mem.get 354 355 when(enqValid) { 356 memStatusNext.waitForSqIdx := commonIn.enq.bits.status.mem.get.waitForSqIdx 357 // update by lfst at dispatch stage 358 memStatusNext.waitForRobIdx := commonIn.enq.bits.status.mem.get.waitForRobIdx 359 // new load inst don't known if it is blocked by store data ahead of it 360 memStatusNext.waitForStd := false.B 361 // update by ssit at rename stage 362 memStatusNext.strictWait := commonIn.enq.bits.status.mem.get.strictWait 363 memStatusNext.sqIdx := commonIn.enq.bits.status.mem.get.sqIdx 364 }.otherwise { 365 memStatusNext := memStatusUpdate 366 } 367 368 // load cannot be issued before older store, unless meet some condition 369 val blockedByOlderStore = isAfter(memStatusNext.sqIdx, fromMem.stIssuePtr) 370 371 val deqFailedForStdInvalid = commonIn.issueResp.valid && commonIn.issueResp.bits.respType === RSFeedbackType.dataInvalid 372 373 val staWaitedReleased = Cat( 374 fromMem.memWaitUpdateReq.robIdx.map(x => x.valid && x.bits.value === memStatusNext.waitForRobIdx.value) 375 ).orR 376 val stdWaitedReleased = Cat( 377 fromMem.memWaitUpdateReq.sqIdx.map(x => x.valid && x.bits.value === memStatusNext.waitForSqIdx.value) 378 ).orR 379 val olderStaNotViolate = staWaitedReleased && !memStatusNext.strictWait 380 val olderStdReady = stdWaitedReleased && memStatusNext.waitForStd 381 val waitStd = !olderStdReady 382 val waitSta = !olderStaNotViolate 383 384 memStatusUpdate := memStatus 385 when(deqFailedForStdInvalid) { 386 memStatusUpdate.waitForSqIdx := commonIn.issueResp.bits.dataInvalidSqIdx 387 memStatusUpdate.waitForStd := true.B 388 } 389 390 val shouldBlock = Mux(enqValid, commonIn.enq.bits.status.blocked, entryReg.status.blocked) 391 val blockNotReleased = waitStd || waitSta 392 val respBlock = deqFailedForStdInvalid 393 entryUpdate.status.blocked := shouldBlock && blockNotReleased && blockedByOlderStore || respBlock 394 entryRegNext.status.blocked := entryUpdate.status.blocked 395 } 396 397 def ExuOHGen(exuOH: Vec[Bool], wakeupByIQOH: Vec[Bool], wakeup: Bool, regSrcExuOH: Vec[Bool])(implicit p: Parameters, params: IssueBlockParams) = { 398 val origExuOH = 0.U.asTypeOf(exuOH) 399 when(wakeupByIQOH.asUInt.orR) { 400 origExuOH := Mux1H(wakeupByIQOH, params.wakeUpSourceExuIdx.map(x => MathUtils.IntToOH(x).U(p(XSCoreParamsKey).backendParams.numExu.W)).toSeq).asBools 401 }.elsewhen(wakeup) { 402 origExuOH := 0.U.asTypeOf(origExuOH) 403 }.otherwise { 404 origExuOH := regSrcExuOH 405 } 406 exuOH := 0.U.asTypeOf(exuOH) 407 params.wakeUpSourceExuIdx.foreach(x => exuOH(x) := origExuOH(x)) 408 } 409 410 object IQFuType { 411 def num = FuType.num 412 413 def apply() = Vec(num, Bool()) 414 415 def readFuType(fuType: Vec[Bool], fus: Seq[FuType.OHType]): Vec[Bool] = { 416 val res = 0.U.asTypeOf(fuType) 417 fus.foreach(x => res(x.id) := fuType(x.id)) 418 res 419 } 420 } 421} 422