1package xiangshan.backend.issue 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import utils.{MathUtils, OptionWrapper} 7import utility.HasCircularQueuePtrHelper 8import xiangshan._ 9import xiangshan.backend.Bundles._ 10import xiangshan.backend.datapath.DataSource 11import xiangshan.backend.fu.FuType 12import xiangshan.backend.rob.RobPtr 13import xiangshan.mem.{MemWaitUpdateReq, SqPtr, LqPtr} 14 15object EntryBundles extends HasCircularQueuePtrHelper { 16 17 class Status(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 18 //basic status 19 val robIdx = new RobPtr 20 val fuType = IQFuType() 21 //src status 22 val srcStatus = Vec(params.numRegSrc, new SrcStatus) 23 //issue status 24 val blocked = Bool() 25 val issued = Bool() 26 val firstIssue = Bool() 27 val issueTimer = UInt(2.W) 28 val deqPortIdx = UInt(1.W) 29 //vector mem status 30 val vecMem = OptionWrapper(params.isVecMemIQ, new StatusVecMemPart) 31 32 def srcReady: Bool = { 33 VecInit(srcStatus.map(_.srcState).map(SrcState.isReady)).asUInt.andR 34 } 35 36 def canIssue: Bool = { 37 srcReady && !issued && !blocked 38 } 39 40 def mergedLoadDependency: Vec[UInt] = { 41 srcStatus.map(_.srcLoadDependency).reduce({ 42 case (l: Vec[UInt], r: Vec[UInt]) => VecInit(l.zip(r).map(x => x._1 | x._2)) 43 }: (Vec[UInt], Vec[UInt]) => Vec[UInt]) 44 } 45 } 46 47 class SrcStatus(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 48 val psrc = UInt(params.rdPregIdxWidth.W) 49 val srcType = SrcType() 50 val srcState = SrcState() 51 val dataSources = DataSource() 52 val srcLoadDependency = Vec(LoadPipelineWidth, UInt(3.W)) 53 val srcWakeUpL1ExuOH = OptionWrapper(params.hasIQWakeUp, ExuVec()) 54 } 55 56 class StatusVecMemPart(implicit p:Parameters, params: IssueBlockParams) extends Bundle { 57 val sqIdx = new SqPtr 58 val lqIdx = new LqPtr 59 } 60 61 class EntryDeqRespBundle(implicit p: Parameters, params: IssueBlockParams) extends Bundle { 62 val robIdx = new RobPtr 63 val resp = RespType() 64 val fuType = FuType() 65 val uopIdx = OptionWrapper(params.isVecMemIQ, Output(UopIdx())) 66 } 67 68 object RespType { 69 def apply() = UInt(2.W) 70 71 def isBlocked(resp: UInt) = { 72 resp === block 73 } 74 75 def succeed(resp: UInt) = { 76 resp === success 77 } 78 79 val block = "b00".U 80 val uncertain = "b01".U 81 val success = "b11".U 82 } 83 84 class EntryBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 85 val status = new Status() 86 val imm = OptionWrapper(params.needImm, UInt((params.deqImmTypesMaxLen).W)) 87 val payload = new DynInst() 88 } 89 90 class CommonInBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 91 val flush = Flipped(ValidIO(new Redirect)) 92 val enq = Flipped(ValidIO(new EntryBundle)) 93 //wakeup 94 val wakeUpFromWB: MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = Flipped(params.genWBWakeUpSinkValidBundle) 95 val wakeUpFromIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(params.genIQWakeUpSinkValidBundle) 96 //cancel 97 val og0Cancel = Input(ExuOH(backendParams.numExu)) 98 val og1Cancel = Input(ExuOH(backendParams.numExu)) 99 val ldCancel = Vec(backendParams.LdExuCnt, Flipped(new LoadCancelIO)) 100 //deq sel 101 val deqSel = Input(Bool()) 102 val deqPortIdxWrite = Input(UInt(1.W)) 103 val issueResp = Flipped(ValidIO(new EntryDeqRespBundle)) 104 //trans sel 105 val transSel = Input(Bool()) 106 // vector mem only 107 val fromLsq = OptionWrapper(params.isVecMemIQ, new Bundle { 108 val sqDeqPtr = Input(new SqPtr) 109 val lqDeqPtr = Input(new LqPtr) 110 }) 111 } 112 113 class CommonOutBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 114 //status 115 val valid = Output(Bool()) 116 val canIssue = Output(Bool()) 117 val fuType = Output(FuType()) 118 val robIdx = Output(new RobPtr) 119 val uopIdx = OptionWrapper(params.isVecMemIQ, Output(UopIdx())) 120 //src 121 val dataSource = Vec(params.numRegSrc, Output(DataSource())) 122 val srcLoadDependency = Vec(params.numRegSrc, Output(Vec(LoadPipelineWidth, UInt(3.W)))) 123 val srcWakeUpL1ExuOH = OptionWrapper(params.hasIQWakeUp, Vec(params.numRegSrc, Output(ExuVec()))) 124 //deq 125 val isFirstIssue = Output(Bool()) 126 val entry = ValidIO(new EntryBundle) 127 val deqPortIdxRead = Output(UInt(1.W)) 128 val issueTimerRead = Output(UInt(2.W)) 129 //trans 130 val enqReady = Output(Bool()) 131 val transEntry = ValidIO(new EntryBundle) 132 // debug 133 val entryInValid = Output(Bool()) 134 val entryOutDeqValid = Output(Bool()) 135 val entryOutTransValid = Output(Bool()) 136 val perfLdCancel = OptionWrapper(params.hasIQWakeUp, Output(Vec(params.numRegSrc, Bool()))) 137 val perfOg0Cancel = OptionWrapper(params.hasIQWakeUp, Output(Vec(params.numRegSrc, Bool()))) 138 val perfWakeupByWB = Output(Vec(params.numRegSrc, Bool())) 139 val perfWakeupByIQ = OptionWrapper(params.hasIQWakeUp, Output(Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool())))) 140 } 141 142 class CommonWireBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 143 val validRegNext = Bool() 144 val flushed = Bool() 145 val clear = Bool() 146 val canIssue = Bool() 147 val enqReady = Bool() 148 val deqSuccess = Bool() 149 val srcWakeup = Vec(params.numRegSrc, Bool()) 150 val srcWakeupByWB = Vec(params.numRegSrc, Bool()) 151 val srcLoadDependencyOut = Vec(params.numRegSrc, Vec(LoadPipelineWidth, UInt(3.W))) 152 val srcCancelVec = Vec(params.numRegSrc, Bool()) 153 val srcLoadCancelVec = Vec(params.numRegSrc, Bool()) 154 } 155 156 def CommonWireConnect(common: CommonWireBundle, hasIQWakeup: Option[CommonIQWakeupBundle], validReg: Bool, status: Status, commonIn: CommonInBundle, isEnq: Boolean)(implicit p: Parameters, params: IssueBlockParams) = { 157 val hasIQWakeupGet = hasIQWakeup.getOrElse(0.U.asTypeOf(new CommonIQWakeupBundle)) 158 common.flushed := status.robIdx.needFlush(commonIn.flush) 159 common.deqSuccess := commonIn.issueResp.valid && RespType.succeed(commonIn.issueResp.bits.resp) && !common.srcLoadCancelVec.asUInt.orR 160 common.srcWakeup := common.srcWakeupByWB.zip(hasIQWakeupGet.srcWakeupByIQ).map { case (x, y) => x || y.asUInt.orR } 161 common.srcWakeupByWB := commonIn.wakeUpFromWB.map(bundle => bundle.bits.wakeUp(status.srcStatus.map(_.psrc) zip status.srcStatus.map(_.srcType), bundle.valid)).transpose.map(x => VecInit(x.toSeq).asUInt.orR).toSeq 162 common.canIssue := validReg && status.canIssue 163 common.enqReady := !validReg || common.clear 164 common.clear := common.flushed || common.deqSuccess || commonIn.transSel 165 common.srcCancelVec.zip(common.srcLoadCancelVec).zip(hasIQWakeupGet.srcWakeupByIQWithoutCancel).zipWithIndex.foreach { case (((srcCancel, srcLoadCancel), wakeUpByIQVec), srcIdx) => 166 val ldTransCancel = if(params.hasIQWakeUp) Mux1H(wakeUpByIQVec, hasIQWakeupGet.wakeupLoadDependencyByIQVec.map(dep => LoadShouldCancel(Some(dep), commonIn.ldCancel))) else false.B 167 srcLoadCancel := LoadShouldCancel(Some(status.srcStatus(srcIdx).srcLoadDependency), commonIn.ldCancel) 168 srcCancel := srcLoadCancel || ldTransCancel 169 } 170 common.srcLoadDependencyOut.zip(hasIQWakeupGet.srcWakeupByIQ).zip(status.srcStatus.map(_.srcLoadDependency)).foreach { 171 case ((loadDependencyOut, wakeUpByIQVec), loadDependency) => 172 if(params.hasIQWakeUp) { 173 loadDependencyOut := Mux(wakeUpByIQVec.asUInt.orR, Mux1H(wakeUpByIQVec, hasIQWakeupGet.shiftedWakeupLoadDependencyByIQBypassVec), loadDependency) 174 } else { 175 loadDependencyOut := loadDependency 176 } 177 178 } 179 if(isEnq) { 180 common.validRegNext := Mux(commonIn.enq.valid && common.enqReady, true.B, Mux(common.clear, false.B, validReg)) 181 } else { 182 common.validRegNext := Mux(commonIn.enq.valid, true.B, Mux(common.clear, false.B, validReg)) 183 } 184 } 185 186 class CommonIQWakeupBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 187 val srcWakeupByIQ = Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool())) 188 val srcWakeupByIQWithoutCancel = Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool())) 189 val srcWakeupByIQButCancel = Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool())) 190 val regSrcWakeupL1ExuOH = Vec(params.numRegSrc, ExuVec()) 191 val srcWakeupL1ExuOHOut = Vec(params.numRegSrc, ExuVec()) 192 val wakeupLoadDependencyByIQVec = Vec(params.numWakeupFromIQ, Vec(LoadPipelineWidth, UInt(3.W))) 193 val shiftedWakeupLoadDependencyByIQVec = Vec(params.numWakeupFromIQ, Vec(LoadPipelineWidth, UInt(3.W))) 194 val shiftedWakeupLoadDependencyByIQBypassVec = Vec(params.numWakeupFromIQ, Vec(LoadPipelineWidth, UInt(3.W))) 195 val cancelVec = Vec(params.numRegSrc, Bool()) 196 val canIssueBypass = Bool() 197 } 198 199 def CommonIQWakeupConnect(common: CommonWireBundle, hasIQWakeupGet: CommonIQWakeupBundle, validReg: Bool, status: Status, commonIn: CommonInBundle, isEnq: Boolean)(implicit p: Parameters, params: IssueBlockParams) = { 200 val wakeupVec: Seq[Seq[Bool]] = commonIn.wakeUpFromIQ.map((bundle: ValidIO[IssueQueueIQWakeUpBundle]) => 201 bundle.bits.wakeUpFromIQ(status.srcStatus.map(_.psrc) zip status.srcStatus.map(_.srcType)) 202 ).toSeq.transpose 203 val cancelSel = params.wakeUpSourceExuIdx.zip(commonIn.wakeUpFromIQ).map { case (x, y) => commonIn.og0Cancel(x) && y.bits.is0Lat } 204 205 hasIQWakeupGet.cancelVec := common.srcCancelVec 206 hasIQWakeupGet.srcWakeupByIQ := wakeupVec.map(x => VecInit(x.zip(cancelSel).map { case (wakeup, cancel) => wakeup && !cancel })) 207 hasIQWakeupGet.srcWakeupByIQButCancel := wakeupVec.map(x => VecInit(x.zip(cancelSel).map { case (wakeup, cancel) => wakeup && cancel })) 208 hasIQWakeupGet.srcWakeupByIQWithoutCancel := wakeupVec.map(x => VecInit(x)) 209 hasIQWakeupGet.wakeupLoadDependencyByIQVec := commonIn.wakeUpFromIQ.map(_.bits.loadDependency).toSeq 210 hasIQWakeupGet.regSrcWakeupL1ExuOH.zip(status.srcStatus.map(_.srcWakeUpL1ExuOH.get)).foreach { 211 case (exuOH, regExuOH) => 212 exuOH := 0.U.asTypeOf(exuOH) 213 params.wakeUpSourceExuIdx.foreach(x => exuOH(x) := regExuOH(x)) 214 } 215 hasIQWakeupGet.srcWakeupL1ExuOHOut.zip(hasIQWakeupGet.srcWakeupByIQWithoutCancel).zip(common.srcWakeup).zipWithIndex.foreach { 216 case (((exuOH: Vec[Bool], wakeUpByIQOH: Vec[Bool]), wakeUp: Bool), srcIdx) => 217 if(isEnq) { 218 ExuOHGen(exuOH, wakeUpByIQOH, wakeUp, status.srcStatus(srcIdx).srcWakeUpL1ExuOH.get) 219 } else { 220 ExuOHGen(exuOH, wakeUpByIQOH, wakeUp, hasIQWakeupGet.regSrcWakeupL1ExuOH(srcIdx)) 221 } 222 } 223 hasIQWakeupGet.canIssueBypass := validReg && !status.issued && !status.blocked && 224 VecInit(status.srcStatus.map(_.srcState).zip(hasIQWakeupGet.srcWakeupByIQWithoutCancel).zipWithIndex.map { case ((state, wakeupVec), srcIdx) => 225 wakeupVec.asUInt.orR | state 226 }).asUInt.andR 227 } 228 229 230 def ShiftLoadDependency(hasIQWakeupGet: CommonIQWakeupBundle)(implicit p: Parameters, params: IssueBlockParams) = { 231 hasIQWakeupGet.shiftedWakeupLoadDependencyByIQVec 232 .zip(hasIQWakeupGet.wakeupLoadDependencyByIQVec) 233 .zip(params.wakeUpInExuSources.map(_.name)).foreach { 234 case ((deps, originalDeps), name) => deps.zip(originalDeps).zipWithIndex.foreach { 235 case ((dep, originalDep), deqPortIdx) => 236 if (params.backendParam.getLdExuIdx(params.backendParam.allExuParams.find(_.name == name).get) == deqPortIdx) 237 dep := 2.U 238 else 239 dep := originalDep << 1 240 } 241 } 242 hasIQWakeupGet.shiftedWakeupLoadDependencyByIQBypassVec 243 .zip(hasIQWakeupGet.wakeupLoadDependencyByIQVec) 244 .zip(params.wakeUpInExuSources.map(_.name)).foreach { 245 case ((deps, originalDeps), name) => deps.zip(originalDeps).zipWithIndex.foreach { 246 case ((dep, originalDep), deqPortIdx) => 247 if (params.backendParam.getLdExuIdx(params.backendParam.allExuParams.find(_.name == name).get) == deqPortIdx) 248 dep := 1.U 249 else 250 dep := originalDep 251 } 252 } 253 } 254 255 def EntryRegCommonConnect(common: CommonWireBundle, hasIQWakeup: Option[CommonIQWakeupBundle], validReg: Bool, entryUpdate: EntryBundle, entryReg: EntryBundle, status: Status, commonIn: CommonInBundle, isEnq: Boolean)(implicit p: Parameters, params: IssueBlockParams) = { 256 val hasIQWakeupGet = hasIQWakeup.getOrElse(0.U.asTypeOf(new CommonIQWakeupBundle)) 257 val cancelByLd = common.srcCancelVec.asUInt.orR 258 val cancelWhenWakeup = VecInit(hasIQWakeupGet.srcWakeupByIQButCancel.map(_.asUInt.orR)).asUInt.orR 259 val respIssueFail = commonIn.issueResp.valid && RespType.isBlocked(commonIn.issueResp.bits.resp) 260 val srcWakeupExuOH = if(isEnq) status.srcStatus.map(_.srcWakeUpL1ExuOH.getOrElse(0.U.asTypeOf(ExuVec()))) else hasIQWakeupGet.regSrcWakeupL1ExuOH 261 entryUpdate.status.robIdx := status.robIdx 262 entryUpdate.status.fuType := IQFuType.readFuType(status.fuType, params.getFuCfgs.map(_.fuType)) 263 entryUpdate.status.srcStatus.zip(status.srcStatus).zipWithIndex.foreach { case ((srcStatusNext, srcStatus), srcIdx) => 264 val cancel = common.srcCancelVec(srcIdx) 265 val wakeupByIQ = hasIQWakeupGet.srcWakeupByIQ(srcIdx).asUInt.orR 266 val wakeupByIQOH = hasIQWakeupGet.srcWakeupByIQ(srcIdx) 267 val wakeup = common.srcWakeup(srcIdx) 268 srcStatusNext.psrc := srcStatus.psrc 269 srcStatusNext.srcType := srcStatus.srcType 270 srcStatusNext.srcState := Mux(cancel, false.B, wakeup | srcStatus.srcState) 271 srcStatusNext.dataSources.value := (if (params.inVfSchd && params.readVfRf && params.hasIQWakeUp) { 272 // Vf / Mem -> Vf 273 val isWakeupByMemIQ = wakeupByIQOH.zip(commonIn.wakeUpFromIQ).filter(_._2.bits.params.isMemExeUnit).map(_._1).fold(false.B)(_ || _) 274 MuxCase(srcStatus.dataSources.value, Seq( 275 (wakeupByIQ && isWakeupByMemIQ) -> DataSource.bypass2, 276 (wakeupByIQ && !isWakeupByMemIQ) -> DataSource.bypass, 277 srcStatus.dataSources.readBypass -> DataSource.bypass2, 278 srcStatus.dataSources.readBypass2 -> DataSource.reg, 279 )) 280 } 281 else if (params.inMemSchd && params.readVfRf && params.hasIQWakeUp) { 282 // Vf / Int -> Mem 283 MuxCase(srcStatus.dataSources.value, Seq( 284 wakeupByIQ -> DataSource.bypass, 285 (srcStatus.dataSources.readBypass && SrcType.isVfp(srcStatus.srcType)) -> DataSource.bypass2, 286 (srcStatus.dataSources.readBypass && !SrcType.isVfp(srcStatus.srcType)) -> DataSource.reg, 287 srcStatus.dataSources.readBypass2 -> DataSource.reg, 288 )) 289 } 290 else { 291 MuxCase(srcStatus.dataSources.value, Seq( 292 wakeupByIQ -> DataSource.bypass, 293 srcStatus.dataSources.readBypass -> DataSource.reg, 294 )) 295 }) 296 if(params.hasIQWakeUp) { 297 ExuOHGen(srcStatusNext.srcWakeUpL1ExuOH.get, wakeupByIQOH, wakeup, srcWakeupExuOH(srcIdx)) 298 srcStatusNext.srcLoadDependency := 299 Mux(wakeup, 300 Mux1H(wakeupByIQOH, hasIQWakeupGet.shiftedWakeupLoadDependencyByIQVec), 301 Mux(validReg && srcStatus.srcLoadDependency.asUInt.orR, VecInit(srcStatus.srcLoadDependency.map(i => i(i.getWidth - 2, 0) << 1)), srcStatus.srcLoadDependency)) 302 } else { 303 srcStatusNext.srcLoadDependency := Mux(validReg && srcStatus.srcLoadDependency.asUInt.orR, VecInit(srcStatus.srcLoadDependency.map(i => i(i.getWidth - 2, 0) << 1)), srcStatus.srcLoadDependency) 304 } 305 } 306 entryUpdate.status.blocked := false.B 307 entryUpdate.status.issued := MuxCase(status.issued, Seq( 308 (cancelByLd || cancelWhenWakeup || respIssueFail) -> false.B, 309 commonIn.deqSel -> true.B, 310 !status.srcReady -> false.B, 311 )) 312 entryUpdate.status.firstIssue := commonIn.deqSel || status.firstIssue 313 entryUpdate.status.issueTimer := Mux(commonIn.deqSel, 0.U, Mux(status.issued, status.issueTimer + 1.U, "b11".U)) 314 entryUpdate.status.deqPortIdx := Mux(commonIn.deqSel, commonIn.deqPortIdxWrite, Mux(status.issued, status.deqPortIdx, 0.U)) 315 entryUpdate.imm.foreach(_ := entryReg.imm.get) 316 entryUpdate.payload := entryReg.payload 317 if (params.isVecMemIQ) { 318 entryUpdate.status.vecMem.get := entryReg.status.vecMem.get 319 } 320 } 321 322 def CommonOutConnect(commonOut: CommonOutBundle, common: CommonWireBundle, hasIQWakeup: Option[CommonIQWakeupBundle], validReg: Bool, entryUpdate: EntryBundle, entryReg: EntryBundle, status: Status, commonIn: CommonInBundle, isEnq: Boolean, isComp: Boolean)(implicit p: Parameters, params: IssueBlockParams) = { 323 val hasIQWakeupGet = hasIQWakeup.getOrElse(0.U.asTypeOf(new CommonIQWakeupBundle)) 324 val srcWakeupExuOH = if(isEnq) status.srcStatus.map(_.srcWakeUpL1ExuOH.getOrElse(0.U.asTypeOf(ExuVec()))) else hasIQWakeupGet.regSrcWakeupL1ExuOH 325 commonOut.valid := validReg 326 commonOut.canIssue := (if (isComp) (common.canIssue || hasIQWakeupGet.canIssueBypass) && !common.flushed 327 else common.canIssue && !common.flushed) 328 commonOut.fuType := IQFuType.readFuType(status.fuType, params.getFuCfgs.map(_.fuType)).asUInt 329 commonOut.robIdx := status.robIdx 330 commonOut.dataSource.zipWithIndex.foreach{ case (dataSourceOut, srcIdx) => 331 val wakeupByIQWithoutCancel = hasIQWakeupGet.srcWakeupByIQWithoutCancel(srcIdx).asUInt.orR 332 val wakeupByIQWithoutCancelOH = hasIQWakeupGet.srcWakeupByIQWithoutCancel(srcIdx) 333 val isWakeupByMemIQ = wakeupByIQWithoutCancelOH.zip(commonIn.wakeUpFromIQ).filter(_._2.bits.params.isMemExeUnit).map(_._1).fold(false.B)(_ || _) 334 dataSourceOut.value := Mux(wakeupByIQWithoutCancel, 335 if (params.inVfSchd && params.readVfRf && params.hasWakeupFromMem) Mux(isWakeupByMemIQ, DataSource.bypass, DataSource.forward) else DataSource.forward, 336 status.srcStatus(srcIdx).dataSources.value) 337 } 338 commonOut.isFirstIssue := !status.firstIssue 339 commonOut.entry.valid := validReg 340 commonOut.entry.bits := entryReg 341 if(isEnq) { 342 commonOut.entry.bits.status := status 343 } 344 commonOut.issueTimerRead := status.issueTimer 345 commonOut.deqPortIdxRead := status.deqPortIdx 346 if(params.hasIQWakeUp) { 347 val wakeupSrcLoadDependency = hasIQWakeupGet.srcWakeupByIQWithoutCancel.map(x => Mux1H(x, hasIQWakeupGet.wakeupLoadDependencyByIQVec)) 348 commonOut.srcWakeUpL1ExuOH.get := (if (isComp) Mux(hasIQWakeupGet.canIssueBypass && !common.canIssue, hasIQWakeupGet.srcWakeupL1ExuOHOut, VecInit(srcWakeupExuOH)) 349 else VecInit(srcWakeupExuOH)) 350 commonOut.srcLoadDependency.zipWithIndex.foreach { case (srcLoadDependencyOut, srcIdx) => 351 srcLoadDependencyOut := (if (isComp) Mux(hasIQWakeupGet.canIssueBypass && !common.canIssue, 352 VecInit(status.srcStatus(srcIdx).srcLoadDependency.zip(wakeupSrcLoadDependency(srcIdx)).map(x => x._1 | x._2)), 353 status.srcStatus(srcIdx).srcLoadDependency) 354 else status.srcStatus(srcIdx).srcLoadDependency) 355 } 356 } else { 357 commonOut.srcLoadDependency.zipWithIndex.foreach { case (srcLoadDependencyOut, srcIdx) => 358 srcLoadDependencyOut := status.srcStatus(srcIdx).srcLoadDependency 359 } 360 } 361 commonOut.entry.bits.status.srcStatus.map(_.srcLoadDependency).zipWithIndex.foreach { case (srcLoadDependencyOut, srcIdx) => 362 srcLoadDependencyOut := (if (isComp) Mux(hasIQWakeupGet.canIssueBypass && !common.canIssue, 363 common.srcLoadDependencyOut(srcIdx), 364 status.srcStatus(srcIdx).srcLoadDependency) 365 else status.srcStatus(srcIdx).srcLoadDependency) 366 } 367 commonOut.enqReady := common.enqReady 368 commonOut.transEntry.valid := validReg && !common.flushed && !common.deqSuccess 369 commonOut.transEntry.bits := entryUpdate 370 // debug 371 commonOut.entryInValid := commonIn.enq.valid 372 commonOut.entryOutDeqValid := validReg && (common.flushed || common.deqSuccess) 373 commonOut.entryOutTransValid := validReg && commonIn.transSel && !(common.flushed || common.deqSuccess) 374 commonOut.perfWakeupByWB := common.srcWakeupByWB.zip(status.srcStatus).map{ case (w, s) => w && SrcState.isBusy(s.srcState) && validReg } 375 if (params.hasIQWakeUp) { 376 commonOut.perfLdCancel.get := hasIQWakeupGet.cancelVec.map(_ && validReg) 377 commonOut.perfOg0Cancel.get := hasIQWakeupGet.srcWakeupByIQButCancel.map(_.asUInt.orR && validReg) 378 commonOut.perfWakeupByIQ.get := hasIQWakeupGet.srcWakeupByIQ.map(x => VecInit(x.map(_ && validReg))) 379 } 380 // vecMem 381 if (params.isVecMemIQ) { 382 commonOut.uopIdx.get := entryReg.payload.uopIdx 383 } 384 } 385 386 def EntryVecMemConnect(commonIn: CommonInBundle, common: CommonWireBundle, validReg: Bool, entryReg: EntryBundle, entryRegNext: EntryBundle, entryUpdate: EntryBundle)(implicit p: Parameters, params: IssueBlockParams) = { 387 val fromLsq = commonIn.fromLsq.get 388 val vecMemStatus = entryReg.status.vecMem.get 389 val vecMemStatusUpdate = entryUpdate.status.vecMem.get 390 vecMemStatusUpdate := vecMemStatus 391 392 val isLsqHead = { 393 entryReg.status.vecMem.get.lqIdx <= fromLsq.lqDeqPtr && 394 entryReg.status.vecMem.get.sqIdx <= fromLsq.sqDeqPtr 395 } 396 397 // update blocked 398 entryUpdate.status.blocked := !isLsqHead 399 } 400 401 def ExuOHGen(exuOH: Vec[Bool], wakeupByIQOH: Vec[Bool], wakeup: Bool, regSrcExuOH: Vec[Bool])(implicit p: Parameters, params: IssueBlockParams) = { 402 val origExuOH = 0.U.asTypeOf(exuOH) 403 when(wakeupByIQOH.asUInt.orR) { 404 origExuOH := Mux1H(wakeupByIQOH, params.wakeUpSourceExuIdx.map(x => MathUtils.IntToOH(x).U(p(XSCoreParamsKey).backendParams.numExu.W)).toSeq).asBools 405 }.otherwise { 406 origExuOH := regSrcExuOH 407 } 408 exuOH := 0.U.asTypeOf(exuOH) 409 params.wakeUpSourceExuIdx.foreach(x => exuOH(x) := origExuOH(x)) 410 } 411 412 object IQFuType { 413 def num = FuType.num 414 415 def apply() = Vec(num, Bool()) 416 417 def readFuType(fuType: Vec[Bool], fus: Seq[FuType.OHType]): Vec[Bool] = { 418 val res = 0.U.asTypeOf(fuType) 419 fus.foreach(x => res(x.id) := fuType(x.id)) 420 res 421 } 422 } 423 424 class EnqDelayInBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 425 //wakeup 426 val wakeUpFromWB: MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = Flipped(params.genWBWakeUpSinkValidBundle) 427 val wakeUpFromIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(params.genIQWakeUpSinkValidBundle) 428 //cancel 429 val og0Cancel = Input(ExuOH(backendParams.numExu)) 430 val ldCancel = Vec(backendParams.LdExuCnt, Flipped(new LoadCancelIO)) 431 } 432 433 class EnqDelayOutBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 434 val srcWakeUpByWB: Vec[UInt] = Vec(params.numRegSrc, SrcState()) 435 val srcWakeUpByIQ: Vec[UInt] = Vec(params.numRegSrc, SrcState()) 436 val srcWakeUpByIQVec: Vec[Vec[Bool]] = Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool())) 437 val shiftedWakeupLoadDependencyByIQVec: Vec[Vec[UInt]] = Vec(params.numWakeupFromIQ, Vec(LoadPipelineWidth, UInt(3.W))) 438 } 439 440 def EnqDelayWakeupConnect(enqDelayIn: EnqDelayInBundle, enqDelayOut: EnqDelayOutBundle, status: Status, delay: Int)(implicit p: Parameters, params: IssueBlockParams) = { 441 enqDelayOut.srcWakeUpByWB.zipWithIndex.foreach { case (wakeup, i) => 442 wakeup := enqDelayIn.wakeUpFromWB.map(x => x.bits.wakeUp(Seq((status.srcStatus(i).psrc, status.srcStatus(i).srcType)), x.valid).head 443 ).reduce(_ || _) 444 } 445 446 if (params.hasIQWakeUp) { 447 val wakeupVec: IndexedSeq[IndexedSeq[Bool]] = enqDelayIn.wakeUpFromIQ.map( x => 448 x.bits.wakeUpFromIQ(status.srcStatus.map(_.psrc) zip status.srcStatus.map(_.srcType)) 449 ).toIndexedSeq.transpose 450 val cancelSel = params.wakeUpSourceExuIdx.zip(enqDelayIn.wakeUpFromIQ).map{ case (x, y) => enqDelayIn.og0Cancel(x) && y.bits.is0Lat} 451 enqDelayOut.srcWakeUpByIQVec := wakeupVec.map(x => VecInit(x.zip(cancelSel).map { case (wakeup, cancel) => wakeup && !cancel })) 452 } else { 453 enqDelayOut.srcWakeUpByIQVec := 0.U.asTypeOf(enqDelayOut.srcWakeUpByIQVec) 454 } 455 456 if (params.hasIQWakeUp) { 457 enqDelayOut.srcWakeUpByIQ.zipWithIndex.foreach { case (wakeup, i) => 458 val ldTransCancel = Mux1H(enqDelayOut.srcWakeUpByIQVec(i), enqDelayIn.wakeUpFromIQ.map(_.bits.loadDependency).map(dp => LoadShouldCancel(Some(dp), enqDelayIn.ldCancel)).toSeq) 459 wakeup := enqDelayOut.srcWakeUpByIQVec(i).asUInt.orR && !ldTransCancel 460 } 461 } else { 462 enqDelayOut.srcWakeUpByIQ := 0.U.asTypeOf(enqDelayOut.srcWakeUpByIQ) 463 } 464 465 enqDelayOut.shiftedWakeupLoadDependencyByIQVec.zip(enqDelayIn.wakeUpFromIQ.map(_.bits.loadDependency)) 466 .zip(params.wakeUpInExuSources.map(_.name)).foreach { case ((dps, ldps), name) => 467 dps.zip(ldps).zipWithIndex.foreach { case ((dp, ldp), deqPortIdx) => 468 if (params.backendParam.getLdExuIdx(params.backendParam.allExuParams.find(_.name == name).get) == deqPortIdx) 469 dp := 1.U << delay 470 else 471 dp := ldp << delay 472 } 473 } 474 } 475} 476