1package xiangshan.backend.issue 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import utils.{MathUtils, OptionWrapper, XSError} 7import utility.HasCircularQueuePtrHelper 8import xiangshan._ 9import xiangshan.backend.Bundles._ 10import xiangshan.backend.datapath.DataSource 11import xiangshan.backend.fu.FuType 12import xiangshan.backend.fu.vector.Bundles.NumLsElem 13import xiangshan.backend.rob.RobPtr 14import xiangshan.mem.{LqPtr, MemWaitUpdateReq, SqPtr} 15 16object EntryBundles extends HasCircularQueuePtrHelper { 17 18 class Status(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 19 //basic status 20 val robIdx = new RobPtr 21 val fuType = IQFuType() 22 //src status 23 val srcStatus = Vec(params.numRegSrc, new SrcStatus) 24 //issue status 25 val blocked = Bool() 26 val issued = Bool() 27 val firstIssue = Bool() 28 val issueTimer = UInt(2.W) 29 val deqPortIdx = UInt(1.W) 30 //vector mem status 31 val vecMem = OptionWrapper(params.isVecMemIQ, new StatusVecMemPart) 32 33 def srcReady: Bool = { 34 VecInit(srcStatus.map(_.srcState).map(SrcState.isReady)).asUInt.andR 35 } 36 37 def canIssue: Bool = { 38 srcReady && !issued && !blocked 39 } 40 41 def mergedLoadDependency: Vec[UInt] = { 42 srcStatus.map(_.srcLoadDependency).reduce({ 43 case (l: Vec[UInt], r: Vec[UInt]) => VecInit(l.zip(r).map(x => x._1 | x._2)) 44 }: (Vec[UInt], Vec[UInt]) => Vec[UInt]) 45 } 46 } 47 48 class SrcStatus(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 49 val psrc = UInt(params.rdPregIdxWidth.W) 50 val srcType = SrcType() 51 val srcState = SrcState() 52 val dataSources = DataSource() 53 val srcLoadDependency = Vec(LoadPipelineWidth, UInt(3.W)) 54 val srcTimer = OptionWrapper(params.hasIQWakeUp, UInt(3.W)) 55 val srcWakeUpL1ExuOH = OptionWrapper(params.hasIQWakeUp, ExuVec()) 56 } 57 58 class StatusVecMemPart(implicit p:Parameters, params: IssueBlockParams) extends Bundle { 59 val sqIdx = new SqPtr 60 val lqIdx = new LqPtr 61 val numLsElem = NumLsElem() 62 } 63 64 class EntryDeqRespBundle(implicit p: Parameters, params: IssueBlockParams) extends Bundle { 65 val robIdx = new RobPtr 66 val resp = RespType() 67 val fuType = FuType() 68 val uopIdx = OptionWrapper(params.isVecMemIQ, Output(UopIdx())) 69 } 70 71 object RespType { 72 def apply() = UInt(2.W) 73 74 def isBlocked(resp: UInt) = { 75 resp === block 76 } 77 78 def succeed(resp: UInt) = { 79 resp === success 80 } 81 82 val block = "b00".U 83 val uncertain = "b01".U 84 val success = "b11".U 85 } 86 87 class EntryBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 88 val status = new Status() 89 val imm = OptionWrapper(params.needImm, UInt((params.deqImmTypesMaxLen).W)) 90 val payload = new DynInst() 91 } 92 93 class CommonInBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 94 val flush = Flipped(ValidIO(new Redirect)) 95 val enq = Flipped(ValidIO(new EntryBundle)) 96 //wakeup 97 val wakeUpFromWB: MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = Flipped(params.genWBWakeUpSinkValidBundle) 98 val wakeUpFromIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(params.genIQWakeUpSinkValidBundle) 99 // vl 100 val vlIsZero = Input(Bool()) 101 val vlIsVlmax = Input(Bool()) 102 //cancel 103 val og0Cancel = Input(ExuOH(backendParams.numExu)) 104 val og1Cancel = Input(ExuOH(backendParams.numExu)) 105 val ldCancel = Vec(backendParams.LdExuCnt, Flipped(new LoadCancelIO)) 106 //deq sel 107 val deqSel = Input(Bool()) 108 val deqPortIdxWrite = Input(UInt(1.W)) 109 val issueResp = Flipped(ValidIO(new EntryDeqRespBundle)) 110 //trans sel 111 val transSel = Input(Bool()) 112 // vector mem only 113 val fromLsq = OptionWrapper(params.isVecMemIQ, new Bundle { 114 val sqDeqPtr = Input(new SqPtr) 115 val lqDeqPtr = Input(new LqPtr) 116 }) 117 } 118 119 class CommonOutBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 120 //status 121 val valid = Output(Bool()) 122 val canIssue = Output(Bool()) 123 val fuType = Output(FuType()) 124 val robIdx = Output(new RobPtr) 125 val uopIdx = OptionWrapper(params.isVecMemIQ, Output(UopIdx())) 126 //src 127 val dataSource = Vec(params.numRegSrc, Output(DataSource())) 128 val srcLoadDependency = Vec(params.numRegSrc, Output(Vec(LoadPipelineWidth, UInt(3.W)))) 129 val srcWakeUpL1ExuOH = OptionWrapper(params.hasIQWakeUp, Vec(params.numRegSrc, Output(ExuVec()))) 130 val srcTimer = OptionWrapper(params.hasIQWakeUp, Vec(params.numRegSrc, Output(UInt(3.W)))) 131 //deq 132 val isFirstIssue = Output(Bool()) 133 val entry = ValidIO(new EntryBundle) 134 val deqPortIdxRead = Output(UInt(1.W)) 135 val issueTimerRead = Output(UInt(2.W)) 136 //trans 137 val enqReady = Output(Bool()) 138 val transEntry = ValidIO(new EntryBundle) 139 // debug 140 val cancel = OptionWrapper(params.hasIQWakeUp, Output(Bool())) 141 val entryInValid = Output(Bool()) 142 val entryOutDeqValid = Output(Bool()) 143 val entryOutTransValid = Output(Bool()) 144 } 145 146 class CommonWireBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 147 val validRegNext = Bool() 148 val flushed = Bool() 149 val clear = Bool() 150 val canIssue = Bool() 151 val enqReady = Bool() 152 val deqSuccess = Bool() 153 val srcWakeup = Vec(params.numRegSrc, Bool()) 154 val srcWakeupByWB = Vec(params.numRegSrc, Bool()) 155 val vlWakeupByWb = Bool() 156 val srcLoadDependencyOut = Vec(params.numRegSrc, Vec(LoadPipelineWidth, UInt(3.W))) 157 val srcCancelVec = Vec(params.numRegSrc, Bool()) 158 val srcLoadCancelVec = Vec(params.numRegSrc, Bool()) 159 } 160 161 def CommonWireConnect(common: CommonWireBundle, hasIQWakeup: Option[CommonIQWakeupBundle], validReg: Bool, status: Status, commonIn: CommonInBundle, isEnq: Boolean)(implicit p: Parameters, params: IssueBlockParams) = { 162 val hasIQWakeupGet = hasIQWakeup.getOrElse(0.U.asTypeOf(new CommonIQWakeupBundle)) 163 common.flushed := status.robIdx.needFlush(commonIn.flush) 164 common.deqSuccess := commonIn.issueResp.valid && RespType.succeed(commonIn.issueResp.bits.resp) && !common.srcLoadCancelVec.asUInt.orR 165 common.srcWakeup := common.srcWakeupByWB.zip(hasIQWakeupGet.srcWakeupByIQ).map { case (x, y) => x || y.asUInt.orR } 166 common.srcWakeupByWB := commonIn.wakeUpFromWB.map(bundle => bundle.bits.wakeUp(status.srcStatus.map(_.psrc) zip status.srcStatus.map(_.srcType), bundle.valid)).transpose.map(x => VecInit(x.toSeq).asUInt.orR).toSeq 167 common.canIssue := validReg && status.canIssue 168 common.enqReady := !validReg || common.clear 169 common.clear := common.flushed || common.deqSuccess || commonIn.transSel 170 common.srcCancelVec.zip(common.srcLoadCancelVec).zip(hasIQWakeupGet.srcWakeupByIQWithoutCancel).zipWithIndex.foreach { case (((srcCancel, srcLoadCancel), wakeUpByIQVec), srcIdx) => 171 val ldTransCancel = if(params.hasIQWakeUp) Mux1H(wakeUpByIQVec, hasIQWakeupGet.wakeupLoadDependencyByIQVec.map(dep => LoadShouldCancel(Some(dep), commonIn.ldCancel))) else false.B 172 srcLoadCancel := LoadShouldCancel(Some(status.srcStatus(srcIdx).srcLoadDependency), commonIn.ldCancel) 173 srcCancel := srcLoadCancel || ldTransCancel 174 } 175 common.srcLoadDependencyOut.zip(hasIQWakeupGet.srcWakeupByIQ).zip(status.srcStatus.map(_.srcLoadDependency)).foreach { 176 case ((loadDependencyOut, wakeUpByIQVec), loadDependency) => 177 if(params.hasIQWakeUp) { 178 loadDependencyOut := Mux(wakeUpByIQVec.asUInt.orR, Mux1H(wakeUpByIQVec, hasIQWakeupGet.shiftedWakeupLoadDependencyByIQBypassVec), loadDependency) 179 } else { 180 loadDependencyOut := loadDependency 181 } 182 183 } 184 if(isEnq) { 185 common.validRegNext := Mux(commonIn.enq.valid && common.enqReady, true.B, Mux(common.clear, false.B, validReg)) 186 } else { 187 common.validRegNext := Mux(commonIn.enq.valid, true.B, Mux(common.clear, false.B, validReg)) 188 } 189 if (params.numRegSrc == 5) { 190 // only when numRegSrc == 5 need vl 191 common.vlWakeupByWb := common.srcWakeupByWB(4) 192 } else { 193 common.vlWakeupByWb := false.B 194 } 195 } 196 197 class CommonIQWakeupBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 198 val srcWakeupByIQ = Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool())) 199 val srcWakeupByIQWithoutCancel = Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool())) 200 val srcWakeupByIQButCancel = Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool())) 201 val regSrcWakeupL1ExuOH = Vec(params.numRegSrc, ExuVec()) 202 val srcWakeupL1ExuOHOut = Vec(params.numRegSrc, ExuVec()) 203 val wakeupLoadDependencyByIQVec = Vec(params.numWakeupFromIQ, Vec(LoadPipelineWidth, UInt(3.W))) 204 val shiftedWakeupLoadDependencyByIQVec = Vec(params.numWakeupFromIQ, Vec(LoadPipelineWidth, UInt(3.W))) 205 val shiftedWakeupLoadDependencyByIQBypassVec = Vec(params.numWakeupFromIQ, Vec(LoadPipelineWidth, UInt(3.W))) 206 val cancelVec = Vec(params.numRegSrc, Bool()) 207 val canIssueBypass = Bool() 208 } 209 210 def CommonIQWakeupConnect(common: CommonWireBundle, hasIQWakeupGet: CommonIQWakeupBundle, validReg: Bool, status: Status, commonIn: CommonInBundle, isEnq: Boolean)(implicit p: Parameters, params: IssueBlockParams) = { 211 val wakeupVec: Seq[Seq[Bool]] = commonIn.wakeUpFromIQ.map((bundle: ValidIO[IssueQueueIQWakeUpBundle]) => 212 bundle.bits.wakeUpFromIQ(status.srcStatus.map(_.psrc) zip status.srcStatus.map(_.srcType)) 213 ).toSeq.transpose 214 val cancelSel = params.wakeUpSourceExuIdx.zip(commonIn.wakeUpFromIQ).map { case (x, y) => commonIn.og0Cancel(x) && y.bits.is0Lat } 215 216 hasIQWakeupGet.cancelVec := common.srcCancelVec 217 hasIQWakeupGet.srcWakeupByIQ := wakeupVec.map(x => VecInit(x.zip(cancelSel).map { case (wakeup, cancel) => wakeup && !cancel })) 218 hasIQWakeupGet.srcWakeupByIQButCancel := wakeupVec.map(x => VecInit(x.zip(cancelSel).map { case (wakeup, cancel) => wakeup && cancel })) 219 hasIQWakeupGet.srcWakeupByIQWithoutCancel := wakeupVec.map(x => VecInit(x)) 220 hasIQWakeupGet.wakeupLoadDependencyByIQVec := commonIn.wakeUpFromIQ.map(_.bits.loadDependency).toSeq 221 hasIQWakeupGet.regSrcWakeupL1ExuOH.zip(status.srcStatus.map(_.srcWakeUpL1ExuOH.get)).foreach { 222 case (exuOH, regExuOH) => 223 exuOH := 0.U.asTypeOf(exuOH) 224 params.wakeUpSourceExuIdx.foreach(x => exuOH(x) := regExuOH(x)) 225 } 226 hasIQWakeupGet.srcWakeupL1ExuOHOut.zip(hasIQWakeupGet.srcWakeupByIQWithoutCancel).zip(common.srcWakeup).zipWithIndex.foreach { 227 case (((exuOH: Vec[Bool], wakeUpByIQOH: Vec[Bool]), wakeUp: Bool), srcIdx) => 228 if(isEnq) { 229 ExuOHGen(exuOH, wakeUpByIQOH, wakeUp, status.srcStatus(srcIdx).srcWakeUpL1ExuOH.get) 230 } else { 231 ExuOHGen(exuOH, wakeUpByIQOH, wakeUp, hasIQWakeupGet.regSrcWakeupL1ExuOH(srcIdx)) 232 } 233 } 234 hasIQWakeupGet.canIssueBypass := validReg && !status.issued && !status.blocked && 235 VecInit(status.srcStatus.map(_.srcState).zip(hasIQWakeupGet.srcWakeupByIQWithoutCancel).zipWithIndex.map { case ((state, wakeupVec), srcIdx) => 236 wakeupVec.asUInt.orR | state 237 }).asUInt.andR 238 } 239 240 241 def ShiftLoadDependency(hasIQWakeupGet: CommonIQWakeupBundle)(implicit p: Parameters, params: IssueBlockParams) = { 242 hasIQWakeupGet.shiftedWakeupLoadDependencyByIQVec 243 .zip(hasIQWakeupGet.wakeupLoadDependencyByIQVec) 244 .zip(params.wakeUpInExuSources.map(_.name)).foreach { 245 case ((deps, originalDeps), name) => deps.zip(originalDeps).zipWithIndex.foreach { 246 case ((dep, originalDep), deqPortIdx) => 247 if (params.backendParam.getLdExuIdx(params.backendParam.allExuParams.find(_.name == name).get) == deqPortIdx) 248 dep := (originalDep << 2).asUInt | 2.U 249 else 250 dep := originalDep << 1 251 } 252 } 253 hasIQWakeupGet.shiftedWakeupLoadDependencyByIQBypassVec 254 .zip(hasIQWakeupGet.wakeupLoadDependencyByIQVec) 255 .zip(params.wakeUpInExuSources.map(_.name)).foreach { 256 case ((deps, originalDeps), name) => deps.zip(originalDeps).zipWithIndex.foreach { 257 case ((dep, originalDep), deqPortIdx) => 258 if (params.backendParam.getLdExuIdx(params.backendParam.allExuParams.find(_.name == name).get) == deqPortIdx) 259 dep := (originalDep << 1).asUInt | 1.U 260 else 261 dep := originalDep 262 } 263 } 264 } 265 266 def EntryRegCommonConnect(common: CommonWireBundle, hasIQWakeup: Option[CommonIQWakeupBundle], validReg: Bool, entryUpdate: EntryBundle, entryReg: EntryBundle, status: Status, commonIn: CommonInBundle, isEnq: Boolean)(implicit p: Parameters, params: IssueBlockParams) = { 267 val hasIQWakeupGet = hasIQWakeup.getOrElse(0.U.asTypeOf(new CommonIQWakeupBundle)) 268 val cancelByLd = common.srcCancelVec.asUInt.orR 269 val cancelWhenWakeup = VecInit(hasIQWakeupGet.srcWakeupByIQButCancel.map(_.asUInt.orR)).asUInt.orR 270 val respIssueFail = commonIn.issueResp.valid && RespType.isBlocked(commonIn.issueResp.bits.resp) 271 val srcWakeupExuOH = if(isEnq) status.srcStatus.map(_.srcWakeUpL1ExuOH.getOrElse(0.U.asTypeOf(ExuVec()))) else hasIQWakeupGet.regSrcWakeupL1ExuOH 272 entryUpdate.status.robIdx := status.robIdx 273 entryUpdate.status.fuType := IQFuType.readFuType(status.fuType, params.getFuCfgs.map(_.fuType)) 274 entryUpdate.status.srcStatus.zip(status.srcStatus).zipWithIndex.foreach { case ((srcStatusNext, srcStatus), srcIdx) => 275 val cancel = common.srcCancelVec(srcIdx) 276 val wakeupByIQ = hasIQWakeupGet.srcWakeupByIQ(srcIdx).asUInt.orR 277 val wakeupByIQOH = hasIQWakeupGet.srcWakeupByIQ(srcIdx) 278 val wakeup = common.srcWakeup(srcIdx) 279 280 val ignoreOldVd = Wire(Bool()) 281 val vlWakeUpByWb = common.vlWakeupByWb 282 val isDependOldvd = entryReg.payload.vpu.isDependOldvd 283 val vta = entryReg.payload.vpu.vta 284 val vma = entryReg.payload.vpu.vma 285 val vm = entryReg.payload.vpu.vm 286 val vlIsZero = commonIn.vlIsZero 287 val vlIsVlmax = commonIn.vlIsVlmax 288 val ignoreTail = vlIsVlmax && (vm =/= 0.U || vma) 289 val ignoreWhole = !vlIsVlmax && (vm =/= 0.U || vma) && vta 290 if (params.numVfSrc > 0 && srcIdx == 2) { 291 /** 292 * the src store the old vd, update it when vl is write back 293 * 1. when the instruction depend on old vd, we cannot set the srctype to imm, we will update the method of uop split to avoid this situation soon 294 * 2. when vl = 0, we cannot set the srctype to imm because the vd keep the old value 295 * 3. when vl = vlmax, we can set srctype to imm when vta is not set 296 */ 297 ignoreOldVd := vlWakeUpByWb && !isDependOldvd && !vlIsZero && (ignoreTail || ignoreWhole) 298 } else { 299 ignoreOldVd := false.B 300 } 301 302 srcStatusNext.psrc := srcStatus.psrc 303 srcStatusNext.srcType := Mux(ignoreOldVd, SrcType.no, srcStatus.srcType) 304 srcStatusNext.srcState := Mux(cancel, false.B, wakeup | srcStatus.srcState | ignoreOldVd) 305 srcStatusNext.dataSources.value := Mux(wakeupByIQ, DataSource.bypass, Mux(srcStatus.dataSources.readBypass, DataSource.reg, srcStatus.dataSources.value)) 306 if(params.hasIQWakeUp) { 307 srcStatusNext.srcTimer.get := MuxCase(3.U, Seq( 308 // T0: waked up by IQ, T1: reset timer as 1 309 wakeupByIQ -> 2.U, 310 // do not overflow 311 srcStatus.srcTimer.get.andR -> srcStatus.srcTimer.get, 312 // T2+: increase if the entry is valid, the src is ready, and the src is woken up by iq 313 (validReg && SrcState.isReady(srcStatus.srcState) && srcWakeupExuOH(srcIdx).asUInt.orR) -> (srcStatus.srcTimer.get + 1.U) 314 )) 315 ExuOHGen(srcStatusNext.srcWakeUpL1ExuOH.get, wakeupByIQOH, wakeup, srcWakeupExuOH(srcIdx)) 316 srcStatusNext.srcLoadDependency := 317 Mux(wakeup, 318 Mux1H(wakeupByIQOH, hasIQWakeupGet.shiftedWakeupLoadDependencyByIQVec), 319 Mux(validReg && srcStatus.srcLoadDependency.asUInt.orR, VecInit(srcStatus.srcLoadDependency.map(i => i(i.getWidth - 2, 0) << 1)), srcStatus.srcLoadDependency)) 320 } else { 321 srcStatusNext.srcLoadDependency := Mux(validReg && srcStatus.srcLoadDependency.asUInt.orR, VecInit(srcStatus.srcLoadDependency.map(i => i(i.getWidth - 2, 0) << 1)), srcStatus.srcLoadDependency) 322 } 323 } 324 entryUpdate.status.blocked := false.B 325 entryUpdate.status.issued := MuxCase(status.issued, Seq( 326 (cancelByLd || cancelWhenWakeup || respIssueFail) -> false.B, 327 commonIn.deqSel -> true.B, 328 !status.srcReady -> false.B, 329 )) 330 entryUpdate.status.firstIssue := commonIn.deqSel || status.firstIssue 331 entryUpdate.status.issueTimer := Mux(commonIn.deqSel, 0.U, Mux(status.issued, status.issueTimer + 1.U, "b10".U)) 332 entryUpdate.status.deqPortIdx := Mux(commonIn.deqSel, commonIn.deqPortIdxWrite, Mux(status.issued, status.deqPortIdx, 0.U)) 333 entryUpdate.imm.foreach(_ := entryReg.imm.get) 334 entryUpdate.payload := entryReg.payload 335 if (params.isVecMemIQ) { 336 entryUpdate.status.vecMem.get := entryReg.status.vecMem.get 337 } 338 } 339 340 def CommonOutConnect(commonOut: CommonOutBundle, common: CommonWireBundle, hasIQWakeup: Option[CommonIQWakeupBundle], validReg: Bool, entryUpdate: EntryBundle, entryReg: EntryBundle, status: Status, commonIn: CommonInBundle, isEnq: Boolean, isComp: Boolean)(implicit p: Parameters, params: IssueBlockParams) = { 341 val hasIQWakeupGet = hasIQWakeup.getOrElse(0.U.asTypeOf(new CommonIQWakeupBundle)) 342 val srcWakeupExuOH = if(isEnq) status.srcStatus.map(_.srcWakeUpL1ExuOH.getOrElse(0.U.asTypeOf(ExuVec()))) else hasIQWakeupGet.regSrcWakeupL1ExuOH 343 commonOut.valid := validReg 344 commonOut.canIssue := (if (isComp) (common.canIssue || hasIQWakeupGet.canIssueBypass) && !common.flushed 345 else common.canIssue && !common.flushed) 346 commonOut.fuType := IQFuType.readFuType(status.fuType, params.getFuCfgs.map(_.fuType)).asUInt 347 commonOut.robIdx := status.robIdx 348 commonOut.dataSource.zipWithIndex.foreach{ case (dataSourceOut, srcIdx) => 349 dataSourceOut.value := Mux(hasIQWakeupGet.srcWakeupByIQWithoutCancel(srcIdx).asUInt.orR, DataSource.forward, status.srcStatus(srcIdx).dataSources.value) 350 } 351 commonOut.isFirstIssue := !status.firstIssue 352 commonOut.entry.valid := validReg 353 commonOut.entry.bits := entryReg 354 if(isEnq) { 355 commonOut.entry.bits.status := status 356 } 357 commonOut.issueTimerRead := status.issueTimer 358 commonOut.deqPortIdxRead := status.deqPortIdx 359 if(params.hasIQWakeUp) { 360 val wakeupSrcLoadDependency = hasIQWakeupGet.srcWakeupByIQWithoutCancel.map(x => Mux1H(x, hasIQWakeupGet.wakeupLoadDependencyByIQVec)) 361 commonOut.srcWakeUpL1ExuOH.get := (if (isComp) Mux(hasIQWakeupGet.canIssueBypass && !common.canIssue, hasIQWakeupGet.srcWakeupL1ExuOHOut, VecInit(srcWakeupExuOH)) 362 else VecInit(srcWakeupExuOH)) 363 commonOut.srcTimer.get.zipWithIndex.foreach { case (srcTimerOut, srcIdx) => 364 val wakeupByIQOH = hasIQWakeupGet.srcWakeupByIQWithoutCancel(srcIdx) 365 srcTimerOut := Mux(wakeupByIQOH.asUInt.orR, Mux1H(wakeupByIQOH, commonIn.wakeUpFromIQ.map(_.bits.is0Lat).toSeq).asUInt, status.srcStatus(srcIdx).srcTimer.get) 366 } 367 commonOut.srcLoadDependency.zipWithIndex.foreach { case (srcLoadDependencyOut, srcIdx) => 368 srcLoadDependencyOut := (if (isComp) Mux(hasIQWakeupGet.canIssueBypass && !common.canIssue, 369 VecInit(status.srcStatus(srcIdx).srcLoadDependency.zip(wakeupSrcLoadDependency(srcIdx)).map(x => x._1 | x._2)), 370 status.srcStatus(srcIdx).srcLoadDependency) 371 else status.srcStatus(srcIdx).srcLoadDependency) 372 } 373 } else { 374 commonOut.srcLoadDependency.zipWithIndex.foreach { case (srcLoadDependencyOut, srcIdx) => 375 srcLoadDependencyOut := status.srcStatus(srcIdx).srcLoadDependency 376 } 377 } 378 commonOut.entry.bits.status.srcStatus.map(_.srcLoadDependency).zipWithIndex.foreach { case (srcLoadDependencyOut, srcIdx) => 379 srcLoadDependencyOut := (if (isComp) Mux(hasIQWakeupGet.canIssueBypass && !common.canIssue, 380 common.srcLoadDependencyOut(srcIdx), 381 status.srcStatus(srcIdx).srcLoadDependency) 382 else status.srcStatus(srcIdx).srcLoadDependency) 383 } 384 commonOut.enqReady := common.enqReady 385 commonOut.transEntry.valid := validReg && !common.flushed && !common.deqSuccess 386 commonOut.transEntry.bits := entryUpdate 387 // debug 388 commonOut.cancel.foreach(_ := hasIQWakeupGet.cancelVec.asUInt.orR) 389 commonOut.entryInValid := commonIn.enq.valid 390 commonOut.entryOutDeqValid := validReg && (common.flushed || common.deqSuccess) 391 commonOut.entryOutTransValid := validReg && commonIn.transSel && !(common.flushed || common.deqSuccess) 392 if (params.isVecMemIQ) { 393 commonOut.uopIdx.get := entryReg.payload.uopIdx 394 } 395 } 396 397 def EntryVecMemConnect(commonIn: CommonInBundle, common: CommonWireBundle, validReg: Bool, entryReg: EntryBundle, entryRegNext: EntryBundle, entryUpdate: EntryBundle)(implicit p: Parameters, params: IssueBlockParams) = { 398 val fromLsq = commonIn.fromLsq.get 399 val vecMemStatus = entryReg.status.vecMem.get 400 val vecMemStatusUpdate = entryUpdate.status.vecMem.get 401 vecMemStatusUpdate := vecMemStatus 402 403 // update blocked 404 entryUpdate.status.blocked := false.B 405 } 406 407 def ExuOHGen(exuOH: Vec[Bool], wakeupByIQOH: Vec[Bool], wakeup: Bool, regSrcExuOH: Vec[Bool])(implicit p: Parameters, params: IssueBlockParams) = { 408 val origExuOH = 0.U.asTypeOf(exuOH) 409 when(wakeupByIQOH.asUInt.orR) { 410 origExuOH := Mux1H(wakeupByIQOH, params.wakeUpSourceExuIdx.map(x => MathUtils.IntToOH(x).U(p(XSCoreParamsKey).backendParams.numExu.W)).toSeq).asBools 411 }.otherwise { 412 origExuOH := regSrcExuOH 413 } 414 exuOH := 0.U.asTypeOf(exuOH) 415 params.wakeUpSourceExuIdx.foreach(x => exuOH(x) := origExuOH(x)) 416 } 417 418 object IQFuType { 419 def num = FuType.num 420 421 def apply() = Vec(num, Bool()) 422 423 def readFuType(fuType: Vec[Bool], fus: Seq[FuType.OHType]): Vec[Bool] = { 424 val res = 0.U.asTypeOf(fuType) 425 fus.foreach(x => res(x.id) := fuType(x.id)) 426 res 427 } 428 } 429} 430