1package xiangshan.backend.issue 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import utils.{MathUtils, OptionWrapper} 7import utility.HasCircularQueuePtrHelper 8import xiangshan._ 9import xiangshan.backend.Bundles._ 10import xiangshan.backend.datapath.DataSource 11import xiangshan.backend.fu.FuType 12import xiangshan.backend.rob.RobPtr 13import xiangshan.mem.{MemWaitUpdateReq, SqPtr, LqPtr} 14 15object EntryBundles extends HasCircularQueuePtrHelper { 16 17 class Status(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 18 //basic status 19 val robIdx = new RobPtr 20 val fuType = IQFuType() 21 //src status 22 val srcStatus = Vec(params.numRegSrc, new SrcStatus) 23 //issue status 24 val blocked = Bool() 25 val issued = Bool() 26 val firstIssue = Bool() 27 val issueTimer = UInt(2.W) 28 val deqPortIdx = UInt(1.W) 29 //mem status 30 val mem = OptionWrapper(params.isMemAddrIQ, new StatusMemPart) 31 //vector mem status 32 val vecMem = OptionWrapper(params.isVecMemIQ, new StatusVecMemPart) 33 34 def srcReady: Bool = { 35 VecInit(srcStatus.map(_.srcState).map(SrcState.isReady)).asUInt.andR 36 } 37 38 def canIssue: Bool = { 39 srcReady && !issued && !blocked 40 } 41 42 def mergedLoadDependency: Option[Vec[UInt]] = { 43 OptionWrapper(params.hasIQWakeUp, srcStatus.map(_.srcLoadDependency.get).reduce({ 44 case (l: Vec[UInt], r: Vec[UInt]) => VecInit(l.zip(r).map(x => x._1 | x._2)) 45 }: (Vec[UInt], Vec[UInt]) => Vec[UInt])) 46 } 47 } 48 49 class SrcStatus(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 50 val psrc = UInt(params.rdPregIdxWidth.W) 51 val srcType = SrcType() 52 val srcState = SrcState() 53 val dataSources = DataSource() 54 val srcTimer = OptionWrapper(params.hasIQWakeUp, UInt(3.W)) 55 val srcWakeUpL1ExuOH = OptionWrapper(params.hasIQWakeUp, ExuVec()) 56 val srcLoadDependency = OptionWrapper(params.hasIQWakeUp, Vec(LoadPipelineWidth, UInt(3.W))) 57 } 58 59 class StatusMemPart(implicit p:Parameters) extends Bundle { 60 val waitForSqIdx = new SqPtr // generated by store data valid check 61 val waitForRobIdx = new RobPtr // generated by store set 62 val waitForStd = Bool() 63 val strictWait = Bool() 64 val sqIdx = new SqPtr 65 } 66 67 class StatusVecMemPart(implicit p:Parameters, params: IssueBlockParams) extends Bundle { 68 val sqIdx = new SqPtr 69 val lqIdx = new LqPtr 70 val uopIdx = UopIdx() 71 } 72 73 class EntryDeqRespBundle(implicit p: Parameters, params: IssueBlockParams) extends Bundle { 74 val robIdx = new RobPtr 75 val respType = RSFeedbackType() // update credit if needs replay 76 val dataInvalidSqIdx = new SqPtr 77 val rfWen = Bool() 78 val fuType = FuType() 79 val uopIdx = OptionWrapper(params.isVecMemIQ, Output(UopIdx())) 80 } 81 82 class EntryBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 83 val status = new Status() 84 val imm = OptionWrapper(params.needImm, UInt((params.deqImmTypesMaxLen).W)) 85 val payload = new DynInst() 86 } 87 88 class CommonInBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 89 val flush = Flipped(ValidIO(new Redirect)) 90 val enq = Flipped(ValidIO(new EntryBundle)) 91 //wakeup 92 val wakeUpFromWB: MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = Flipped(params.genWBWakeUpSinkValidBundle) 93 val wakeUpFromIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(params.genIQWakeUpSinkValidBundle) 94 //cancel 95 val og0Cancel = Input(ExuOH(backendParams.numExu)) 96 val og1Cancel = Input(ExuOH(backendParams.numExu)) 97 val ldCancel = Vec(backendParams.LdExuCnt, Flipped(new LoadCancelIO)) 98 //deq sel 99 val deqSel = Input(Bool()) 100 val deqPortIdxWrite = Input(UInt(1.W)) 101 val issueResp = Flipped(ValidIO(new EntryDeqRespBundle)) 102 //trans sel 103 val transSel = Input(Bool()) 104 // mem only 105 val fromMem = OptionWrapper(params.isMemAddrIQ, new Bundle { 106 val stIssuePtr = Input(new SqPtr) 107 val memWaitUpdateReq = Flipped(new MemWaitUpdateReq) 108 }) 109 // vector mem only 110 val fromLsq = OptionWrapper(params.isVecMemIQ, new Bundle { 111 val sqDeqPtr = Input(new SqPtr) 112 val lqDeqPtr = Input(new LqPtr) 113 }) 114 } 115 116 class CommonOutBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 117 //status 118 val valid = Output(Bool()) 119 val canIssue = Output(Bool()) 120 val fuType = Output(FuType()) 121 val robIdx = Output(new RobPtr) 122 val uopIdx = OptionWrapper(params.isVecMemIQ, Output(UopIdx())) 123 //src 124 val dataSource = Vec(params.numRegSrc, Output(DataSource())) 125 val srcWakeUpL1ExuOH = OptionWrapper(params.hasIQWakeUp, Vec(params.numRegSrc, Output(ExuVec()))) 126 val srcTimer = OptionWrapper(params.hasIQWakeUp, Vec(params.numRegSrc, Output(UInt(3.W)))) 127 val srcLoadDependency = OptionWrapper(params.hasIQWakeUp, Vec(params.numRegSrc, Output(Vec(LoadPipelineWidth, UInt(3.W))))) 128 //deq 129 val isFirstIssue = Output(Bool()) 130 val entry = ValidIO(new EntryBundle) 131 val deqPortIdxRead = Output(UInt(1.W)) 132 val issueTimerRead = Output(UInt(2.W)) 133 // debug 134 val cancel = OptionWrapper(params.hasIQWakeUp, Output(Bool())) 135 } 136 137 class CommonWireBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 138 val validRegNext = Bool() 139 val flushed = Bool() 140 val clear = Bool() 141 val canIssue = Bool() 142 val enqReady = Bool() 143 val deqSuccess = Bool() 144 val srcWakeup = Vec(params.numRegSrc, Bool()) 145 val srcWakeupByWB = Vec(params.numRegSrc, Bool()) 146 } 147 148 def CommonWireConnect(common: CommonWireBundle, hasIQWakeup: Option[CommonIQWakeupBundle], validReg: Bool, status: Status, commonIn: CommonInBundle, isEnq: Boolean)(implicit p: Parameters, params: IssueBlockParams) = { 149 val hasIQWakeupGet = hasIQWakeup.getOrElse(0.U.asTypeOf(new CommonIQWakeupBundle)) 150 common.flushed := status.robIdx.needFlush(commonIn.flush) 151 common.deqSuccess := commonIn.issueResp.valid && commonIn.issueResp.bits.respType === RSFeedbackType.fuIdle && !hasIQWakeupGet.srcLoadCancelVec.asUInt.orR 152 common.srcWakeup := common.srcWakeupByWB.zip(hasIQWakeupGet.srcWakeupByIQ).map { case (x, y) => x || y.asUInt.orR } 153 common.srcWakeupByWB := commonIn.wakeUpFromWB.map(bundle => bundle.bits.wakeUp(status.srcStatus.map(_.psrc) zip status.srcStatus.map(_.srcType), bundle.valid)).transpose.map(x => VecInit(x.toSeq).asUInt.orR).toSeq 154 common.canIssue := validReg && status.canIssue 155 common.enqReady := !validReg || common.clear 156 if(isEnq) { 157 common.validRegNext := Mux(commonIn.enq.valid && common.enqReady, true.B, Mux(common.clear, false.B, validReg)) 158 common.clear := common.flushed || common.deqSuccess || commonIn.transSel 159 } else { 160 common.validRegNext := Mux(commonIn.enq.valid && commonIn.transSel, true.B, Mux(common.clear, false.B, validReg)) 161 common.clear := common.flushed || common.deqSuccess 162 } 163 } 164 165 class CommonIQWakeupBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 166 val srcWakeupByIQ = Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool())) 167 val srcWakeupByIQWithoutCancel = Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool())) 168 val srcWakeupByIQButCancel = Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool())) 169 val regSrcWakeupL1ExuOH = Vec(params.numRegSrc, ExuVec()) 170 val srcWakeupL1ExuOHOut = Vec(params.numRegSrc, ExuVec()) 171 val srcLoadDependencyOut = Vec(params.numRegSrc, Vec(LoadPipelineWidth, UInt(3.W))) 172 val wakeupLoadDependencyByIQVec = Vec(params.numWakeupFromIQ, Vec(LoadPipelineWidth, UInt(3.W))) 173 val shiftedWakeupLoadDependencyByIQVec = Vec(params.numWakeupFromIQ, Vec(LoadPipelineWidth, UInt(3.W))) 174 val shiftedWakeupLoadDependencyByIQBypassVec = Vec(params.numWakeupFromIQ, Vec(LoadPipelineWidth, UInt(3.W))) 175 val cancelVec = Vec(params.numRegSrc, Bool()) 176 val srcCancelVec = Vec(params.numRegSrc, Bool()) 177 val srcLoadCancelVec = Vec(params.numRegSrc, Bool()) 178 val canIssueBypass = Bool() 179 } 180 181 def CommonIQWakeupConnect(common: CommonWireBundle, hasIQWakeupGet: CommonIQWakeupBundle, validReg: Bool, status: Status, commonIn: CommonInBundle, isEnq: Boolean)(implicit p: Parameters, params: IssueBlockParams) = { 182 val wakeupVec: Seq[Seq[Bool]] = commonIn.wakeUpFromIQ.map((bundle: ValidIO[IssueQueueIQWakeUpBundle]) => 183 bundle.bits.wakeUpFromIQ(status.srcStatus.map(_.psrc) zip status.srcStatus.map(_.srcType)) 184 ).toSeq.transpose 185 val cancelSel = params.wakeUpSourceExuIdx.zip(commonIn.wakeUpFromIQ).map { case (x, y) => commonIn.og0Cancel(x) && y.bits.is0Lat } 186 187 hasIQWakeupGet.srcCancelVec.zip(hasIQWakeupGet.srcLoadCancelVec).zip(hasIQWakeupGet.srcWakeupByIQWithoutCancel).zipWithIndex.foreach { case (((srcCancel, srcLoadCancel), wakeUpByIQVec), srcIdx) => 188 val ldTransCancel = Mux1H(wakeUpByIQVec, hasIQWakeupGet.wakeupLoadDependencyByIQVec.map(dep => LoadShouldCancel(Some(dep), commonIn.ldCancel))) 189 srcLoadCancel := LoadShouldCancel(status.srcStatus(srcIdx).srcLoadDependency, commonIn.ldCancel) 190 srcCancel := srcLoadCancel || ldTransCancel 191 } 192 hasIQWakeupGet.cancelVec := hasIQWakeupGet.srcCancelVec 193 hasIQWakeupGet.srcWakeupByIQ := wakeupVec.map(x => VecInit(x.zip(cancelSel).map { case (wakeup, cancel) => wakeup && !cancel })) 194 hasIQWakeupGet.srcWakeupByIQButCancel := wakeupVec.map(x => VecInit(x.zip(cancelSel).map { case (wakeup, cancel) => wakeup && cancel })) 195 hasIQWakeupGet.srcWakeupByIQWithoutCancel := wakeupVec.map(x => VecInit(x)) 196 hasIQWakeupGet.wakeupLoadDependencyByIQVec := commonIn.wakeUpFromIQ.map(_.bits.loadDependency).toSeq 197 hasIQWakeupGet.regSrcWakeupL1ExuOH.zip(status.srcStatus.map(_.srcWakeUpL1ExuOH.get)).foreach { 198 case (exuOH, regExuOH) => 199 exuOH := 0.U.asTypeOf(exuOH) 200 params.wakeUpSourceExuIdx.foreach(x => exuOH(x) := regExuOH(x)) 201 } 202 hasIQWakeupGet.srcWakeupL1ExuOHOut.zip(hasIQWakeupGet.srcWakeupByIQWithoutCancel).zip(common.srcWakeup).zipWithIndex.foreach { 203 case (((exuOH: Vec[Bool], wakeUpByIQOH: Vec[Bool]), wakeUp: Bool), srcIdx) => 204 if(isEnq) { 205 ExuOHGen(exuOH, wakeUpByIQOH, wakeUp, status.srcStatus(srcIdx).srcWakeUpL1ExuOH.get) 206 } else { 207 ExuOHGen(exuOH, wakeUpByIQOH, wakeUp, hasIQWakeupGet.regSrcWakeupL1ExuOH(srcIdx)) 208 } 209 } 210 hasIQWakeupGet.srcLoadDependencyOut.zip(hasIQWakeupGet.srcWakeupByIQ).foreach { 211 case (loadDependencyOut, wakeUpByIQVec) => 212 loadDependencyOut := Mux1H(wakeUpByIQVec, hasIQWakeupGet.shiftedWakeupLoadDependencyByIQBypassVec) 213 } 214 hasIQWakeupGet.canIssueBypass := validReg && !status.issued && !status.blocked && 215 VecInit(status.srcStatus.map(_.srcState).zip(hasIQWakeupGet.srcWakeupByIQWithoutCancel).zipWithIndex.map { case ((state, wakeupVec), srcIdx) => 216 wakeupVec.asUInt.orR | state 217 }).asUInt.andR 218 } 219 220 221 def ShiftLoadDependency(hasIQWakeupGet: CommonIQWakeupBundle)(implicit p: Parameters, params: IssueBlockParams) = { 222 hasIQWakeupGet.shiftedWakeupLoadDependencyByIQVec 223 .zip(hasIQWakeupGet.wakeupLoadDependencyByIQVec) 224 .zip(params.wakeUpInExuSources.map(_.name)).foreach { 225 case ((deps, originalDeps), name) => deps.zip(originalDeps).zipWithIndex.foreach { 226 case ((dep, originalDep), deqPortIdx) => 227 if (name.contains("LDU") && name.replace("LDU", "").toInt == deqPortIdx) 228 dep := (originalDep << 2).asUInt | 2.U 229 else 230 dep := originalDep << 1 231 } 232 } 233 hasIQWakeupGet.shiftedWakeupLoadDependencyByIQBypassVec 234 .zip(hasIQWakeupGet.wakeupLoadDependencyByIQVec) 235 .zip(params.wakeUpInExuSources.map(_.name)).foreach { 236 case ((deps, originalDeps), name) => deps.zip(originalDeps).zipWithIndex.foreach { 237 case ((dep, originalDep), deqPortIdx) => 238 if (name.contains("LDU") && name.replace("LDU", "").toInt == deqPortIdx) 239 dep := (originalDep << 1).asUInt | 1.U 240 else 241 dep := originalDep 242 } 243 } 244 } 245 246 def EntryRegCommonConnect(common: CommonWireBundle, hasIQWakeup: Option[CommonIQWakeupBundle], validReg: Bool, entryRegNext: EntryBundle, entryReg: EntryBundle, status: Status, commonIn: CommonInBundle, isEnq: Boolean)(implicit p: Parameters, params: IssueBlockParams) = { 247 val hasIQWakeupGet = hasIQWakeup.getOrElse(0.U.asTypeOf(new CommonIQWakeupBundle)) 248 val cancelByLd = hasIQWakeupGet.srcCancelVec.asUInt.orR 249 val cancelWhenWakeup = VecInit(hasIQWakeupGet.srcWakeupByIQButCancel.map(_.asUInt.orR)).asUInt.orR 250 val respIssueFail = commonIn.issueResp.valid && RSFeedbackType.isBlocked(commonIn.issueResp.bits.respType) 251 val srcWakeupExuOH = if(isEnq) status.srcStatus.map(_.srcWakeUpL1ExuOH.getOrElse(0.U.asTypeOf(ExuVec()))) else hasIQWakeupGet.regSrcWakeupL1ExuOH 252 entryRegNext.status.robIdx := status.robIdx 253 entryRegNext.status.fuType := IQFuType.readFuType(status.fuType, params.getFuCfgs.map(_.fuType)) 254 entryRegNext.status.srcStatus.zip(status.srcStatus).zipWithIndex.foreach { case ((srcStatusNext, srcStatus), srcIdx) => 255 val cancel = hasIQWakeupGet.srcCancelVec(srcIdx) 256 val wakeupByIQ = hasIQWakeupGet.srcWakeupByIQ(srcIdx).asUInt.orR 257 val wakeupByIQOH = hasIQWakeupGet.srcWakeupByIQ(srcIdx) 258 val wakeup = common.srcWakeup(srcIdx) 259 srcStatusNext.psrc := srcStatus.psrc 260 srcStatusNext.srcType := srcStatus.srcType 261 srcStatusNext.srcState := Mux(cancel, false.B, wakeup | srcStatus.srcState) 262 srcStatusNext.dataSources.value := Mux(wakeupByIQ, DataSource.bypass, DataSource.reg) 263 if(params.hasIQWakeUp) { 264 srcStatusNext.srcTimer.get := MuxCase(3.U, Seq( 265 // T0: waked up by IQ, T1: reset timer as 1 266 wakeupByIQ -> 2.U, 267 // do not overflow 268 srcStatus.srcTimer.get.andR -> srcStatus.srcTimer.get, 269 // T2+: increase if the entry is valid, the src is ready, and the src is woken up by iq 270 (validReg && SrcState.isReady(srcStatus.srcState) && srcWakeupExuOH(srcIdx).asUInt.orR) -> (srcStatus.srcTimer.get + 1.U) 271 )) 272 ExuOHGen(srcStatusNext.srcWakeUpL1ExuOH.get, wakeupByIQOH, wakeup, srcWakeupExuOH(srcIdx)) 273 srcStatusNext.srcLoadDependency.get := 274 Mux(wakeup, 275 Mux1H(wakeupByIQOH, hasIQWakeupGet.shiftedWakeupLoadDependencyByIQVec), 276 Mux(validReg && srcStatus.srcLoadDependency.get.asUInt.orR, VecInit(srcStatus.srcLoadDependency.get.map(i => i(i.getWidth - 2, 0) << 1)), srcStatus.srcLoadDependency.get)) 277 } 278 } 279 entryRegNext.status.blocked := false.B 280 entryRegNext.status.issued := MuxCase(status.issued, Seq( 281 (cancelByLd || cancelWhenWakeup || respIssueFail) -> false.B, 282 commonIn.deqSel -> true.B, 283 !status.srcReady -> false.B, 284 )) 285 entryRegNext.status.firstIssue := commonIn.deqSel || status.firstIssue 286 entryRegNext.status.issueTimer := Mux(commonIn.deqSel, 0.U, Mux(status.issued, status.issueTimer + 1.U, "b10".U)) 287 entryRegNext.status.deqPortIdx := Mux(commonIn.deqSel, commonIn.deqPortIdxWrite, Mux(status.issued, status.deqPortIdx, 0.U)) 288 entryRegNext.imm.foreach(_ := entryReg.imm.get) 289 entryRegNext.payload := entryReg.payload 290 291 } 292 293 def CommonOutConnect(commonOut: CommonOutBundle, common: CommonWireBundle, hasIQWakeup: Option[CommonIQWakeupBundle], validReg: Bool, entryReg: EntryBundle, status: Status, commonIn: CommonInBundle, isEnq: Boolean)(implicit p: Parameters, params: IssueBlockParams) = { 294 val hasIQWakeupGet = hasIQWakeup.getOrElse(0.U.asTypeOf(new CommonIQWakeupBundle)) 295 val srcWakeupExuOH = if(isEnq) status.srcStatus.map(_.srcWakeUpL1ExuOH.getOrElse(0.U.asTypeOf(ExuVec()))) else hasIQWakeupGet.regSrcWakeupL1ExuOH 296 commonOut.valid := validReg 297 commonOut.canIssue := (common.canIssue || hasIQWakeupGet.canIssueBypass) && !common.flushed 298 commonOut.fuType := IQFuType.readFuType(status.fuType, params.getFuCfgs.map(_.fuType)).asUInt 299 commonOut.robIdx := status.robIdx 300 commonOut.dataSource.zipWithIndex.foreach{ case (dataSourceOut, srcIdx) => 301 dataSourceOut.value := Mux(hasIQWakeupGet.srcWakeupByIQ(srcIdx).asUInt.orR, DataSource.forward, status.srcStatus(srcIdx).dataSources.value) 302 } 303 commonOut.isFirstIssue := !status.firstIssue 304 commonOut.entry.valid := validReg 305 commonOut.entry.bits := entryReg 306 if(isEnq) { 307 commonOut.entry.bits.status := status 308 } 309 commonOut.issueTimerRead := status.issueTimer 310 commonOut.deqPortIdxRead := status.deqPortIdx 311 if(params.hasIQWakeUp) { 312 val wakeupSrcLoadDependency = hasIQWakeupGet.srcWakeupByIQWithoutCancel.map(x => Mux1H(x, hasIQWakeupGet.wakeupLoadDependencyByIQVec)) 313 commonOut.srcWakeUpL1ExuOH.get := Mux(hasIQWakeupGet.canIssueBypass && !common.canIssue, hasIQWakeupGet.srcWakeupL1ExuOHOut, VecInit(srcWakeupExuOH)) 314 commonOut.srcTimer.get.zipWithIndex.foreach { case (srcTimerOut, srcIdx) => 315 val wakeupByIQOH = hasIQWakeupGet.srcWakeupByIQWithoutCancel(srcIdx) 316 srcTimerOut := Mux(wakeupByIQOH.asUInt.orR, Mux1H(wakeupByIQOH, commonIn.wakeUpFromIQ.map(_.bits.is0Lat).toSeq).asUInt, status.srcStatus(srcIdx).srcTimer.get) 317 } 318 commonOut.entry.bits.status.srcStatus.map(_.srcLoadDependency.get).zipWithIndex.foreach { case (srcLoadDependencyOut, srcIdx) => 319 srcLoadDependencyOut := Mux(hasIQWakeupGet.canIssueBypass && !common.canIssue, hasIQWakeupGet.srcLoadDependencyOut(srcIdx), status.srcStatus(srcIdx).srcLoadDependency.get) 320 } 321 commonOut.srcLoadDependency.get.zipWithIndex.foreach { case (srcLoadDependencyOut, srcIdx) => 322 srcLoadDependencyOut := Mux(hasIQWakeupGet.canIssueBypass && !common.canIssue, VecInit(status.srcStatus(srcIdx).srcLoadDependency.get.zip(wakeupSrcLoadDependency(srcIdx)).map(x => x._1 | x._2)), status.srcStatus(srcIdx).srcLoadDependency.get) 323 } 324 } 325 commonOut.cancel.foreach(_ := hasIQWakeupGet.cancelVec.asUInt.orR) 326 if (params.isVecMemIQ) { 327 commonOut.uopIdx.get := status.vecMem.get.uopIdx 328 } 329 } 330 331 def EntryMemConnect(commonIn: CommonInBundle, common: CommonWireBundle, validReg: Bool, entryReg: EntryBundle, entryRegNext: EntryBundle, isEnq: Boolean)(implicit p: Parameters, params: IssueBlockParams) = { 332 val enqValid = if(isEnq) commonIn.enq.valid && (!validReg || common.clear) else commonIn.enq.valid && commonIn.transSel 333 val fromMem = commonIn.fromMem.get 334 val memStatus = entryReg.status.mem.get 335 val memStatusNext = entryRegNext.status.mem.get 336 337 // load cannot be issued before older store, unless meet some condition 338 val blockedByOlderStore = isAfter(memStatusNext.sqIdx, fromMem.stIssuePtr) 339 340 val deqFailedForStdInvalid = commonIn.issueResp.valid && commonIn.issueResp.bits.respType === RSFeedbackType.dataInvalid 341 342 val staWaitedReleased = Cat( 343 fromMem.memWaitUpdateReq.robIdx.map(x => x.valid && x.bits.value === memStatusNext.waitForRobIdx.value) 344 ).orR 345 val stdWaitedReleased = Cat( 346 fromMem.memWaitUpdateReq.sqIdx.map(x => x.valid && x.bits.value === memStatusNext.waitForSqIdx.value) 347 ).orR 348 val olderStaNotViolate = staWaitedReleased && !memStatusNext.strictWait 349 val olderStdReady = stdWaitedReleased && memStatusNext.waitForStd 350 val waitStd = !olderStdReady 351 val waitSta = !olderStaNotViolate 352 353 when(enqValid) { 354 memStatusNext.waitForSqIdx := commonIn.enq.bits.status.mem.get.waitForSqIdx 355 // update by lfst at dispatch stage 356 memStatusNext.waitForRobIdx := commonIn.enq.bits.status.mem.get.waitForRobIdx 357 // new load inst don't known if it is blocked by store data ahead of it 358 memStatusNext.waitForStd := false.B 359 // update by ssit at rename stage 360 memStatusNext.strictWait := commonIn.enq.bits.status.mem.get.strictWait 361 memStatusNext.sqIdx := commonIn.enq.bits.status.mem.get.sqIdx 362 }.elsewhen(deqFailedForStdInvalid) { 363 // Todo: check if need assign statusNext.block 364 memStatusNext.waitForSqIdx := commonIn.issueResp.bits.dataInvalidSqIdx 365 memStatusNext.waitForRobIdx := memStatus.waitForRobIdx 366 memStatusNext.waitForStd := true.B 367 memStatusNext.strictWait := memStatus.strictWait 368 memStatusNext.sqIdx := memStatus.sqIdx 369 }.otherwise { 370 memStatusNext := memStatus 371 } 372 373 val shouldBlock = Mux(commonIn.enq.valid && commonIn.transSel, commonIn.enq.bits.status.blocked, entryReg.status.blocked) 374 val blockNotReleased = waitStd || waitSta 375 val respBlock = deqFailedForStdInvalid 376 entryRegNext.status.blocked := shouldBlock && blockNotReleased && blockedByOlderStore || respBlock 377 shouldBlock && blockNotReleased && blockedByOlderStore || respBlock 378 } 379 380 def ExuOHGen(exuOH: Vec[Bool], wakeupByIQOH: Vec[Bool], wakeup: Bool, regSrcExuOH: Vec[Bool])(implicit p: Parameters, params: IssueBlockParams) = { 381 val origExuOH = 0.U.asTypeOf(exuOH) 382 when(wakeupByIQOH.asUInt.orR) { 383 origExuOH := Mux1H(wakeupByIQOH, params.wakeUpSourceExuIdx.map(x => MathUtils.IntToOH(x).U(p(XSCoreParamsKey).backendParams.numExu.W)).toSeq).asBools 384 }.elsewhen(wakeup) { 385 origExuOH := 0.U.asTypeOf(origExuOH) 386 }.otherwise { 387 origExuOH := regSrcExuOH 388 } 389 exuOH := 0.U.asTypeOf(exuOH) 390 params.wakeUpSourceExuIdx.foreach(x => exuOH(x) := origExuOH(x)) 391 } 392 393 object IQFuType { 394 def num = FuType.num 395 396 def apply() = Vec(num, Bool()) 397 398 def readFuType(fuType: Vec[Bool], fus: Seq[FuType.OHType]): Vec[Bool] = { 399 val res = 0.U.asTypeOf(fuType) 400 fus.foreach(x => res(x.id) := fuType(x.id)) 401 res 402 } 403 } 404} 405