1package xiangshan.backend.issue 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import utility.HasCircularQueuePtrHelper 7import utils._ 8import xiangshan._ 9import xiangshan.backend.Bundles._ 10import xiangshan.backend.datapath.DataConfig.VAddrData 11import xiangshan.backend.datapath.DataSource 12import xiangshan.backend.fu.FuType 13import xiangshan.backend.fu.vector.Utils.NOnes 14import xiangshan.backend.rob.RobPtr 15import xiangshan.mem.{LqPtr, MemWaitUpdateReq, SqPtr} 16import xiangshan.backend.issue.EntryBundles._ 17 18class Entries(implicit p: Parameters, params: IssueBlockParams) extends XSModule { 19 override def desiredName: String = params.getEntryName 20 21 require(params.numEnq <= 2, "number of enq should be no more than 2") 22 23 private val EnqEntryNum = params.numEnq 24 private val OthersEntryNum = params.numEntries - params.numEnq 25 private val SimpEntryNum = params.numSimp 26 private val CompEntryNum = params.numComp 27 val io = IO(new EntriesIO) 28 29 // only memAddrIQ use it 30 val memEtyResps: MixedVec[ValidIO[EntryDeqRespBundle]] = { 31 if (params.isLdAddrIQ && !params.isStAddrIQ) //LDU 32 MixedVecInit(io.og0Resp ++ io.og1Resp ++ io.fromLoad.get.finalIssueResp ++ io.fromLoad.get.memAddrIssueResp) 33 else if (params.isLdAddrIQ && params.isStAddrIQ || params.isHyAddrIQ) //HYU 34 MixedVecInit(io.og0Resp ++ io.og1Resp ++ io.fromLoad.get.finalIssueResp ++ io.fromLoad.get.memAddrIssueResp ++ io.fromMem.get.fastResp ++ io.fromMem.get.slowResp) 35 else if (params.isStAddrIQ) //STU, VLDU, VSTU 36 MixedVecInit(io.og0Resp ++ io.og1Resp ++ io.fromMem.get.slowResp) 37 else if (params.isVecLduIQ || params.isVecStuIQ) 38 MixedVecInit(io.og0Resp ++ io.og1Resp ++ io.fromMem.get.slowResp) 39 else MixedVecInit(Seq()) 40 } 41 42 val resps: Vec[Vec[ValidIO[EntryDeqRespBundle]]] = VecInit(io.og0Resp, io.og1Resp, 0.U.asTypeOf(io.og0Resp)) 43 44 //Module 45 val enqEntries = Seq.fill(EnqEntryNum)(Module(EnqEntry(isComp = true)(p, params))) 46 val othersEntriesSimp = Seq.fill(SimpEntryNum)(Module(OthersEntry(isComp = false)(p, params))) 47 val othersEntriesComp = Seq.fill(CompEntryNum)(Module(OthersEntry(isComp = true)(p, params))) 48 val othersEntries = othersEntriesSimp ++ othersEntriesComp 49 val othersTransPolicy = OptionWrapper(params.isAllComp || params.isAllSimp, Module(new EnqPolicy)) 50 val simpTransPolicy = OptionWrapper(params.hasCompAndSimp, Module(new EnqPolicy)) 51 val compTransPolicy = OptionWrapper(params.hasCompAndSimp, Module(new EnqPolicy)) 52 53 //Wire 54 //entries status 55 val entries = Wire(Vec(params.numEntries, ValidIO(new EntryBundle))) 56 val robIdxVec = Wire(Vec(params.numEntries, new RobPtr)) 57 val validVec = Wire(Vec(params.numEntries, Bool())) 58 val canIssueVec = Wire(Vec(params.numEntries, Bool())) 59 val fuTypeVec = Wire(Vec(params.numEntries, FuType())) 60 val isFirstIssueVec = Wire(Vec(params.numEntries, Bool())) 61 val issueTimerVec = Wire(Vec(params.numEntries, UInt(2.W))) 62 val uopIdxVec = OptionWrapper(params.isVecMemIQ, Wire(Vec(params.numEntries, UopIdx()))) 63 //src status 64 val dataSourceVec = Wire(Vec(params.numEntries, Vec(params.numRegSrc, DataSource()))) 65 val loadDependencyVec = Wire(Vec(params.numEntries, Vec(LoadPipelineWidth, UInt(3.W)))) 66 val srcLoadDependencyVec= Wire(Vec(params.numEntries, Vec(params.numRegSrc, Vec(LoadPipelineWidth, UInt(3.W))))) 67 val srcTimerVec = OptionWrapper(params.hasIQWakeUp, Wire(Vec(params.numEntries, Vec(params.numRegSrc, UInt(3.W))))) 68 val srcWakeUpL1ExuOHVec = OptionWrapper(params.hasIQWakeUp, Wire(Vec(params.numEntries, Vec(params.numRegSrc, ExuVec())))) 69 //deq sel 70 val deqSelVec = Wire(Vec(params.numEntries, Bool())) 71 val issueRespVec = Wire(Vec(params.numEntries, ValidIO(new EntryDeqRespBundle))) 72 val deqPortIdxWriteVec = Wire(Vec(params.numEntries, UInt(1.W))) 73 val deqPortIdxReadVec = Wire(Vec(params.numEntries, UInt(1.W))) 74 //trans sel 75 val othersEntryEnqReadyVec = Wire(Vec(OthersEntryNum, Bool())) 76 val othersEntryEnqVec = Wire(Vec(OthersEntryNum, Valid(new EntryBundle))) 77 val enqEntryTransVec = Wire(Vec(EnqEntryNum, Valid(new EntryBundle))) 78 val simpEntryTransVec = OptionWrapper(params.hasCompAndSimp, Wire(Vec(SimpEntryNum, Valid(new EntryBundle)))) 79 val compEnqVec = OptionWrapper(params.hasCompAndSimp, Wire(Vec(EnqEntryNum, Valid(new EntryBundle)))) 80 81 val enqCanTrans2Simp = OptionWrapper(params.hasCompAndSimp, Wire(Bool())) 82 val enqCanTrans2Comp = OptionWrapper(params.hasCompAndSimp, Wire(Bool())) 83 val simpCanTrans2Comp = OptionWrapper(params.hasCompAndSimp, Wire(Vec(EnqEntryNum, Bool()))) 84 val simpTransSelVec = OptionWrapper(params.hasCompAndSimp, Wire(Vec(EnqEntryNum, Valid(UInt(SimpEntryNum.W))))) 85 val compTransSelVec = OptionWrapper(params.hasCompAndSimp, Wire(Vec(EnqEntryNum, Valid(UInt(CompEntryNum.W))))) 86 val finalSimpTransSelVec = OptionWrapper(params.hasCompAndSimp, Wire(Vec(EnqEntryNum, UInt(SimpEntryNum.W)))) 87 val finalCompTransSelVec = OptionWrapper(params.hasCompAndSimp, Wire(Vec(EnqEntryNum, UInt(CompEntryNum.W)))) 88 89 val enqCanTrans2Others = OptionWrapper(params.isAllComp || params.isAllSimp, Wire(Bool())) 90 val othersTransSelVec = OptionWrapper(params.isAllComp || params.isAllSimp, Wire(Vec(EnqEntryNum, Valid(UInt(OthersEntryNum.W))))) 91 val finalOthersTransSelVec = OptionWrapper(params.isAllComp || params.isAllSimp, Wire(Vec(EnqEntryNum, UInt(OthersEntryNum.W)))) 92 93 val simpEntryEnqReadyVec = othersEntryEnqReadyVec.take(SimpEntryNum) 94 val compEntryEnqReadyVec = othersEntryEnqReadyVec.takeRight(CompEntryNum) 95 val simpEntryEnqVec = othersEntryEnqVec.take(SimpEntryNum) 96 val compEntryEnqVec = othersEntryEnqVec.takeRight(CompEntryNum) 97 //debug 98 val cancelVec = OptionWrapper(params.hasIQWakeUp, Wire(Vec(params.numEntries, Bool()))) 99 val entryInValidVec = Wire(Vec(params.numEntries, Bool())) 100 val entryOutDeqValidVec = Wire(Vec(params.numEntries, Bool())) 101 val entryOutTransValidVec = Wire(Vec(params.numEntries, Bool())) 102 //cancel bypass 103 val cancelBypassVec = Wire(Vec(params.numEntries, Bool())) 104 105 106 //enqEntries 107 enqEntries.zipWithIndex.foreach { case (enqEntry, entryIdx) => 108 enqEntry.io.commonIn.enq := io.enq(entryIdx) 109 enqEntry.io.commonIn.transSel := (if (params.isAllComp || params.isAllSimp) enqCanTrans2Others.get && othersTransSelVec.get(entryIdx).valid 110 else enqCanTrans2Simp.get && simpTransSelVec.get(entryIdx).valid || enqCanTrans2Comp.get && compTransSelVec.get(entryIdx).valid) 111 EntriesConnect(enqEntry.io.commonIn, enqEntry.io.commonOut, entryIdx) 112 enqEntry.io.enqDelayWakeUpFromWB := RegEnable(io.wakeUpFromWB, io.enq(entryIdx).valid) 113 enqEntry.io.enqDelayWakeUpFromIQ := RegEnable(io.wakeUpFromIQ, io.enq(entryIdx).valid) 114 enqEntry.io.enqDelayOg0Cancel := RegNext(io.og0Cancel.asUInt) 115 enqEntry.io.enqDelayLdCancel := RegNext(io.ldCancel) 116 enqEntryTransVec(entryIdx) := enqEntry.io.commonOut.transEntry 117 } 118 //othersEntries 119 othersEntries.zipWithIndex.foreach { case (othersEntry, entryIdx) => 120 othersEntry.io.commonIn.enq := othersEntryEnqVec(entryIdx) 121 othersEntry.io.commonIn.transSel := (if (params.hasCompAndSimp && (entryIdx < SimpEntryNum)) 122 io.simpEntryDeqSelVec.get.zip(simpCanTrans2Comp.get).map(x => x._1(entryIdx) && x._2).reduce(_ | _) 123 else false.B) 124 EntriesConnect(othersEntry.io.commonIn, othersEntry.io.commonOut, entryIdx + EnqEntryNum) 125 othersEntryEnqReadyVec(entryIdx) := othersEntry.io.commonOut.enqReady 126 if (params.hasCompAndSimp && (entryIdx < SimpEntryNum)) { 127 simpEntryTransVec.get(entryIdx) := othersEntry.io.commonOut.transEntry 128 } 129 } 130 131 132 deqSelVec.zip(deqPortIdxWriteVec).zipWithIndex.foreach { case ((deqSel, deqPortIdxWrite), i) => 133 val deqVec = io.deqSelOH.zip(io.deqReady).map(x => x._1.valid && x._1.bits(i) && x._2) 134 deqPortIdxWrite := OHToUInt(deqVec) 135 deqSel := deqVec.reduce(_ | _) 136 } 137 138 139 if (params.isAllComp || params.isAllSimp) { 140 //transPolicy 141 othersTransPolicy.get.io.canEnq := othersEntryEnqReadyVec.asUInt 142 143 // we only allow all or none of the enq entries transfering to others entries. 144 enqCanTrans2Others.get := PopCount(validVec.take(EnqEntryNum)) <= PopCount(othersEntryEnqReadyVec) 145 // othersTransSelVec(i) is the target others entry for enq entry [i]. 146 // note that dispatch does not guarantee the validity of enq entries with low index. 147 // that means in some cases enq entry [0] is invalid while enq entry [1] is valid. 148 // in this case, enq entry [1] should use result [0] of TransPolicy. 149 othersTransSelVec.get(0).valid := othersTransPolicy.get.io.enqSelOHVec(0).valid && validVec(0) 150 othersTransSelVec.get(0).bits := othersTransPolicy.get.io.enqSelOHVec(0).bits 151 if (params.numEnq == 2) { 152 othersTransSelVec.get(1).valid := Mux(!validVec(0), othersTransPolicy.get.io.enqSelOHVec(0).valid, othersTransPolicy.get.io.enqSelOHVec(1).valid) 153 othersTransSelVec.get(1).bits := Mux(!validVec(0), othersTransPolicy.get.io.enqSelOHVec(0).bits, othersTransPolicy.get.io.enqSelOHVec(1).bits) 154 } 155 156 finalOthersTransSelVec.get.zip(othersTransSelVec.get).zipWithIndex.foreach { case ((finalOH, selOH), enqIdx) => 157 finalOH := Fill(OthersEntryNum, enqCanTrans2Others.get && selOH.valid) & selOH.bits 158 } 159 160 //othersEntryEnq 161 othersEntryEnqVec.zipWithIndex.foreach { case (othersEntryEnq, othersIdx) => 162 val othersEnqOH = finalOthersTransSelVec.get.map(_(othersIdx)) 163 if (othersEnqOH.size == 1) 164 othersEntryEnq := Mux(othersEnqOH.head, enqEntryTransVec.head, 0.U.asTypeOf(enqEntryTransVec.head)) 165 else 166 othersEntryEnq := Mux1H(othersEnqOH, enqEntryTransVec) 167 } 168 } 169 else { 170 //transPolicy 171 simpTransPolicy.get.io.canEnq := VecInit(simpEntryEnqReadyVec).asUInt 172 compTransPolicy.get.io.canEnq := VecInit(validVec.takeRight(CompEntryNum).map(!_)).asUInt 173 174 // we only allow all or none of the enq entries transfering to comp/simp entries. 175 // when all of simp entries are empty and comp entries are enough, transfer to comp entries. 176 // otherwise, transfer to simp entries. 177 enqCanTrans2Comp.get := PopCount(validVec.take(EnqEntryNum)) <= PopCount(validVec.takeRight(CompEntryNum).map(!_)) && !validVec.drop(EnqEntryNum).take(SimpEntryNum).reduce(_ || _) 178 enqCanTrans2Simp.get := !enqCanTrans2Comp.get && PopCount(validVec.take(EnqEntryNum)) <= PopCount(simpEntryEnqReadyVec) 179 simpCanTrans2Comp.get.zipWithIndex.foreach { case (canTrans, idx) => 180 canTrans := !enqCanTrans2Comp.get && PopCount(validVec.takeRight(CompEntryNum).map(!_)) >= (idx + 1).U 181 } 182 183 // simp/compTransSelVec(i) is the target simp/comp entry for enq entry [i]. 184 // note that dispatch does not guarantee the validity of enq entries with low index. 185 // that means in some cases enq entry [0] is invalid while enq entry [1] is valid. 186 // in this case, enq entry [1] should use result [0] of TransPolicy. 187 simpTransSelVec.get(0).valid := simpTransPolicy.get.io.enqSelOHVec(0).valid && validVec(0) 188 simpTransSelVec.get(0).bits := simpTransPolicy.get.io.enqSelOHVec(0).bits 189 compTransSelVec.get(0).valid := compTransPolicy.get.io.enqSelOHVec(0).valid && validVec(0) 190 compTransSelVec.get(0).bits := compTransPolicy.get.io.enqSelOHVec(0).bits 191 if (params.numEnq == 2) { 192 simpTransSelVec.get(1).valid := Mux(!validVec(0), simpTransPolicy.get.io.enqSelOHVec(0).valid, simpTransPolicy.get.io.enqSelOHVec(1).valid) 193 simpTransSelVec.get(1).bits := Mux(!validVec(0), simpTransPolicy.get.io.enqSelOHVec(0).bits, simpTransPolicy.get.io.enqSelOHVec(1).bits) 194 compTransSelVec.get(1).valid := Mux(!validVec(0), compTransPolicy.get.io.enqSelOHVec(0).valid, compTransPolicy.get.io.enqSelOHVec(1).valid) 195 compTransSelVec.get(1).bits := Mux(!validVec(0), compTransPolicy.get.io.enqSelOHVec(0).bits, compTransPolicy.get.io.enqSelOHVec(1).bits) 196 } 197 198 finalSimpTransSelVec.get.zip(simpTransSelVec.get).zipWithIndex.foreach { case ((finalOH, selOH), enqIdx) => 199 finalOH := Fill(SimpEntryNum, enqCanTrans2Simp.get && selOH.valid) & selOH.bits 200 } 201 finalCompTransSelVec.get.zip(compTransSelVec.get).zip(compTransPolicy.get.io.enqSelOHVec).zipWithIndex.foreach { 202 case (((finalOH, selOH), origSelOH), enqIdx) => 203 finalOH := Mux(enqCanTrans2Comp.get, Fill(CompEntryNum, selOH.valid) & selOH.bits, Fill(CompEntryNum, origSelOH.valid) & origSelOH.bits) 204 } 205 206 //othersEntryEnq 207 simpEntryEnqVec.zipWithIndex.foreach { case (simpEntryEnq, simpIdx) => 208 val simpEnqOH = finalSimpTransSelVec.get.map(_(simpIdx)) 209 // shit Mux1H directly returns in(0) if the seq has only 1 elements 210 if (simpEnqOH.size == 1) 211 simpEntryEnq := Mux(simpEnqOH.head, enqEntryTransVec.head, 0.U.asTypeOf(enqEntryTransVec.head)) 212 else 213 simpEntryEnq := Mux1H(simpEnqOH, enqEntryTransVec) 214 } 215 216 compEnqVec.get.zip(enqEntryTransVec).zip(io.simpEntryDeqSelVec.get).foreach { case ((compEnq, enqEntry), deqSel) => 217 compEnq := Mux(enqCanTrans2Comp.get, enqEntry, Mux1H(deqSel, simpEntryTransVec.get)) 218 } 219 compEntryEnqVec.zipWithIndex.foreach { case (compEntryEnq, compIdx) => 220 val compEnqOH = finalCompTransSelVec.get.map(_(compIdx)) 221 // shit Mux1H directly returns in(0) if the seq has only 1 elements 222 if (compEnqOH.size == 1) 223 compEntryEnq := Mux(compEnqOH.head, compEnqVec.get.head, 0.U.asTypeOf(compEnqVec.get.head)) 224 else 225 compEntryEnq := Mux1H(compEnqOH, compEnqVec.get) 226 } 227 228 assert(PopCount(simpEntryEnqVec.map(_.valid)) <= params.numEnq.U, "the number of simpEntryEnq is more than numEnq\n") 229 assert(PopCount(compEntryEnqVec.map(_.valid)) <= params.numEnq.U, "the number of compEntryEnq is more than numEnq\n") 230 } 231 232 if(backendParams.debugEn) { 233 dontTouch(othersEntryEnqVec) 234 } 235 236 //issueRespVec 237 if (params.isVecMemIQ) { 238 // vector memory IQ 239 issueRespVec.zip(robIdxVec).zip(uopIdxVec.get).foreach { case ((issueResp, robIdx), uopIdx) => 240 val hitRespsVec = VecInit(memEtyResps.map(x => 241 x.valid && x.bits.robIdx === robIdx && x.bits.uopIdx.get === uopIdx 242 ).toSeq) 243 issueResp.valid := hitRespsVec.reduce(_ | _) 244 issueResp.bits := Mux1H(hitRespsVec, memEtyResps.map(_.bits).toSeq) 245 } 246 } else if (params.isMemAddrIQ) { 247 // scalar memory IQ 248 issueRespVec.zip(robIdxVec).foreach { case (issueResp, robIdx) => 249 val hitRespsVec = VecInit(memEtyResps.map(x => x.valid && (x.bits.robIdx === robIdx)).toSeq) 250 issueResp.valid := hitRespsVec.reduce(_ | _) 251 issueResp.bits := Mux1H(hitRespsVec, memEtyResps.map(_.bits).toSeq) 252 } 253 } 254 else { 255 issueRespVec.zip(issueTimerVec).zip(deqPortIdxReadVec).foreach { case ((issueResp, issueTimer), deqPortIdx) => 256 val Resp = resps(issueTimer)(deqPortIdx) 257 issueResp := Resp 258 } 259 } 260 261 //deq 262 val enqEntryOldest = Wire(Vec(params.numDeq, ValidIO(new EntryBundle))) 263 val simpEntryOldest = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numDeq, ValidIO(new EntryBundle)))) 264 val compEntryOldest = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numDeq, ValidIO(new EntryBundle)))) 265 val othersEntryOldest = OptionWrapper(params.isAllComp || params.isAllSimp, Wire(Vec(params.numDeq, ValidIO(new EntryBundle)))) 266 val enqEntryOldestCancel = Wire(Vec(params.numDeq, Bool())) 267 val simpEntryOldestCancel = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numDeq, Bool()))) 268 val compEntryOldestCancel = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numDeq, Bool()))) 269 val othersEntryOldestCancel = OptionWrapper(params.isAllComp || params.isAllSimp, Wire(Vec(params.numDeq, Bool()))) 270 271 io.enqEntryOldestSel.zipWithIndex.map { case (sel, deqIdx) => 272 enqEntryOldest(deqIdx) := Mux1H(sel.bits, entries.take(EnqEntryNum)) 273 enqEntryOldestCancel(deqIdx) := Mux1H(sel.bits, cancelBypassVec.take(EnqEntryNum)) 274 } 275 276 if (params.isAllComp || params.isAllSimp) { 277 io.othersEntryOldestSel.get.zipWithIndex.map { case (sel, deqIdx) => 278 othersEntryOldest.get(deqIdx) := Mux1H(sel.bits, entries.drop(EnqEntryNum)) 279 othersEntryOldestCancel.get(deqIdx) := Mux1H(sel.bits, cancelBypassVec.drop(EnqEntryNum)) 280 } 281 } 282 else { 283 io.simpEntryOldestSel.get.zipWithIndex.map { case (sel, deqIdx) => 284 simpEntryOldest.get(deqIdx) := Mux1H(sel.bits, entries.drop(EnqEntryNum).take(SimpEntryNum)) 285 simpEntryOldestCancel.get(deqIdx) := Mux1H(sel.bits, cancelBypassVec.drop(EnqEntryNum).take(SimpEntryNum)) 286 } 287 io.compEntryOldestSel.get.zipWithIndex.map { case (sel, deqIdx) => 288 compEntryOldest.get(deqIdx) := Mux1H(sel.bits, entries.drop(EnqEntryNum).takeRight(CompEntryNum)) 289 compEntryOldestCancel.get(deqIdx) := Mux1H(sel.bits, cancelBypassVec.drop(EnqEntryNum).takeRight(CompEntryNum)) 290 } 291 } 292 293 if (params.deqFuSame) { 294 val subDeqPolicyEntryVec = Wire(Vec(params.numDeq, ValidIO(new EntryBundle))) 295 val subDeqPolicyValidVec = Wire(Vec(params.numDeq, Bool())) 296 val subDeqPolicyCancelBypassVec = Wire(Vec(params.numDeq, Bool())) 297 298 subDeqPolicyValidVec(0) := PopCount(io.subDeqRequest.get(0)) >= 1.U 299 subDeqPolicyValidVec(1) := PopCount(io.subDeqRequest.get(0)) >= 2.U 300 301 if (params.isAllComp || params.isAllSimp) { 302 subDeqPolicyEntryVec(0) := PriorityMux(io.subDeqRequest.get(0), entries) 303 subDeqPolicyEntryVec(1) := PriorityMux(Reverse(io.subDeqRequest.get(0)), entries.reverse) 304 subDeqPolicyCancelBypassVec(0) := PriorityMux(io.subDeqRequest.get(0), cancelBypassVec) 305 subDeqPolicyCancelBypassVec(1) := PriorityMux(Reverse(io.subDeqRequest.get(0)), cancelBypassVec.reverse) 306 307 io.deqEntry(0) := Mux(io.othersEntryOldestSel.get(0).valid, othersEntryOldest.get(0), subDeqPolicyEntryVec(1)) 308 io.deqEntry(1) := subDeqPolicyEntryVec(0) 309 io.cancelDeqVec(0) := Mux(io.othersEntryOldestSel.get(0).valid, othersEntryOldestCancel.get(0), subDeqPolicyCancelBypassVec(1)) 310 io.cancelDeqVec(1) := subDeqPolicyCancelBypassVec(0) 311 } 312 else { 313 subDeqPolicyEntryVec(0) := PriorityMux(Reverse(io.subDeqRequest.get(0)), entries.reverse) 314 subDeqPolicyEntryVec(1) := PriorityMux(io.subDeqRequest.get(0), entries) 315 subDeqPolicyCancelBypassVec(0) := PriorityMux(Reverse(io.subDeqRequest.get(0)), cancelBypassVec.reverse) 316 subDeqPolicyCancelBypassVec(1) := PriorityMux(io.subDeqRequest.get(0), cancelBypassVec) 317 318 io.deqEntry(0) := Mux(io.compEntryOldestSel.get(0).valid, 319 compEntryOldest.get(0), 320 Mux(io.simpEntryOldestSel.get(0).valid, simpEntryOldest.get(0), subDeqPolicyEntryVec(1))) 321 io.deqEntry(1) := subDeqPolicyEntryVec(0) 322 io.cancelDeqVec(0) := Mux(io.compEntryOldestSel.get(0).valid, 323 compEntryOldestCancel.get(0), 324 Mux(io.simpEntryOldestSel.get(0).valid, simpEntryOldestCancel.get(0), subDeqPolicyCancelBypassVec(1))) 325 io.cancelDeqVec(1) := subDeqPolicyCancelBypassVec(0) 326 } 327 328 when (subDeqPolicyValidVec(0)) { 329 assert(Mux1H(io.subDeqSelOH.get(0), entries).bits.status.robIdx === subDeqPolicyEntryVec(0).bits.status.robIdx, "subDeqSelOH(0) is not the same\n") 330 } 331 when (subDeqPolicyValidVec(1)) { 332 assert(Mux1H(io.subDeqSelOH.get(1), entries).bits.status.robIdx === subDeqPolicyEntryVec(1).bits.status.robIdx, "subDeqSelOH(1) is not the same\n") 333 } 334 } 335 else { 336 if (params.isAllComp || params.isAllSimp) { 337 io.othersEntryOldestSel.get.zipWithIndex.foreach { case (sel, i) => 338 io.deqEntry(i) := Mux(sel.valid, othersEntryOldest.get(i), enqEntryOldest(i)) 339 io.cancelDeqVec(i) := Mux(sel.valid, othersEntryOldestCancel.get(i), enqEntryOldestCancel(i)) 340 } 341 } 342 else { 343 io.compEntryOldestSel.get.zip(io.simpEntryOldestSel.get).zipWithIndex.foreach { case ((compSel, simpSel), i) => 344 io.deqEntry(i) := Mux(compSel.valid, 345 compEntryOldest.get(i), 346 Mux(simpSel.valid, simpEntryOldest.get(i), enqEntryOldest(i))) 347 io.cancelDeqVec(i) := Mux(compSel.valid, 348 compEntryOldestCancel.get(i), 349 Mux(simpSel.valid, simpEntryOldestCancel.get(i), enqEntryOldestCancel(i))) 350 } 351 } 352 } 353 354 if (params.hasIQWakeUp) { 355 cancelBypassVec.zip(srcWakeUpL1ExuOHVec.get).zip(srcTimerVec.get).zip(srcLoadDependencyVec).foreach{ case (((cancelBypass: Bool, l1ExuOH: Vec[Vec[Bool]]), srcTimer: Vec[UInt]), srcLoadDependency: Vec[Vec[UInt]]) => 356 val cancelByOg0 = l1ExuOH.zip(srcTimer).map { 357 case(exuOH, srcTimer) => 358 (exuOH.asUInt & io.og0Cancel.asUInt).orR && srcTimer === 1.U 359 }.reduce(_ | _) 360 val cancelByLd = srcLoadDependency.map(x => LoadShouldCancel(Some(x), io.ldCancel)).reduce(_ | _) 361 cancelBypass := cancelByLd 362 } 363 } else { 364 cancelBypassVec.zip(srcLoadDependencyVec).foreach { case (cancelBypass, srcLoadDependency) => 365 val cancelByLd = srcLoadDependency.map(x => LoadShouldCancel(Some(x), io.ldCancel)).reduce(_ | _) 366 cancelBypass := cancelByLd 367 } 368 } 369 370 io.valid := validVec.asUInt 371 io.canIssue := canIssueVec.asUInt 372 io.fuType := fuTypeVec 373 io.dataSources := dataSourceVec 374 io.srcWakeUpL1ExuOH.foreach(_ := srcWakeUpL1ExuOHVec.get.map(x => VecInit(x.map(_.asUInt)))) 375 io.srcTimer.foreach(_ := srcTimerVec.get) 376 io.loadDependency := loadDependencyVec 377 io.isFirstIssue.zipWithIndex.foreach{ case (isFirstIssue, deqIdx) => 378 isFirstIssue := io.deqSelOH(deqIdx).valid && Mux1H(io.deqSelOH(deqIdx).bits, isFirstIssueVec) 379 } 380 io.simpEntryEnqSelVec.foreach(_ := finalSimpTransSelVec.get.zip(enqEntryTransVec).map(x => x._1 & Fill(SimpEntryNum, x._2.valid))) 381 io.compEntryEnqSelVec.foreach(_ := finalCompTransSelVec.get.zip(compEnqVec.get).map(x => x._1 & Fill(CompEntryNum, x._2.valid))) 382 io.othersEntryEnqSelVec.foreach(_ := finalOthersTransSelVec.get.zip(enqEntryTransVec).map(x => x._1 & Fill(OthersEntryNum, x._2.valid))) 383 io.robIdx.foreach(_ := robIdxVec) 384 io.uopIdx.foreach(_ := uopIdxVec.get) 385 io.cancel.foreach(_ := cancelVec.get) //for debug 386 387 def EntriesConnect(in: CommonInBundle, out: CommonOutBundle, entryIdx: Int) = { 388 in.flush := io.flush 389 in.wakeUpFromWB := io.wakeUpFromWB 390 in.wakeUpFromIQ := io.wakeUpFromIQ 391 in.og0Cancel := io.og0Cancel 392 in.og1Cancel := io.og1Cancel 393 in.ldCancel := io.ldCancel 394 in.deqSel := deqSelVec(entryIdx) 395 in.deqPortIdxWrite := deqPortIdxWriteVec(entryIdx) 396 in.issueResp := issueRespVec(entryIdx) 397 if (params.isVecMemIQ) { 398 in.fromLsq.get.sqDeqPtr := io.vecMemIn.get.sqDeqPtr 399 in.fromLsq.get.lqDeqPtr := io.vecMemIn.get.lqDeqPtr 400 } 401 validVec(entryIdx) := out.valid 402 canIssueVec(entryIdx) := out.canIssue 403 fuTypeVec(entryIdx) := out.fuType 404 robIdxVec(entryIdx) := out.robIdx 405 dataSourceVec(entryIdx) := out.dataSource 406 isFirstIssueVec(entryIdx) := out.isFirstIssue 407 entries(entryIdx) := out.entry 408 deqPortIdxReadVec(entryIdx) := out.deqPortIdxRead 409 issueTimerVec(entryIdx) := out.issueTimerRead 410 srcLoadDependencyVec(entryIdx) := out.srcLoadDependency 411 loadDependencyVec(entryIdx) := out.entry.bits.status.mergedLoadDependency 412 if (params.hasIQWakeUp) { 413 srcWakeUpL1ExuOHVec.get(entryIdx) := out.srcWakeUpL1ExuOH.get 414 srcTimerVec.get(entryIdx) := out.srcTimer.get 415 cancelVec.get(entryIdx) := out.cancel.get 416 } 417 if (params.isVecMemIQ) { 418 uopIdxVec.get(entryIdx) := out.uopIdx.get 419 } 420 entryInValidVec(entryIdx) := out.entryInValid 421 entryOutDeqValidVec(entryIdx) := out.entryOutDeqValid 422 entryOutTransValidVec(entryIdx) := out.entryOutTransValid 423 } 424 425 // entries perf counter 426 // enq 427 for (i <- 0 until params.numEnq) { 428 XSPerfAccumulate(s"enqEntry_${i}_in_cnt", entryInValidVec(i)) 429 XSPerfAccumulate(s"enqEntry_${i}_out_deq_cnt", entryOutDeqValidVec(i)) 430 XSPerfAccumulate(s"enqEntry_${i}_out_trans_cnt", entryOutTransValidVec(i)) 431 } 432 // simple 433 for (i <- 0 until params.numSimp) { 434 XSPerfAccumulate(s"simpEntry_${i}_in_cnt", entryInValidVec(i + params.numEnq)) 435 XSPerfAccumulate(s"simpEntry_${i}_out_deq_cnt", entryOutDeqValidVec(i + params.numEnq)) 436 XSPerfAccumulate(s"simpEntry_${i}_out_trans_cnt", entryOutTransValidVec(i + params.numEnq)) 437 } 438 // complex 439 for (i <- 0 until params.numComp) { 440 XSPerfAccumulate(s"compEntry_${i}_in_cnt", entryInValidVec(i + params.numEnq + params.numSimp)) 441 XSPerfAccumulate(s"compEntry_${i}_out_deq_cnt", entryOutDeqValidVec(i + params.numEnq + params.numSimp)) 442 XSPerfAccumulate(s"compEntry_${i}_out_trans_cnt", entryOutTransValidVec(i + params.numEnq + params.numSimp)) 443 } 444 // total 445 XSPerfAccumulate(s"enqEntry_all_in_cnt", PopCount(entryInValidVec.take(params.numEnq))) 446 XSPerfAccumulate(s"enqEntry_all_out_deq_cnt", PopCount(entryOutDeqValidVec.take(params.numEnq))) 447 XSPerfAccumulate(s"enqEntry_all_out_trans_cnt", PopCount(entryOutTransValidVec.take(params.numEnq))) 448 449 XSPerfAccumulate(s"othersEntry_all_in_cnt", PopCount(entryInValidVec.drop(params.numEnq))) 450 XSPerfAccumulate(s"othersEntry_all_out_deq_cnt", PopCount(entryOutDeqValidVec.drop(params.numEnq))) 451 XSPerfAccumulate(s"othersEntry_all_out_trans_cnt", PopCount(entryOutTransValidVec.drop(params.numEnq))) 452} 453 454class EntriesIO(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 455 val flush = Flipped(ValidIO(new Redirect)) 456 //enq 457 val enq = Vec(params.numEnq, Flipped(ValidIO(new EntryBundle))) 458 val og0Resp = Vec(params.numDeq, Flipped(ValidIO(new EntryDeqRespBundle))) 459 val og1Resp = Vec(params.numDeq, Flipped(ValidIO(new EntryDeqRespBundle))) 460 //deq sel 461 val deqReady = Vec(params.numDeq, Input(Bool())) 462 val deqSelOH = Vec(params.numDeq, Flipped(ValidIO(UInt(params.numEntries.W)))) 463 val enqEntryOldestSel = Vec(params.numDeq, Flipped(ValidIO(UInt(params.numEnq.W)))) 464 val simpEntryOldestSel = OptionWrapper(params.hasCompAndSimp, Vec(params.numDeq, Flipped(ValidIO(UInt(params.numSimp.W))))) 465 val compEntryOldestSel = OptionWrapper(params.hasCompAndSimp, Vec(params.numDeq, Flipped(ValidIO(UInt(params.numComp.W))))) 466 val othersEntryOldestSel= OptionWrapper(params.isAllComp || params.isAllSimp, Vec(params.numDeq, Flipped(ValidIO(UInt((params.numEntries - params.numEnq).W))))) 467 val subDeqRequest = OptionWrapper(params.deqFuSame, Vec(params.numDeq, Input(UInt(params.numEntries.W)))) 468 val subDeqSelOH = OptionWrapper(params.deqFuSame, Vec(params.numDeq, Input(UInt(params.numEntries.W)))) 469 // wakeup 470 val wakeUpFromWB: MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = Flipped(params.genWBWakeUpSinkValidBundle) 471 val wakeUpFromIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(params.genIQWakeUpSinkValidBundle) 472 val og0Cancel = Input(ExuOH(backendParams.numExu)) 473 val og1Cancel = Input(ExuOH(backendParams.numExu)) 474 val ldCancel = Vec(backendParams.LdExuCnt, Flipped(new LoadCancelIO)) 475 //entries status 476 val valid = Output(UInt(params.numEntries.W)) 477 val canIssue = Output(UInt(params.numEntries.W)) 478 val fuType = Vec(params.numEntries, Output(FuType())) 479 val dataSources = Vec(params.numEntries, Vec(params.numRegSrc, Output(DataSource()))) 480 val loadDependency = Vec(params.numEntries, Vec(LoadPipelineWidth, UInt(3.W))) 481 val srcWakeUpL1ExuOH = OptionWrapper(params.hasIQWakeUp, Vec(params.numEntries, Vec(params.numRegSrc, Output(ExuOH())))) 482 val srcTimer = OptionWrapper(params.hasIQWakeUp, Vec(params.numEntries, Vec(params.numRegSrc, Output(UInt(3.W))))) 483 //deq status 484 val isFirstIssue = Vec(params.numDeq, Output(Bool())) 485 val deqEntry = Vec(params.numDeq, ValidIO(new EntryBundle)) 486 val cancelDeqVec = Vec(params.numDeq, Output(Bool())) 487 488 // load/hybird only 489 val fromLoad = OptionWrapper(params.isLdAddrIQ || params.isHyAddrIQ, new Bundle { 490 val finalIssueResp = Vec(params.numDeq, Flipped(ValidIO(new EntryDeqRespBundle))) 491 val memAddrIssueResp = Vec(params.numDeq, Flipped(ValidIO(new EntryDeqRespBundle))) 492 }) 493 // mem only 494 val fromMem = OptionWrapper(params.isMemAddrIQ, new Bundle { 495 val slowResp = Vec(params.numDeq, Flipped(ValidIO(new EntryDeqRespBundle))) 496 val fastResp = Vec(params.numDeq, Flipped(ValidIO(new EntryDeqRespBundle))) 497 }) 498 // vec mem only 499 val vecMemIn = OptionWrapper(params.isVecMemIQ, new Bundle { 500 val sqDeqPtr = Input(new SqPtr) 501 val lqDeqPtr = Input(new LqPtr) 502 }) 503 val robIdx = OptionWrapper(params.isVecMemIQ, Output(Vec(params.numEntries, new RobPtr))) 504 val uopIdx = OptionWrapper(params.isVecMemIQ, Output(Vec(params.numEntries, UopIdx()))) 505 506 // trans 507 val simpEntryDeqSelVec = OptionWrapper(params.hasCompAndSimp, Vec(params.numEnq, Input(UInt(params.numSimp.W)))) 508 val simpEntryEnqSelVec = OptionWrapper(params.hasCompAndSimp, Vec(params.numEnq, Output(UInt(params.numSimp.W)))) 509 val compEntryEnqSelVec = OptionWrapper(params.hasCompAndSimp, Vec(params.numEnq, Output(UInt(params.numComp.W)))) 510 val othersEntryEnqSelVec = OptionWrapper(params.isAllComp || params.isAllSimp, Vec(params.numEnq, Output(UInt((params.numEntries - params.numEnq).W)))) 511 512 // debug 513 val cancel = OptionWrapper(params.hasIQWakeUp, Output(Vec(params.numEntries, Bool()))) 514 515 def wakeup = wakeUpFromWB ++ wakeUpFromIQ 516} 517