1package xiangshan.backend.issue 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import utility.HasCircularQueuePtrHelper 7import utils._ 8import xiangshan._ 9import xiangshan.backend.Bundles._ 10import xiangshan.backend.datapath.DataConfig.VAddrData 11import xiangshan.backend.datapath.DataSource 12import xiangshan.backend.fu.FuType 13import xiangshan.backend.fu.vector.Utils.NOnes 14import xiangshan.backend.rob.RobPtr 15import xiangshan.mem.{LqPtr, MemWaitUpdateReq, SqPtr} 16import xiangshan.backend.issue.EntryBundles._ 17 18class Entries(implicit p: Parameters, params: IssueBlockParams) extends XSModule { 19 override def desiredName: String = params.getEntryName 20 21 require(params.numEnq <= 2, "number of enq should be no more than 2") 22 23 private val EnqEntryNum = params.numEnq 24 private val OthersEntryNum = params.numEntries - params.numEnq 25 private val SimpEntryNum = params.numSimp 26 private val CompEntryNum = params.numComp 27 val io = IO(new EntriesIO) 28 29 // only memAddrIQ use it 30 val memEtyResps: MixedVec[ValidIO[EntryDeqRespBundle]] = { 31 if (params.isLdAddrIQ && !params.isStAddrIQ) //LDU 32 MixedVecInit(io.og0Resp ++ io.og1Resp ++ io.fromLoad.get.finalIssueResp ++ io.fromLoad.get.memAddrIssueResp) 33 else if (params.isLdAddrIQ && params.isStAddrIQ || params.isHyAddrIQ) //HYU 34 MixedVecInit(io.og0Resp ++ io.og1Resp ++ io.fromLoad.get.finalIssueResp ++ io.fromLoad.get.memAddrIssueResp ++ io.fromMem.get.fastResp ++ io.fromMem.get.slowResp) 35 else if (params.isMemAddrIQ) //STU, VLDU, VSTU 36 MixedVecInit(io.og0Resp ++ io.og1Resp ++ io.fromMem.get.slowResp) 37 else MixedVecInit(Seq()) 38 } 39 40 val resps: Vec[Vec[ValidIO[EntryDeqRespBundle]]] = { 41 if (params.inVfSchd) 42 VecInit(io.og0Resp, io.og1Resp, io.og2Resp.get, 0.U.asTypeOf(io.og0Resp)) 43 else 44 VecInit(io.og0Resp, io.og1Resp, 0.U.asTypeOf(io.og0Resp), 0.U.asTypeOf(io.og0Resp)) 45 } 46 47 //Module 48 val enqEntries = Seq.fill(EnqEntryNum)(Module(EnqEntry(isComp = true)(p, params))) 49 val othersEntriesSimp = Seq.fill(SimpEntryNum)(Module(OthersEntry(isComp = false)(p, params))) 50 val othersEntriesComp = Seq.fill(CompEntryNum)(Module(OthersEntry(isComp = true)(p, params))) 51 val othersEntries = othersEntriesSimp ++ othersEntriesComp 52 val othersTransPolicy = OptionWrapper(params.isAllComp || params.isAllSimp, Module(new EnqPolicy)) 53 val simpTransPolicy = OptionWrapper(params.hasCompAndSimp, Module(new EnqPolicy)) 54 val compTransPolicy = OptionWrapper(params.hasCompAndSimp, Module(new EnqPolicy)) 55 56 //Wire 57 //entries status 58 val entries = Wire(Vec(params.numEntries, ValidIO(new EntryBundle))) 59 val robIdxVec = Wire(Vec(params.numEntries, new RobPtr)) 60 val validVec = Wire(Vec(params.numEntries, Bool())) 61 val canIssueVec = Wire(Vec(params.numEntries, Bool())) 62 val fuTypeVec = Wire(Vec(params.numEntries, FuType())) 63 val isFirstIssueVec = Wire(Vec(params.numEntries, Bool())) 64 val issueTimerVec = Wire(Vec(params.numEntries, UInt(2.W))) 65 val uopIdxVec = OptionWrapper(params.isVecMemIQ, Wire(Vec(params.numEntries, UopIdx()))) 66 //src status 67 val dataSourceVec = Wire(Vec(params.numEntries, Vec(params.numRegSrc, DataSource()))) 68 val loadDependencyVec = Wire(Vec(params.numEntries, Vec(LoadPipelineWidth, UInt(3.W)))) 69 val srcLoadDependencyVec= Wire(Vec(params.numEntries, Vec(params.numRegSrc, Vec(LoadPipelineWidth, UInt(3.W))))) 70 val srcTimerVec = OptionWrapper(params.hasIQWakeUp, Wire(Vec(params.numEntries, Vec(params.numRegSrc, UInt(3.W))))) 71 val srcWakeUpL1ExuOHVec = OptionWrapper(params.hasIQWakeUp, Wire(Vec(params.numEntries, Vec(params.numRegSrc, ExuVec())))) 72 //deq sel 73 val deqSelVec = Wire(Vec(params.numEntries, Bool())) 74 val issueRespVec = Wire(Vec(params.numEntries, ValidIO(new EntryDeqRespBundle))) 75 val deqPortIdxWriteVec = Wire(Vec(params.numEntries, UInt(1.W))) 76 val deqPortIdxReadVec = Wire(Vec(params.numEntries, UInt(1.W))) 77 //trans sel 78 val othersEntryEnqReadyVec = Wire(Vec(OthersEntryNum, Bool())) 79 val othersEntryEnqVec = Wire(Vec(OthersEntryNum, Valid(new EntryBundle))) 80 val enqEntryTransVec = Wire(Vec(EnqEntryNum, Valid(new EntryBundle))) 81 val simpEntryTransVec = OptionWrapper(params.hasCompAndSimp, Wire(Vec(SimpEntryNum, Valid(new EntryBundle)))) 82 val compEnqVec = OptionWrapper(params.hasCompAndSimp, Wire(Vec(EnqEntryNum, Valid(new EntryBundle)))) 83 84 val enqCanTrans2Simp = OptionWrapper(params.hasCompAndSimp, Wire(Bool())) 85 val enqCanTrans2Comp = OptionWrapper(params.hasCompAndSimp, Wire(Bool())) 86 val simpCanTrans2Comp = OptionWrapper(params.hasCompAndSimp, Wire(Vec(EnqEntryNum, Bool()))) 87 val simpTransSelVec = OptionWrapper(params.hasCompAndSimp, Wire(Vec(EnqEntryNum, Valid(UInt(SimpEntryNum.W))))) 88 val compTransSelVec = OptionWrapper(params.hasCompAndSimp, Wire(Vec(EnqEntryNum, Valid(UInt(CompEntryNum.W))))) 89 val finalSimpTransSelVec = OptionWrapper(params.hasCompAndSimp, Wire(Vec(EnqEntryNum, UInt(SimpEntryNum.W)))) 90 val finalCompTransSelVec = OptionWrapper(params.hasCompAndSimp, Wire(Vec(EnqEntryNum, UInt(CompEntryNum.W)))) 91 92 val enqCanTrans2Others = OptionWrapper(params.isAllComp || params.isAllSimp, Wire(Bool())) 93 val othersTransSelVec = OptionWrapper(params.isAllComp || params.isAllSimp, Wire(Vec(EnqEntryNum, Valid(UInt(OthersEntryNum.W))))) 94 val finalOthersTransSelVec = OptionWrapper(params.isAllComp || params.isAllSimp, Wire(Vec(EnqEntryNum, UInt(OthersEntryNum.W)))) 95 96 val simpEntryEnqReadyVec = othersEntryEnqReadyVec.take(SimpEntryNum) 97 val compEntryEnqReadyVec = othersEntryEnqReadyVec.takeRight(CompEntryNum) 98 val simpEntryEnqVec = othersEntryEnqVec.take(SimpEntryNum) 99 val compEntryEnqVec = othersEntryEnqVec.takeRight(CompEntryNum) 100 //debug 101 val entryInValidVec = Wire(Vec(params.numEntries, Bool())) 102 val entryOutDeqValidVec = Wire(Vec(params.numEntries, Bool())) 103 val entryOutTransValidVec = Wire(Vec(params.numEntries, Bool())) 104 val perfLdCancelVec = OptionWrapper(params.hasIQWakeUp, Wire(Vec(params.numEntries, Vec(params.numRegSrc, Bool())))) 105 val perfOg0CancelVec = OptionWrapper(params.hasIQWakeUp, Wire(Vec(params.numEntries, Vec(params.numRegSrc, Bool())))) 106 val perfWakeupByWBVec = Wire(Vec(params.numEntries, Vec(params.numRegSrc, Bool()))) 107 val perfWakeupByIQVec = OptionWrapper(params.hasIQWakeUp, Wire(Vec(params.numEntries, Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool()))))) 108 //cancel bypass 109 val cancelBypassVec = Wire(Vec(params.numEntries, Bool())) 110 111 112 //enqEntries 113 enqEntries.zipWithIndex.foreach { case (enqEntry, entryIdx) => 114 enqEntry.io.commonIn.enq := io.enq(entryIdx) 115 enqEntry.io.commonIn.transSel := (if (params.isAllComp || params.isAllSimp) enqCanTrans2Others.get && othersTransSelVec.get(entryIdx).valid 116 else enqCanTrans2Simp.get && simpTransSelVec.get(entryIdx).valid || enqCanTrans2Comp.get && compTransSelVec.get(entryIdx).valid) 117 EntriesConnect(enqEntry.io.commonIn, enqEntry.io.commonOut, entryIdx) 118 enqEntry.io.enqDelayWakeUpFromWB := RegEnable(io.wakeUpFromWB, io.enq(entryIdx).valid) 119 enqEntry.io.enqDelayWakeUpFromIQ := RegEnable(io.wakeUpFromIQ, io.enq(entryIdx).valid) 120 enqEntry.io.enqDelayOg0Cancel := RegNext(io.og0Cancel.asUInt) 121 enqEntry.io.enqDelayLdCancel := RegNext(io.ldCancel) 122 enqEntryTransVec(entryIdx) := enqEntry.io.commonOut.transEntry 123 } 124 //othersEntries 125 othersEntries.zipWithIndex.foreach { case (othersEntry, entryIdx) => 126 othersEntry.io.commonIn.enq := othersEntryEnqVec(entryIdx) 127 othersEntry.io.commonIn.transSel := (if (params.hasCompAndSimp && (entryIdx < SimpEntryNum)) 128 io.simpEntryDeqSelVec.get.zip(simpCanTrans2Comp.get).map(x => x._1(entryIdx) && x._2).reduce(_ | _) 129 else false.B) 130 EntriesConnect(othersEntry.io.commonIn, othersEntry.io.commonOut, entryIdx + EnqEntryNum) 131 othersEntryEnqReadyVec(entryIdx) := othersEntry.io.commonOut.enqReady 132 if (params.hasCompAndSimp && (entryIdx < SimpEntryNum)) { 133 simpEntryTransVec.get(entryIdx) := othersEntry.io.commonOut.transEntry 134 } 135 } 136 137 138 deqSelVec.zip(deqPortIdxWriteVec).zipWithIndex.foreach { case ((deqSel, deqPortIdxWrite), i) => 139 val deqVec = io.deqSelOH.zip(io.deqReady).map(x => x._1.valid && x._1.bits(i) && x._2) 140 deqPortIdxWrite := OHToUInt(deqVec) 141 deqSel := deqVec.reduce(_ | _) 142 } 143 144 145 if (params.isAllComp || params.isAllSimp) { 146 //transPolicy 147 othersTransPolicy.get.io.canEnq := othersEntryEnqReadyVec.asUInt 148 149 // we only allow all or none of the enq entries transfering to others entries. 150 enqCanTrans2Others.get := PopCount(validVec.take(EnqEntryNum)) <= PopCount(othersEntryEnqReadyVec) 151 // othersTransSelVec(i) is the target others entry for enq entry [i]. 152 // note that dispatch does not guarantee the validity of enq entries with low index. 153 // that means in some cases enq entry [0] is invalid while enq entry [1] is valid. 154 // in this case, enq entry [1] should use result [0] of TransPolicy. 155 othersTransSelVec.get(0).valid := othersTransPolicy.get.io.enqSelOHVec(0).valid && validVec(0) 156 othersTransSelVec.get(0).bits := othersTransPolicy.get.io.enqSelOHVec(0).bits 157 if (params.numEnq == 2) { 158 othersTransSelVec.get(1).valid := Mux(!validVec(0), othersTransPolicy.get.io.enqSelOHVec(0).valid, othersTransPolicy.get.io.enqSelOHVec(1).valid) 159 othersTransSelVec.get(1).bits := Mux(!validVec(0), othersTransPolicy.get.io.enqSelOHVec(0).bits, othersTransPolicy.get.io.enqSelOHVec(1).bits) 160 } 161 162 finalOthersTransSelVec.get.zip(othersTransSelVec.get).zipWithIndex.foreach { case ((finalOH, selOH), enqIdx) => 163 finalOH := Fill(OthersEntryNum, enqCanTrans2Others.get && selOH.valid) & selOH.bits 164 } 165 166 //othersEntryEnq 167 othersEntryEnqVec.zipWithIndex.foreach { case (othersEntryEnq, othersIdx) => 168 val othersEnqOH = finalOthersTransSelVec.get.map(_(othersIdx)) 169 if (othersEnqOH.size == 1) 170 othersEntryEnq := Mux(othersEnqOH.head, enqEntryTransVec.head, 0.U.asTypeOf(enqEntryTransVec.head)) 171 else 172 othersEntryEnq := Mux1H(othersEnqOH, enqEntryTransVec) 173 } 174 } 175 else { 176 //transPolicy 177 simpTransPolicy.get.io.canEnq := VecInit(simpEntryEnqReadyVec).asUInt 178 compTransPolicy.get.io.canEnq := VecInit(validVec.takeRight(CompEntryNum).map(!_)).asUInt 179 180 // we only allow all or none of the enq entries transfering to comp/simp entries. 181 // when all of simp entries are empty and comp entries are enough, transfer to comp entries. 182 // otherwise, transfer to simp entries. 183 enqCanTrans2Comp.get := PopCount(validVec.take(EnqEntryNum)) <= PopCount(validVec.takeRight(CompEntryNum).map(!_)) && !validVec.drop(EnqEntryNum).take(SimpEntryNum).reduce(_ || _) 184 enqCanTrans2Simp.get := !enqCanTrans2Comp.get && PopCount(validVec.take(EnqEntryNum)) <= PopCount(simpEntryEnqReadyVec) 185 simpCanTrans2Comp.get.zipWithIndex.foreach { case (canTrans, idx) => 186 canTrans := !enqCanTrans2Comp.get && PopCount(validVec.takeRight(CompEntryNum).map(!_)) >= (idx + 1).U 187 } 188 189 // simp/compTransSelVec(i) is the target simp/comp entry for enq entry [i]. 190 // note that dispatch does not guarantee the validity of enq entries with low index. 191 // that means in some cases enq entry [0] is invalid while enq entry [1] is valid. 192 // in this case, enq entry [1] should use result [0] of TransPolicy. 193 simpTransSelVec.get(0).valid := simpTransPolicy.get.io.enqSelOHVec(0).valid && validVec(0) 194 simpTransSelVec.get(0).bits := simpTransPolicy.get.io.enqSelOHVec(0).bits 195 compTransSelVec.get(0).valid := compTransPolicy.get.io.enqSelOHVec(0).valid && validVec(0) 196 compTransSelVec.get(0).bits := compTransPolicy.get.io.enqSelOHVec(0).bits 197 if (params.numEnq == 2) { 198 simpTransSelVec.get(1).valid := Mux(!validVec(0), simpTransPolicy.get.io.enqSelOHVec(0).valid, simpTransPolicy.get.io.enqSelOHVec(1).valid) 199 simpTransSelVec.get(1).bits := Mux(!validVec(0), simpTransPolicy.get.io.enqSelOHVec(0).bits, simpTransPolicy.get.io.enqSelOHVec(1).bits) 200 compTransSelVec.get(1).valid := Mux(!validVec(0), compTransPolicy.get.io.enqSelOHVec(0).valid, compTransPolicy.get.io.enqSelOHVec(1).valid) 201 compTransSelVec.get(1).bits := Mux(!validVec(0), compTransPolicy.get.io.enqSelOHVec(0).bits, compTransPolicy.get.io.enqSelOHVec(1).bits) 202 } 203 204 finalSimpTransSelVec.get.zip(simpTransSelVec.get).zipWithIndex.foreach { case ((finalOH, selOH), enqIdx) => 205 finalOH := Fill(SimpEntryNum, enqCanTrans2Simp.get && selOH.valid) & selOH.bits 206 } 207 finalCompTransSelVec.get.zip(compTransSelVec.get).zip(compTransPolicy.get.io.enqSelOHVec).zipWithIndex.foreach { 208 case (((finalOH, selOH), origSelOH), enqIdx) => 209 finalOH := Mux(enqCanTrans2Comp.get, Fill(CompEntryNum, selOH.valid) & selOH.bits, Fill(CompEntryNum, origSelOH.valid) & origSelOH.bits) 210 } 211 212 //othersEntryEnq 213 simpEntryEnqVec.zipWithIndex.foreach { case (simpEntryEnq, simpIdx) => 214 val simpEnqOH = finalSimpTransSelVec.get.map(_(simpIdx)) 215 // shit Mux1H directly returns in(0) if the seq has only 1 elements 216 if (simpEnqOH.size == 1) 217 simpEntryEnq := Mux(simpEnqOH.head, enqEntryTransVec.head, 0.U.asTypeOf(enqEntryTransVec.head)) 218 else 219 simpEntryEnq := Mux1H(simpEnqOH, enqEntryTransVec) 220 } 221 222 compEnqVec.get.zip(enqEntryTransVec).zip(io.simpEntryDeqSelVec.get).foreach { case ((compEnq, enqEntry), deqSel) => 223 compEnq := Mux(enqCanTrans2Comp.get, enqEntry, Mux1H(deqSel, simpEntryTransVec.get)) 224 } 225 compEntryEnqVec.zipWithIndex.foreach { case (compEntryEnq, compIdx) => 226 val compEnqOH = finalCompTransSelVec.get.map(_(compIdx)) 227 // shit Mux1H directly returns in(0) if the seq has only 1 elements 228 if (compEnqOH.size == 1) 229 compEntryEnq := Mux(compEnqOH.head, compEnqVec.get.head, 0.U.asTypeOf(compEnqVec.get.head)) 230 else 231 compEntryEnq := Mux1H(compEnqOH, compEnqVec.get) 232 } 233 234 assert(PopCount(simpEntryEnqVec.map(_.valid)) <= params.numEnq.U, "the number of simpEntryEnq is more than numEnq\n") 235 assert(PopCount(compEntryEnqVec.map(_.valid)) <= params.numEnq.U, "the number of compEntryEnq is more than numEnq\n") 236 } 237 238 if(backendParams.debugEn) { 239 dontTouch(othersEntryEnqVec) 240 } 241 242 //issueRespVec 243 if (params.isVecMemIQ) { 244 // vector memory IQ 245 issueRespVec.zip(robIdxVec).zip(uopIdxVec.get).foreach { case ((issueResp, robIdx), uopIdx) => 246 val hitRespsVec = VecInit(resps.flatten.map(x => 247 x.valid && x.bits.robIdx === robIdx && x.bits.uopIdx.get === uopIdx 248 )) 249 issueResp.valid := hitRespsVec.reduce(_ | _) 250 issueResp.bits := Mux1H(hitRespsVec, resps.flatten.map(_.bits)) 251 } 252 } else if (params.isMemAddrIQ) { 253 // scalar memory IQ 254 issueRespVec.zip(robIdxVec).foreach { case (issueResp, robIdx) => 255 val hitRespsVec = VecInit(memEtyResps.map(x => x.valid && (x.bits.robIdx === robIdx)).toSeq) 256 issueResp.valid := hitRespsVec.reduce(_ | _) 257 issueResp.bits := Mux1H(hitRespsVec, memEtyResps.map(_.bits).toSeq) 258 } 259 } 260 else { 261 issueRespVec.zip(issueTimerVec).zip(deqPortIdxReadVec).foreach { case ((issueResp, issueTimer), deqPortIdx) => 262 val Resp = resps(issueTimer)(deqPortIdx) 263 issueResp := Resp 264 } 265 } 266 267 //deq 268 val enqEntryOldest = Wire(Vec(params.numDeq, ValidIO(new EntryBundle))) 269 val simpEntryOldest = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numDeq, ValidIO(new EntryBundle)))) 270 val compEntryOldest = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numDeq, ValidIO(new EntryBundle)))) 271 val othersEntryOldest = OptionWrapper(params.isAllComp || params.isAllSimp, Wire(Vec(params.numDeq, ValidIO(new EntryBundle)))) 272 val enqEntryOldestCancel = Wire(Vec(params.numDeq, Bool())) 273 val simpEntryOldestCancel = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numDeq, Bool()))) 274 val compEntryOldestCancel = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numDeq, Bool()))) 275 val othersEntryOldestCancel = OptionWrapper(params.isAllComp || params.isAllSimp, Wire(Vec(params.numDeq, Bool()))) 276 277 io.enqEntryOldestSel.zipWithIndex.map { case (sel, deqIdx) => 278 enqEntryOldest(deqIdx) := Mux1H(sel.bits, entries.take(EnqEntryNum)) 279 enqEntryOldestCancel(deqIdx) := Mux1H(sel.bits, cancelBypassVec.take(EnqEntryNum)) 280 } 281 282 if (params.isAllComp || params.isAllSimp) { 283 io.othersEntryOldestSel.get.zipWithIndex.map { case (sel, deqIdx) => 284 othersEntryOldest.get(deqIdx) := Mux1H(sel.bits, entries.drop(EnqEntryNum)) 285 othersEntryOldestCancel.get(deqIdx) := Mux1H(sel.bits, cancelBypassVec.drop(EnqEntryNum)) 286 } 287 } 288 else { 289 io.simpEntryOldestSel.get.zipWithIndex.map { case (sel, deqIdx) => 290 simpEntryOldest.get(deqIdx) := Mux1H(sel.bits, entries.drop(EnqEntryNum).take(SimpEntryNum)) 291 simpEntryOldestCancel.get(deqIdx) := Mux1H(sel.bits, cancelBypassVec.drop(EnqEntryNum).take(SimpEntryNum)) 292 } 293 io.compEntryOldestSel.get.zipWithIndex.map { case (sel, deqIdx) => 294 compEntryOldest.get(deqIdx) := Mux1H(sel.bits, entries.drop(EnqEntryNum).takeRight(CompEntryNum)) 295 compEntryOldestCancel.get(deqIdx) := Mux1H(sel.bits, cancelBypassVec.drop(EnqEntryNum).takeRight(CompEntryNum)) 296 } 297 } 298 299 if (params.deqFuSame) { 300 val subDeqPolicyEntryVec = Wire(Vec(params.numDeq, ValidIO(new EntryBundle))) 301 val subDeqPolicyValidVec = Wire(Vec(params.numDeq, Bool())) 302 val subDeqPolicyCancelBypassVec = Wire(Vec(params.numDeq, Bool())) 303 304 subDeqPolicyValidVec(0) := PopCount(io.subDeqRequest.get(0)) >= 1.U 305 subDeqPolicyValidVec(1) := PopCount(io.subDeqRequest.get(0)) >= 2.U 306 307 if (params.isAllComp || params.isAllSimp) { 308 subDeqPolicyEntryVec(0) := PriorityMux(io.subDeqRequest.get(0), entries) 309 subDeqPolicyEntryVec(1) := PriorityMux(Reverse(io.subDeqRequest.get(0)), entries.reverse) 310 subDeqPolicyCancelBypassVec(0) := PriorityMux(io.subDeqRequest.get(0), cancelBypassVec) 311 subDeqPolicyCancelBypassVec(1) := PriorityMux(Reverse(io.subDeqRequest.get(0)), cancelBypassVec.reverse) 312 313 io.deqEntry(0) := Mux(io.othersEntryOldestSel.get(0).valid, othersEntryOldest.get(0), subDeqPolicyEntryVec(1)) 314 io.deqEntry(1) := subDeqPolicyEntryVec(0) 315 io.cancelDeqVec(0) := Mux(io.othersEntryOldestSel.get(0).valid, othersEntryOldestCancel.get(0), subDeqPolicyCancelBypassVec(1)) 316 io.cancelDeqVec(1) := subDeqPolicyCancelBypassVec(0) 317 } 318 else { 319 subDeqPolicyEntryVec(0) := PriorityMux(Reverse(io.subDeqRequest.get(0)), entries.reverse) 320 subDeqPolicyEntryVec(1) := PriorityMux(io.subDeqRequest.get(0), entries) 321 subDeqPolicyCancelBypassVec(0) := PriorityMux(Reverse(io.subDeqRequest.get(0)), cancelBypassVec.reverse) 322 subDeqPolicyCancelBypassVec(1) := PriorityMux(io.subDeqRequest.get(0), cancelBypassVec) 323 324 io.deqEntry(0) := Mux(io.compEntryOldestSel.get(0).valid, 325 compEntryOldest.get(0), 326 Mux(io.simpEntryOldestSel.get(0).valid, simpEntryOldest.get(0), subDeqPolicyEntryVec(1))) 327 io.deqEntry(1) := subDeqPolicyEntryVec(0) 328 io.cancelDeqVec(0) := Mux(io.compEntryOldestSel.get(0).valid, 329 compEntryOldestCancel.get(0), 330 Mux(io.simpEntryOldestSel.get(0).valid, simpEntryOldestCancel.get(0), subDeqPolicyCancelBypassVec(1))) 331 io.cancelDeqVec(1) := subDeqPolicyCancelBypassVec(0) 332 } 333 334 when (subDeqPolicyValidVec(0)) { 335 assert(Mux1H(io.subDeqSelOH.get(0), entries).bits.status.robIdx === subDeqPolicyEntryVec(0).bits.status.robIdx, "subDeqSelOH(0) is not the same\n") 336 } 337 when (subDeqPolicyValidVec(1)) { 338 assert(Mux1H(io.subDeqSelOH.get(1), entries).bits.status.robIdx === subDeqPolicyEntryVec(1).bits.status.robIdx, "subDeqSelOH(1) is not the same\n") 339 } 340 } 341 else { 342 if (params.isAllComp || params.isAllSimp) { 343 io.othersEntryOldestSel.get.zipWithIndex.foreach { case (sel, i) => 344 io.deqEntry(i) := Mux(sel.valid, othersEntryOldest.get(i), enqEntryOldest(i)) 345 io.cancelDeqVec(i) := Mux(sel.valid, othersEntryOldestCancel.get(i), enqEntryOldestCancel(i)) 346 } 347 } 348 else { 349 io.compEntryOldestSel.get.zip(io.simpEntryOldestSel.get).zipWithIndex.foreach { case ((compSel, simpSel), i) => 350 io.deqEntry(i) := Mux(compSel.valid, 351 compEntryOldest.get(i), 352 Mux(simpSel.valid, simpEntryOldest.get(i), enqEntryOldest(i))) 353 io.cancelDeqVec(i) := Mux(compSel.valid, 354 compEntryOldestCancel.get(i), 355 Mux(simpSel.valid, simpEntryOldestCancel.get(i), enqEntryOldestCancel(i))) 356 } 357 } 358 } 359 360 if (params.hasIQWakeUp) { 361 cancelBypassVec.zip(srcWakeUpL1ExuOHVec.get).zip(srcTimerVec.get).zip(srcLoadDependencyVec).foreach{ case (((cancelBypass: Bool, l1ExuOH: Vec[Vec[Bool]]), srcTimer: Vec[UInt]), srcLoadDependency: Vec[Vec[UInt]]) => 362 val cancelByOg0 = l1ExuOH.zip(srcTimer).map { 363 case(exuOH, srcTimer) => 364 (exuOH.asUInt & io.og0Cancel.asUInt).orR && srcTimer === 1.U 365 }.reduce(_ | _) 366 val cancelByLd = srcLoadDependency.map(x => LoadShouldCancel(Some(x), io.ldCancel)).reduce(_ | _) 367 cancelBypass := cancelByLd 368 } 369 } else { 370 cancelBypassVec.zip(srcLoadDependencyVec).foreach { case (cancelBypass, srcLoadDependency) => 371 val cancelByLd = srcLoadDependency.map(x => LoadShouldCancel(Some(x), io.ldCancel)).reduce(_ | _) 372 cancelBypass := cancelByLd 373 } 374 } 375 376 io.valid := validVec.asUInt 377 io.canIssue := canIssueVec.asUInt 378 io.fuType := fuTypeVec 379 io.dataSources := dataSourceVec 380 io.srcWakeUpL1ExuOH.foreach(_ := srcWakeUpL1ExuOHVec.get.map(x => VecInit(x.map(_.asUInt)))) 381 io.srcTimer.foreach(_ := srcTimerVec.get) 382 io.loadDependency := loadDependencyVec 383 io.isFirstIssue.zipWithIndex.foreach{ case (isFirstIssue, deqIdx) => 384 isFirstIssue := io.deqSelOH(deqIdx).valid && Mux1H(io.deqSelOH(deqIdx).bits, isFirstIssueVec) 385 } 386 io.simpEntryEnqSelVec.foreach(_ := finalSimpTransSelVec.get.zip(enqEntryTransVec).map(x => x._1 & Fill(SimpEntryNum, x._2.valid))) 387 io.compEntryEnqSelVec.foreach(_ := finalCompTransSelVec.get.zip(compEnqVec.get).map(x => x._1 & Fill(CompEntryNum, x._2.valid))) 388 io.othersEntryEnqSelVec.foreach(_ := finalOthersTransSelVec.get.zip(enqEntryTransVec).map(x => x._1 & Fill(OthersEntryNum, x._2.valid))) 389 io.robIdx.foreach(_ := robIdxVec) 390 io.uopIdx.foreach(_ := uopIdxVec.get) 391 392 def EntriesConnect(in: CommonInBundle, out: CommonOutBundle, entryIdx: Int) = { 393 in.flush := io.flush 394 in.wakeUpFromWB := io.wakeUpFromWB 395 in.wakeUpFromIQ := io.wakeUpFromIQ 396 in.og0Cancel := io.og0Cancel 397 in.og1Cancel := io.og1Cancel 398 in.ldCancel := io.ldCancel 399 in.deqSel := deqSelVec(entryIdx) 400 in.deqPortIdxWrite := deqPortIdxWriteVec(entryIdx) 401 in.issueResp := issueRespVec(entryIdx) 402 if (params.isVecMemIQ) { 403 in.fromLsq.get.sqDeqPtr := io.vecMemIn.get.sqDeqPtr 404 in.fromLsq.get.lqDeqPtr := io.vecMemIn.get.lqDeqPtr 405 } 406 validVec(entryIdx) := out.valid 407 canIssueVec(entryIdx) := out.canIssue 408 fuTypeVec(entryIdx) := out.fuType 409 robIdxVec(entryIdx) := out.robIdx 410 dataSourceVec(entryIdx) := out.dataSource 411 isFirstIssueVec(entryIdx) := out.isFirstIssue 412 entries(entryIdx) := out.entry 413 deqPortIdxReadVec(entryIdx) := out.deqPortIdxRead 414 issueTimerVec(entryIdx) := out.issueTimerRead 415 srcLoadDependencyVec(entryIdx) := out.srcLoadDependency 416 loadDependencyVec(entryIdx) := out.entry.bits.status.mergedLoadDependency 417 if (params.hasIQWakeUp) { 418 srcWakeUpL1ExuOHVec.get(entryIdx) := out.srcWakeUpL1ExuOH.get 419 srcTimerVec.get(entryIdx) := out.srcTimer.get 420 } 421 if (params.isVecMemIQ) { 422 uopIdxVec.get(entryIdx) := out.uopIdx.get 423 } 424 entryInValidVec(entryIdx) := out.entryInValid 425 entryOutDeqValidVec(entryIdx) := out.entryOutDeqValid 426 entryOutTransValidVec(entryIdx) := out.entryOutTransValid 427 perfWakeupByWBVec(entryIdx) := out.perfWakeupByWB 428 if (params.hasIQWakeUp) { 429 perfLdCancelVec.get(entryIdx) := out.perfLdCancel.get 430 perfOg0CancelVec.get(entryIdx) := out.perfOg0Cancel.get 431 perfWakeupByIQVec.get(entryIdx) := out.perfWakeupByIQ.get 432 } 433 } 434 435 // entries perf counter 436 // enq 437 for (i <- 0 until params.numEnq) { 438 XSPerfAccumulate(s"enqEntry_${i}_in_cnt", entryInValidVec(i)) 439 XSPerfAccumulate(s"enqEntry_${i}_out_deq_cnt", entryOutDeqValidVec(i)) 440 XSPerfAccumulate(s"enqEntry_${i}_out_trans_cnt", entryOutTransValidVec(i)) 441 } 442 // simple 443 for (i <- 0 until params.numSimp) { 444 XSPerfAccumulate(s"simpEntry_${i}_in_cnt", entryInValidVec(i + params.numEnq)) 445 XSPerfAccumulate(s"simpEntry_${i}_out_deq_cnt", entryOutDeqValidVec(i + params.numEnq)) 446 XSPerfAccumulate(s"simpEntry_${i}_out_trans_cnt", entryOutTransValidVec(i + params.numEnq)) 447 } 448 // complex 449 for (i <- 0 until params.numComp) { 450 XSPerfAccumulate(s"compEntry_${i}_in_cnt", entryInValidVec(i + params.numEnq + params.numSimp)) 451 XSPerfAccumulate(s"compEntry_${i}_out_deq_cnt", entryOutDeqValidVec(i + params.numEnq + params.numSimp)) 452 XSPerfAccumulate(s"compEntry_${i}_out_trans_cnt", entryOutTransValidVec(i + params.numEnq + params.numSimp)) 453 } 454 // total 455 XSPerfAccumulate(s"enqEntry_all_in_cnt", PopCount(entryInValidVec.take(params.numEnq))) 456 XSPerfAccumulate(s"enqEntry_all_out_deq_cnt", PopCount(entryOutDeqValidVec.take(params.numEnq))) 457 XSPerfAccumulate(s"enqEntry_all_out_trans_cnt", PopCount(entryOutTransValidVec.take(params.numEnq))) 458 for (srcIdx <- 0 until params.numRegSrc) { 459 XSPerfAccumulate(s"enqEntry_all_wakeup_wb_src${srcIdx}_cnt", PopCount(perfWakeupByWBVec.take(params.numEnq).map(_(srcIdx)))) 460 if (params.hasIQWakeUp) { 461 XSPerfAccumulate(s"enqEntry_all_ldCancel_src${srcIdx}_cnt", PopCount(perfLdCancelVec.get.take(params.numEnq).map(_(srcIdx)))) 462 XSPerfAccumulate(s"enqEntry_all_og0Cancel_src${srcIdx}_cnt", PopCount(perfOg0CancelVec.get.take(params.numEnq).map(_(srcIdx)))) 463 for (iqIdx <- 0 until params.numWakeupFromIQ) { 464 XSPerfAccumulate(s"enqEntry_all_wakeup_iq_from_exu${params.wakeUpSourceExuIdx(iqIdx)}_src${srcIdx}_cnt", PopCount(perfWakeupByIQVec.get.take(params.numEnq).map(_(srcIdx)(iqIdx)))) 465 } 466 } 467 } 468 469 XSPerfAccumulate(s"othersEntry_all_in_cnt", PopCount(entryInValidVec.drop(params.numEnq))) 470 XSPerfAccumulate(s"othersEntry_all_out_deq_cnt", PopCount(entryOutDeqValidVec.drop(params.numEnq))) 471 XSPerfAccumulate(s"othersEntry_all_out_trans_cnt", PopCount(entryOutTransValidVec.drop(params.numEnq))) 472 for (srcIdx <- 0 until params.numRegSrc) { 473 XSPerfAccumulate(s"othersEntry_all_wakeup_wb_src${srcIdx}_cnt", PopCount(perfWakeupByWBVec.drop(params.numEnq).map(_(srcIdx)))) 474 if (params.hasIQWakeUp) { 475 XSPerfAccumulate(s"othersEntry_all_ldCancel_src${srcIdx}_cnt", PopCount(perfLdCancelVec.get.drop(params.numEnq).map(_(srcIdx)))) 476 XSPerfAccumulate(s"othersEntry_all_og0Cancel_src${srcIdx}_cnt", PopCount(perfOg0CancelVec.get.drop(params.numEnq).map(_(srcIdx)))) 477 for (iqIdx <- 0 until params.numWakeupFromIQ) { 478 XSPerfAccumulate(s"othersEntry_all_wakeup_iq_from_exu${params.wakeUpSourceExuIdx(iqIdx)}_src${srcIdx}_cnt", PopCount(perfWakeupByIQVec.get.drop(params.numEnq).map(_(srcIdx)(iqIdx)))) 479 } 480 } 481 } 482 483 for (t <- FuType.functionNameMap.keys) { 484 val fuName = FuType.functionNameMap(t) 485 if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _) && params.getFuCfgs.size > 1) { 486 for (srcIdx <- 0 until params.numRegSrc) { 487 XSPerfAccumulate(s"allEntry_futype_${fuName}_wakeup_wb_src${srcIdx}_cnt", PopCount(perfWakeupByWBVec.zip(fuTypeVec).map{ case(x, fu) => x(srcIdx) && fu(t.id) })) 488 if (params.hasIQWakeUp) { 489 XSPerfAccumulate(s"allEntry_futype_${fuName}_ldCancel_src${srcIdx}_cnt", PopCount(perfLdCancelVec.get.zip(fuTypeVec).map{ case(x, fu) => x(srcIdx) && fu(t.id) })) 490 XSPerfAccumulate(s"allEntry_futype_${fuName}_og0Cancel_src${srcIdx}_cnt", PopCount(perfOg0CancelVec.get.zip(fuTypeVec).map{ case(x, fu) => x(srcIdx) && fu(t.id) })) 491 for (iqIdx <- 0 until params.numWakeupFromIQ) { 492 XSPerfAccumulate(s"allEntry_futype_${fuName}_wakeup_iq_from_exu${params.wakeUpSourceExuIdx(iqIdx)}_src${srcIdx}_cnt", PopCount(perfWakeupByIQVec.get.zip(fuTypeVec).map{ case(x, fu) => x(srcIdx)(iqIdx) && fu(t.id) })) 493 } 494 } 495 } 496 } 497 } 498} 499 500class EntriesIO(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 501 val flush = Flipped(ValidIO(new Redirect)) 502 //enq 503 val enq = Vec(params.numEnq, Flipped(ValidIO(new EntryBundle))) 504 val og0Resp = Vec(params.numDeq, Flipped(ValidIO(new EntryDeqRespBundle))) 505 val og1Resp = Vec(params.numDeq, Flipped(ValidIO(new EntryDeqRespBundle))) 506 val og2Resp = OptionWrapper(params.inVfSchd, Vec(params.numDeq, Flipped(ValidIO(new EntryDeqRespBundle)))) 507 //deq sel 508 val deqReady = Vec(params.numDeq, Input(Bool())) 509 val deqSelOH = Vec(params.numDeq, Flipped(ValidIO(UInt(params.numEntries.W)))) 510 val enqEntryOldestSel = Vec(params.numDeq, Flipped(ValidIO(UInt(params.numEnq.W)))) 511 val simpEntryOldestSel = OptionWrapper(params.hasCompAndSimp, Vec(params.numDeq, Flipped(ValidIO(UInt(params.numSimp.W))))) 512 val compEntryOldestSel = OptionWrapper(params.hasCompAndSimp, Vec(params.numDeq, Flipped(ValidIO(UInt(params.numComp.W))))) 513 val othersEntryOldestSel= OptionWrapper(params.isAllComp || params.isAllSimp, Vec(params.numDeq, Flipped(ValidIO(UInt((params.numEntries - params.numEnq).W))))) 514 val subDeqRequest = OptionWrapper(params.deqFuSame, Vec(params.numDeq, Input(UInt(params.numEntries.W)))) 515 val subDeqSelOH = OptionWrapper(params.deqFuSame, Vec(params.numDeq, Input(UInt(params.numEntries.W)))) 516 // wakeup 517 val wakeUpFromWB: MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = Flipped(params.genWBWakeUpSinkValidBundle) 518 val wakeUpFromIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(params.genIQWakeUpSinkValidBundle) 519 val og0Cancel = Input(ExuOH(backendParams.numExu)) 520 val og1Cancel = Input(ExuOH(backendParams.numExu)) 521 val ldCancel = Vec(backendParams.LdExuCnt, Flipped(new LoadCancelIO)) 522 //entries status 523 val valid = Output(UInt(params.numEntries.W)) 524 val canIssue = Output(UInt(params.numEntries.W)) 525 val fuType = Vec(params.numEntries, Output(FuType())) 526 val dataSources = Vec(params.numEntries, Vec(params.numRegSrc, Output(DataSource()))) 527 val loadDependency = Vec(params.numEntries, Vec(LoadPipelineWidth, UInt(3.W))) 528 val srcWakeUpL1ExuOH = OptionWrapper(params.hasIQWakeUp, Vec(params.numEntries, Vec(params.numRegSrc, Output(ExuOH())))) 529 val srcTimer = OptionWrapper(params.hasIQWakeUp, Vec(params.numEntries, Vec(params.numRegSrc, Output(UInt(3.W))))) 530 //deq status 531 val isFirstIssue = Vec(params.numDeq, Output(Bool())) 532 val deqEntry = Vec(params.numDeq, ValidIO(new EntryBundle)) 533 val cancelDeqVec = Vec(params.numDeq, Output(Bool())) 534 535 // load/hybird only 536 val fromLoad = OptionWrapper(params.isLdAddrIQ || params.isHyAddrIQ, new Bundle { 537 val finalIssueResp = Vec(params.numDeq, Flipped(ValidIO(new EntryDeqRespBundle))) 538 val memAddrIssueResp = Vec(params.numDeq, Flipped(ValidIO(new EntryDeqRespBundle))) 539 }) 540 // mem only 541 val fromMem = OptionWrapper(params.isMemAddrIQ, new Bundle { 542 val slowResp = Vec(params.numDeq, Flipped(ValidIO(new EntryDeqRespBundle))) 543 val fastResp = Vec(params.numDeq, Flipped(ValidIO(new EntryDeqRespBundle))) 544 }) 545 // vec mem only 546 val vecMemIn = OptionWrapper(params.isVecMemIQ, new Bundle { 547 val sqDeqPtr = Input(new SqPtr) 548 val lqDeqPtr = Input(new LqPtr) 549 }) 550 val robIdx = OptionWrapper(params.isVecMemIQ, Output(Vec(params.numEntries, new RobPtr))) 551 val uopIdx = OptionWrapper(params.isVecMemIQ, Output(Vec(params.numEntries, UopIdx()))) 552 553 // trans 554 val simpEntryDeqSelVec = OptionWrapper(params.hasCompAndSimp, Vec(params.numEnq, Input(UInt(params.numSimp.W)))) 555 val simpEntryEnqSelVec = OptionWrapper(params.hasCompAndSimp, Vec(params.numEnq, Output(UInt(params.numSimp.W)))) 556 val compEntryEnqSelVec = OptionWrapper(params.hasCompAndSimp, Vec(params.numEnq, Output(UInt(params.numComp.W)))) 557 val othersEntryEnqSelVec = OptionWrapper(params.isAllComp || params.isAllSimp, Vec(params.numEnq, Output(UInt((params.numEntries - params.numEnq).W)))) 558 559 def wakeup = wakeUpFromWB ++ wakeUpFromIQ 560} 561