1package xiangshan.backend.issue 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import utility.HasCircularQueuePtrHelper 7import utils._ 8import xiangshan._ 9import xiangshan.backend.Bundles._ 10import xiangshan.backend.datapath.DataConfig.VAddrData 11import xiangshan.backend.datapath.DataSource 12import xiangshan.backend.fu.FuType 13import xiangshan.backend.fu.vector.Utils.NOnes 14import xiangshan.backend.rob.RobPtr 15import xiangshan.mem.{LqPtr, MemWaitUpdateReq, SqPtr} 16import xiangshan.backend.issue.EntryBundles._ 17 18class Entries(implicit p: Parameters, params: IssueBlockParams) extends XSModule { 19 override def desiredName: String = params.getEntryName 20 21 require(params.numEnq <= 2, "number of enq should be no more than 2") 22 23 private val EnqEntryNum = params.numEnq 24 private val OthersEntryNum = params.numEntries - params.numEnq 25 private val SimpEntryNum = params.numSimp 26 private val CompEntryNum = params.numComp 27 val io = IO(new EntriesIO) 28 29 // only memAddrIQ use it 30 val memEtyResps: MixedVec[ValidIO[EntryDeqRespBundle]] = { 31 if (params.isLdAddrIQ && !params.isStAddrIQ) //LDU 32 MixedVecInit(io.og0Resp ++ io.og1Resp ++ io.fromLoad.get.finalIssueResp ++ io.fromLoad.get.memAddrIssueResp) 33 else if (params.isLdAddrIQ && params.isStAddrIQ || params.isHyAddrIQ) //HYU 34 MixedVecInit(io.og0Resp ++ io.og1Resp ++ io.fromLoad.get.finalIssueResp ++ io.fromLoad.get.memAddrIssueResp ++ io.fromMem.get.fastResp ++ io.fromMem.get.slowResp) 35 else if (params.isMemAddrIQ) //STU, VLDU, VSTU 36 MixedVecInit(io.og0Resp ++ io.og1Resp ++ io.fromMem.get.slowResp) 37 else MixedVecInit(Seq()) 38 } 39 40 val resps: Vec[Vec[ValidIO[EntryDeqRespBundle]]] = { 41 if (params.inVfSchd) 42 VecInit(io.og0Resp, io.og1Resp, io.og2Resp.get, 0.U.asTypeOf(io.og0Resp)) 43 else 44 VecInit(io.og0Resp, io.og1Resp, 0.U.asTypeOf(io.og0Resp), 0.U.asTypeOf(io.og0Resp)) 45 } 46 47 //Module 48 val enqEntries = Seq.fill(EnqEntryNum)(Module(EnqEntry(isComp = true)(p, params))) 49 val othersEntriesSimp = Seq.fill(SimpEntryNum)(Module(OthersEntry(isComp = false)(p, params))) 50 val othersEntriesComp = Seq.fill(CompEntryNum)(Module(OthersEntry(isComp = true)(p, params))) 51 val othersEntries = othersEntriesSimp ++ othersEntriesComp 52 val othersTransPolicy = OptionWrapper(params.isAllComp || params.isAllSimp, Module(new EnqPolicy)) 53 val simpTransPolicy = OptionWrapper(params.hasCompAndSimp, Module(new EnqPolicy)) 54 val compTransPolicy = OptionWrapper(params.hasCompAndSimp, Module(new EnqPolicy)) 55 56 //Wire 57 //entries status 58 val entries = Wire(Vec(params.numEntries, ValidIO(new EntryBundle))) 59 val robIdxVec = Wire(Vec(params.numEntries, new RobPtr)) 60 val validVec = Wire(Vec(params.numEntries, Bool())) 61 val canIssueVec = Wire(Vec(params.numEntries, Bool())) 62 val fuTypeVec = Wire(Vec(params.numEntries, FuType())) 63 val isFirstIssueVec = Wire(Vec(params.numEntries, Bool())) 64 val issueTimerVec = Wire(Vec(params.numEntries, UInt(2.W))) 65 val uopIdxVec = OptionWrapper(params.isVecMemIQ, Wire(Vec(params.numEntries, UopIdx()))) 66 //src status 67 val dataSourceVec = Wire(Vec(params.numEntries, Vec(params.numRegSrc, DataSource()))) 68 val loadDependencyVec = Wire(Vec(params.numEntries, Vec(LoadPipelineWidth, UInt(3.W)))) 69 val srcLoadDependencyVec= Wire(Vec(params.numEntries, Vec(params.numRegSrc, Vec(LoadPipelineWidth, UInt(3.W))))) 70 val srcTimerVec = OptionWrapper(params.hasIQWakeUp, Wire(Vec(params.numEntries, Vec(params.numRegSrc, UInt(3.W))))) 71 val srcWakeUpL1ExuOHVec = OptionWrapper(params.hasIQWakeUp, Wire(Vec(params.numEntries, Vec(params.numRegSrc, ExuVec())))) 72 //deq sel 73 val deqSelVec = Wire(Vec(params.numEntries, Bool())) 74 val issueRespVec = Wire(Vec(params.numEntries, ValidIO(new EntryDeqRespBundle))) 75 val deqPortIdxWriteVec = Wire(Vec(params.numEntries, UInt(1.W))) 76 val deqPortIdxReadVec = Wire(Vec(params.numEntries, UInt(1.W))) 77 //trans sel 78 val othersEntryEnqReadyVec = Wire(Vec(OthersEntryNum, Bool())) 79 val othersEntryEnqVec = Wire(Vec(OthersEntryNum, Valid(new EntryBundle))) 80 val enqEntryTransVec = Wire(Vec(EnqEntryNum, Valid(new EntryBundle))) 81 val simpEntryTransVec = OptionWrapper(params.hasCompAndSimp, Wire(Vec(SimpEntryNum, Valid(new EntryBundle)))) 82 val compEnqVec = OptionWrapper(params.hasCompAndSimp, Wire(Vec(EnqEntryNum, Valid(new EntryBundle)))) 83 84 val enqCanTrans2Simp = OptionWrapper(params.hasCompAndSimp, Wire(Bool())) 85 val enqCanTrans2Comp = OptionWrapper(params.hasCompAndSimp, Wire(Bool())) 86 val simpCanTrans2Comp = OptionWrapper(params.hasCompAndSimp, Wire(Vec(EnqEntryNum, Bool()))) 87 val simpTransSelVec = OptionWrapper(params.hasCompAndSimp, Wire(Vec(EnqEntryNum, Valid(UInt(SimpEntryNum.W))))) 88 val compTransSelVec = OptionWrapper(params.hasCompAndSimp, Wire(Vec(EnqEntryNum, Valid(UInt(CompEntryNum.W))))) 89 val finalSimpTransSelVec = OptionWrapper(params.hasCompAndSimp, Wire(Vec(EnqEntryNum, UInt(SimpEntryNum.W)))) 90 val finalCompTransSelVec = OptionWrapper(params.hasCompAndSimp, Wire(Vec(EnqEntryNum, UInt(CompEntryNum.W)))) 91 92 val enqCanTrans2Others = OptionWrapper(params.isAllComp || params.isAllSimp, Wire(Bool())) 93 val othersTransSelVec = OptionWrapper(params.isAllComp || params.isAllSimp, Wire(Vec(EnqEntryNum, Valid(UInt(OthersEntryNum.W))))) 94 val finalOthersTransSelVec = OptionWrapper(params.isAllComp || params.isAllSimp, Wire(Vec(EnqEntryNum, UInt(OthersEntryNum.W)))) 95 96 val simpEntryEnqReadyVec = othersEntryEnqReadyVec.take(SimpEntryNum) 97 val compEntryEnqReadyVec = othersEntryEnqReadyVec.takeRight(CompEntryNum) 98 val simpEntryEnqVec = othersEntryEnqVec.take(SimpEntryNum) 99 val compEntryEnqVec = othersEntryEnqVec.takeRight(CompEntryNum) 100 //debug 101 val cancelVec = OptionWrapper(params.hasIQWakeUp, Wire(Vec(params.numEntries, Bool()))) 102 val entryInValidVec = Wire(Vec(params.numEntries, Bool())) 103 val entryOutDeqValidVec = Wire(Vec(params.numEntries, Bool())) 104 val entryOutTransValidVec = Wire(Vec(params.numEntries, Bool())) 105 //cancel bypass 106 val cancelBypassVec = Wire(Vec(params.numEntries, Bool())) 107 108 109 //enqEntries 110 enqEntries.zipWithIndex.foreach { case (enqEntry, entryIdx) => 111 enqEntry.io.commonIn.enq := io.enq(entryIdx) 112 enqEntry.io.commonIn.transSel := (if (params.isAllComp || params.isAllSimp) enqCanTrans2Others.get && othersTransSelVec.get(entryIdx).valid 113 else enqCanTrans2Simp.get && simpTransSelVec.get(entryIdx).valid || enqCanTrans2Comp.get && compTransSelVec.get(entryIdx).valid) 114 EntriesConnect(enqEntry.io.commonIn, enqEntry.io.commonOut, entryIdx) 115 enqEntry.io.enqDelayWakeUpFromWB := RegEnable(io.wakeUpFromWB, io.enq(entryIdx).valid) 116 enqEntry.io.enqDelayWakeUpFromIQ := RegEnable(io.wakeUpFromIQ, io.enq(entryIdx).valid) 117 enqEntry.io.enqDelayOg0Cancel := RegNext(io.og0Cancel.asUInt) 118 enqEntry.io.enqDelayLdCancel := RegNext(io.ldCancel) 119 enqEntryTransVec(entryIdx) := enqEntry.io.commonOut.transEntry 120 } 121 //othersEntries 122 othersEntries.zipWithIndex.foreach { case (othersEntry, entryIdx) => 123 othersEntry.io.commonIn.enq := othersEntryEnqVec(entryIdx) 124 othersEntry.io.commonIn.transSel := (if (params.hasCompAndSimp && (entryIdx < SimpEntryNum)) 125 io.simpEntryDeqSelVec.get.zip(simpCanTrans2Comp.get).map(x => x._1(entryIdx) && x._2).reduce(_ | _) 126 else false.B) 127 EntriesConnect(othersEntry.io.commonIn, othersEntry.io.commonOut, entryIdx + EnqEntryNum) 128 othersEntryEnqReadyVec(entryIdx) := othersEntry.io.commonOut.enqReady 129 if (params.hasCompAndSimp && (entryIdx < SimpEntryNum)) { 130 simpEntryTransVec.get(entryIdx) := othersEntry.io.commonOut.transEntry 131 } 132 } 133 134 135 deqSelVec.zip(deqPortIdxWriteVec).zipWithIndex.foreach { case ((deqSel, deqPortIdxWrite), i) => 136 val deqVec = io.deqSelOH.zip(io.deqReady).map(x => x._1.valid && x._1.bits(i) && x._2) 137 deqPortIdxWrite := OHToUInt(deqVec) 138 deqSel := deqVec.reduce(_ | _) 139 } 140 141 142 if (params.isAllComp || params.isAllSimp) { 143 //transPolicy 144 othersTransPolicy.get.io.canEnq := othersEntryEnqReadyVec.asUInt 145 146 // we only allow all or none of the enq entries transfering to others entries. 147 enqCanTrans2Others.get := PopCount(validVec.take(EnqEntryNum)) <= PopCount(othersEntryEnqReadyVec) 148 // othersTransSelVec(i) is the target others entry for enq entry [i]. 149 // note that dispatch does not guarantee the validity of enq entries with low index. 150 // that means in some cases enq entry [0] is invalid while enq entry [1] is valid. 151 // in this case, enq entry [1] should use result [0] of TransPolicy. 152 othersTransSelVec.get(0).valid := othersTransPolicy.get.io.enqSelOHVec(0).valid && validVec(0) 153 othersTransSelVec.get(0).bits := othersTransPolicy.get.io.enqSelOHVec(0).bits 154 if (params.numEnq == 2) { 155 othersTransSelVec.get(1).valid := Mux(!validVec(0), othersTransPolicy.get.io.enqSelOHVec(0).valid, othersTransPolicy.get.io.enqSelOHVec(1).valid) 156 othersTransSelVec.get(1).bits := Mux(!validVec(0), othersTransPolicy.get.io.enqSelOHVec(0).bits, othersTransPolicy.get.io.enqSelOHVec(1).bits) 157 } 158 159 finalOthersTransSelVec.get.zip(othersTransSelVec.get).zipWithIndex.foreach { case ((finalOH, selOH), enqIdx) => 160 finalOH := Fill(OthersEntryNum, enqCanTrans2Others.get && selOH.valid) & selOH.bits 161 } 162 163 //othersEntryEnq 164 othersEntryEnqVec.zipWithIndex.foreach { case (othersEntryEnq, othersIdx) => 165 val othersEnqOH = finalOthersTransSelVec.get.map(_(othersIdx)) 166 if (othersEnqOH.size == 1) 167 othersEntryEnq := Mux(othersEnqOH.head, enqEntryTransVec.head, 0.U.asTypeOf(enqEntryTransVec.head)) 168 else 169 othersEntryEnq := Mux1H(othersEnqOH, enqEntryTransVec) 170 } 171 } 172 else { 173 //transPolicy 174 simpTransPolicy.get.io.canEnq := VecInit(simpEntryEnqReadyVec).asUInt 175 compTransPolicy.get.io.canEnq := VecInit(validVec.takeRight(CompEntryNum).map(!_)).asUInt 176 177 // we only allow all or none of the enq entries transfering to comp/simp entries. 178 // when all of simp entries are empty and comp entries are enough, transfer to comp entries. 179 // otherwise, transfer to simp entries. 180 enqCanTrans2Comp.get := PopCount(validVec.take(EnqEntryNum)) <= PopCount(validVec.takeRight(CompEntryNum).map(!_)) && !validVec.drop(EnqEntryNum).take(SimpEntryNum).reduce(_ || _) 181 enqCanTrans2Simp.get := !enqCanTrans2Comp.get && PopCount(validVec.take(EnqEntryNum)) <= PopCount(simpEntryEnqReadyVec) 182 simpCanTrans2Comp.get.zipWithIndex.foreach { case (canTrans, idx) => 183 canTrans := !enqCanTrans2Comp.get && PopCount(validVec.takeRight(CompEntryNum).map(!_)) >= (idx + 1).U 184 } 185 186 // simp/compTransSelVec(i) is the target simp/comp entry for enq entry [i]. 187 // note that dispatch does not guarantee the validity of enq entries with low index. 188 // that means in some cases enq entry [0] is invalid while enq entry [1] is valid. 189 // in this case, enq entry [1] should use result [0] of TransPolicy. 190 simpTransSelVec.get(0).valid := simpTransPolicy.get.io.enqSelOHVec(0).valid && validVec(0) 191 simpTransSelVec.get(0).bits := simpTransPolicy.get.io.enqSelOHVec(0).bits 192 compTransSelVec.get(0).valid := compTransPolicy.get.io.enqSelOHVec(0).valid && validVec(0) 193 compTransSelVec.get(0).bits := compTransPolicy.get.io.enqSelOHVec(0).bits 194 if (params.numEnq == 2) { 195 simpTransSelVec.get(1).valid := Mux(!validVec(0), simpTransPolicy.get.io.enqSelOHVec(0).valid, simpTransPolicy.get.io.enqSelOHVec(1).valid) 196 simpTransSelVec.get(1).bits := Mux(!validVec(0), simpTransPolicy.get.io.enqSelOHVec(0).bits, simpTransPolicy.get.io.enqSelOHVec(1).bits) 197 compTransSelVec.get(1).valid := Mux(!validVec(0), compTransPolicy.get.io.enqSelOHVec(0).valid, compTransPolicy.get.io.enqSelOHVec(1).valid) 198 compTransSelVec.get(1).bits := Mux(!validVec(0), compTransPolicy.get.io.enqSelOHVec(0).bits, compTransPolicy.get.io.enqSelOHVec(1).bits) 199 } 200 201 finalSimpTransSelVec.get.zip(simpTransSelVec.get).zipWithIndex.foreach { case ((finalOH, selOH), enqIdx) => 202 finalOH := Fill(SimpEntryNum, enqCanTrans2Simp.get && selOH.valid) & selOH.bits 203 } 204 finalCompTransSelVec.get.zip(compTransSelVec.get).zip(compTransPolicy.get.io.enqSelOHVec).zipWithIndex.foreach { 205 case (((finalOH, selOH), origSelOH), enqIdx) => 206 finalOH := Mux(enqCanTrans2Comp.get, Fill(CompEntryNum, selOH.valid) & selOH.bits, Fill(CompEntryNum, origSelOH.valid) & origSelOH.bits) 207 } 208 209 //othersEntryEnq 210 simpEntryEnqVec.zipWithIndex.foreach { case (simpEntryEnq, simpIdx) => 211 val simpEnqOH = finalSimpTransSelVec.get.map(_(simpIdx)) 212 // shit Mux1H directly returns in(0) if the seq has only 1 elements 213 if (simpEnqOH.size == 1) 214 simpEntryEnq := Mux(simpEnqOH.head, enqEntryTransVec.head, 0.U.asTypeOf(enqEntryTransVec.head)) 215 else 216 simpEntryEnq := Mux1H(simpEnqOH, enqEntryTransVec) 217 } 218 219 compEnqVec.get.zip(enqEntryTransVec).zip(io.simpEntryDeqSelVec.get).foreach { case ((compEnq, enqEntry), deqSel) => 220 compEnq := Mux(enqCanTrans2Comp.get, enqEntry, Mux1H(deqSel, simpEntryTransVec.get)) 221 } 222 compEntryEnqVec.zipWithIndex.foreach { case (compEntryEnq, compIdx) => 223 val compEnqOH = finalCompTransSelVec.get.map(_(compIdx)) 224 // shit Mux1H directly returns in(0) if the seq has only 1 elements 225 if (compEnqOH.size == 1) 226 compEntryEnq := Mux(compEnqOH.head, compEnqVec.get.head, 0.U.asTypeOf(compEnqVec.get.head)) 227 else 228 compEntryEnq := Mux1H(compEnqOH, compEnqVec.get) 229 } 230 231 assert(PopCount(simpEntryEnqVec.map(_.valid)) <= params.numEnq.U, "the number of simpEntryEnq is more than numEnq\n") 232 assert(PopCount(compEntryEnqVec.map(_.valid)) <= params.numEnq.U, "the number of compEntryEnq is more than numEnq\n") 233 } 234 235 if(backendParams.debugEn) { 236 dontTouch(othersEntryEnqVec) 237 } 238 239 //issueRespVec 240 if (params.isVecMemIQ) { 241 // vector memory IQ 242 issueRespVec.zip(robIdxVec).zip(uopIdxVec.get).foreach { case ((issueResp, robIdx), uopIdx) => 243 val hitRespsVec = VecInit(resps.flatten.map(x => 244 x.valid && x.bits.robIdx === robIdx && x.bits.uopIdx.get === uopIdx 245 )) 246 issueResp.valid := hitRespsVec.reduce(_ | _) 247 issueResp.bits := Mux1H(hitRespsVec, resps.flatten.map(_.bits)) 248 } 249 } else if (params.isMemAddrIQ) { 250 // scalar memory IQ 251 issueRespVec.zip(robIdxVec).foreach { case (issueResp, robIdx) => 252 val hitRespsVec = VecInit(memEtyResps.map(x => x.valid && (x.bits.robIdx === robIdx)).toSeq) 253 issueResp.valid := hitRespsVec.reduce(_ | _) 254 issueResp.bits := Mux1H(hitRespsVec, memEtyResps.map(_.bits).toSeq) 255 } 256 } 257 else { 258 issueRespVec.zip(issueTimerVec).zip(deqPortIdxReadVec).foreach { case ((issueResp, issueTimer), deqPortIdx) => 259 val Resp = resps(issueTimer)(deqPortIdx) 260 issueResp := Resp 261 } 262 } 263 264 //deq 265 val enqEntryOldest = Wire(Vec(params.numDeq, ValidIO(new EntryBundle))) 266 val simpEntryOldest = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numDeq, ValidIO(new EntryBundle)))) 267 val compEntryOldest = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numDeq, ValidIO(new EntryBundle)))) 268 val othersEntryOldest = OptionWrapper(params.isAllComp || params.isAllSimp, Wire(Vec(params.numDeq, ValidIO(new EntryBundle)))) 269 val enqEntryOldestCancel = Wire(Vec(params.numDeq, Bool())) 270 val simpEntryOldestCancel = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numDeq, Bool()))) 271 val compEntryOldestCancel = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numDeq, Bool()))) 272 val othersEntryOldestCancel = OptionWrapper(params.isAllComp || params.isAllSimp, Wire(Vec(params.numDeq, Bool()))) 273 274 io.enqEntryOldestSel.zipWithIndex.map { case (sel, deqIdx) => 275 enqEntryOldest(deqIdx) := Mux1H(sel.bits, entries.take(EnqEntryNum)) 276 enqEntryOldestCancel(deqIdx) := Mux1H(sel.bits, cancelBypassVec.take(EnqEntryNum)) 277 } 278 279 if (params.isAllComp || params.isAllSimp) { 280 io.othersEntryOldestSel.get.zipWithIndex.map { case (sel, deqIdx) => 281 othersEntryOldest.get(deqIdx) := Mux1H(sel.bits, entries.drop(EnqEntryNum)) 282 othersEntryOldestCancel.get(deqIdx) := Mux1H(sel.bits, cancelBypassVec.drop(EnqEntryNum)) 283 } 284 } 285 else { 286 io.simpEntryOldestSel.get.zipWithIndex.map { case (sel, deqIdx) => 287 simpEntryOldest.get(deqIdx) := Mux1H(sel.bits, entries.drop(EnqEntryNum).take(SimpEntryNum)) 288 simpEntryOldestCancel.get(deqIdx) := Mux1H(sel.bits, cancelBypassVec.drop(EnqEntryNum).take(SimpEntryNum)) 289 } 290 io.compEntryOldestSel.get.zipWithIndex.map { case (sel, deqIdx) => 291 compEntryOldest.get(deqIdx) := Mux1H(sel.bits, entries.drop(EnqEntryNum).takeRight(CompEntryNum)) 292 compEntryOldestCancel.get(deqIdx) := Mux1H(sel.bits, cancelBypassVec.drop(EnqEntryNum).takeRight(CompEntryNum)) 293 } 294 } 295 296 if (params.deqFuSame) { 297 val subDeqPolicyEntryVec = Wire(Vec(params.numDeq, ValidIO(new EntryBundle))) 298 val subDeqPolicyValidVec = Wire(Vec(params.numDeq, Bool())) 299 val subDeqPolicyCancelBypassVec = Wire(Vec(params.numDeq, Bool())) 300 301 subDeqPolicyValidVec(0) := PopCount(io.subDeqRequest.get(0)) >= 1.U 302 subDeqPolicyValidVec(1) := PopCount(io.subDeqRequest.get(0)) >= 2.U 303 304 if (params.isAllComp || params.isAllSimp) { 305 subDeqPolicyEntryVec(0) := PriorityMux(io.subDeqRequest.get(0), entries) 306 subDeqPolicyEntryVec(1) := PriorityMux(Reverse(io.subDeqRequest.get(0)), entries.reverse) 307 subDeqPolicyCancelBypassVec(0) := PriorityMux(io.subDeqRequest.get(0), cancelBypassVec) 308 subDeqPolicyCancelBypassVec(1) := PriorityMux(Reverse(io.subDeqRequest.get(0)), cancelBypassVec.reverse) 309 310 io.deqEntry(0) := Mux(io.othersEntryOldestSel.get(0).valid, othersEntryOldest.get(0), subDeqPolicyEntryVec(1)) 311 io.deqEntry(1) := subDeqPolicyEntryVec(0) 312 io.cancelDeqVec(0) := Mux(io.othersEntryOldestSel.get(0).valid, othersEntryOldestCancel.get(0), subDeqPolicyCancelBypassVec(1)) 313 io.cancelDeqVec(1) := subDeqPolicyCancelBypassVec(0) 314 } 315 else { 316 subDeqPolicyEntryVec(0) := PriorityMux(Reverse(io.subDeqRequest.get(0)), entries.reverse) 317 subDeqPolicyEntryVec(1) := PriorityMux(io.subDeqRequest.get(0), entries) 318 subDeqPolicyCancelBypassVec(0) := PriorityMux(Reverse(io.subDeqRequest.get(0)), cancelBypassVec.reverse) 319 subDeqPolicyCancelBypassVec(1) := PriorityMux(io.subDeqRequest.get(0), cancelBypassVec) 320 321 io.deqEntry(0) := Mux(io.compEntryOldestSel.get(0).valid, 322 compEntryOldest.get(0), 323 Mux(io.simpEntryOldestSel.get(0).valid, simpEntryOldest.get(0), subDeqPolicyEntryVec(1))) 324 io.deqEntry(1) := subDeqPolicyEntryVec(0) 325 io.cancelDeqVec(0) := Mux(io.compEntryOldestSel.get(0).valid, 326 compEntryOldestCancel.get(0), 327 Mux(io.simpEntryOldestSel.get(0).valid, simpEntryOldestCancel.get(0), subDeqPolicyCancelBypassVec(1))) 328 io.cancelDeqVec(1) := subDeqPolicyCancelBypassVec(0) 329 } 330 331 when (subDeqPolicyValidVec(0)) { 332 assert(Mux1H(io.subDeqSelOH.get(0), entries).bits.status.robIdx === subDeqPolicyEntryVec(0).bits.status.robIdx, "subDeqSelOH(0) is not the same\n") 333 } 334 when (subDeqPolicyValidVec(1)) { 335 assert(Mux1H(io.subDeqSelOH.get(1), entries).bits.status.robIdx === subDeqPolicyEntryVec(1).bits.status.robIdx, "subDeqSelOH(1) is not the same\n") 336 } 337 } 338 else { 339 if (params.isAllComp || params.isAllSimp) { 340 io.othersEntryOldestSel.get.zipWithIndex.foreach { case (sel, i) => 341 io.deqEntry(i) := Mux(sel.valid, othersEntryOldest.get(i), enqEntryOldest(i)) 342 io.cancelDeqVec(i) := Mux(sel.valid, othersEntryOldestCancel.get(i), enqEntryOldestCancel(i)) 343 } 344 } 345 else { 346 io.compEntryOldestSel.get.zip(io.simpEntryOldestSel.get).zipWithIndex.foreach { case ((compSel, simpSel), i) => 347 io.deqEntry(i) := Mux(compSel.valid, 348 compEntryOldest.get(i), 349 Mux(simpSel.valid, simpEntryOldest.get(i), enqEntryOldest(i))) 350 io.cancelDeqVec(i) := Mux(compSel.valid, 351 compEntryOldestCancel.get(i), 352 Mux(simpSel.valid, simpEntryOldestCancel.get(i), enqEntryOldestCancel(i))) 353 } 354 } 355 } 356 357 if (params.hasIQWakeUp) { 358 cancelBypassVec.zip(srcWakeUpL1ExuOHVec.get).zip(srcTimerVec.get).zip(srcLoadDependencyVec).foreach{ case (((cancelBypass: Bool, l1ExuOH: Vec[Vec[Bool]]), srcTimer: Vec[UInt]), srcLoadDependency: Vec[Vec[UInt]]) => 359 val cancelByOg0 = l1ExuOH.zip(srcTimer).map { 360 case(exuOH, srcTimer) => 361 (exuOH.asUInt & io.og0Cancel.asUInt).orR && srcTimer === 1.U 362 }.reduce(_ | _) 363 val cancelByLd = srcLoadDependency.map(x => LoadShouldCancel(Some(x), io.ldCancel)).reduce(_ | _) 364 cancelBypass := cancelByLd 365 } 366 } else { 367 cancelBypassVec.zip(srcLoadDependencyVec).foreach { case (cancelBypass, srcLoadDependency) => 368 val cancelByLd = srcLoadDependency.map(x => LoadShouldCancel(Some(x), io.ldCancel)).reduce(_ | _) 369 cancelBypass := cancelByLd 370 } 371 } 372 373 io.valid := validVec.asUInt 374 io.canIssue := canIssueVec.asUInt 375 io.fuType := fuTypeVec 376 io.dataSources := dataSourceVec 377 io.srcWakeUpL1ExuOH.foreach(_ := srcWakeUpL1ExuOHVec.get.map(x => VecInit(x.map(_.asUInt)))) 378 io.srcTimer.foreach(_ := srcTimerVec.get) 379 io.loadDependency := loadDependencyVec 380 io.isFirstIssue.zipWithIndex.foreach{ case (isFirstIssue, deqIdx) => 381 isFirstIssue := io.deqSelOH(deqIdx).valid && Mux1H(io.deqSelOH(deqIdx).bits, isFirstIssueVec) 382 } 383 io.simpEntryEnqSelVec.foreach(_ := finalSimpTransSelVec.get.zip(enqEntryTransVec).map(x => x._1 & Fill(SimpEntryNum, x._2.valid))) 384 io.compEntryEnqSelVec.foreach(_ := finalCompTransSelVec.get.zip(compEnqVec.get).map(x => x._1 & Fill(CompEntryNum, x._2.valid))) 385 io.othersEntryEnqSelVec.foreach(_ := finalOthersTransSelVec.get.zip(enqEntryTransVec).map(x => x._1 & Fill(OthersEntryNum, x._2.valid))) 386 io.robIdx.foreach(_ := robIdxVec) 387 io.uopIdx.foreach(_ := uopIdxVec.get) 388 io.cancel.foreach(_ := cancelVec.get) //for debug 389 390 def EntriesConnect(in: CommonInBundle, out: CommonOutBundle, entryIdx: Int) = { 391 in.flush := io.flush 392 in.wakeUpFromWB := io.wakeUpFromWB 393 in.wakeUpFromIQ := io.wakeUpFromIQ 394 in.og0Cancel := io.og0Cancel 395 in.og1Cancel := io.og1Cancel 396 in.ldCancel := io.ldCancel 397 in.deqSel := deqSelVec(entryIdx) 398 in.deqPortIdxWrite := deqPortIdxWriteVec(entryIdx) 399 in.issueResp := issueRespVec(entryIdx) 400 if (params.isVecMemIQ) { 401 in.fromLsq.get.sqDeqPtr := io.vecMemIn.get.sqDeqPtr 402 in.fromLsq.get.lqDeqPtr := io.vecMemIn.get.lqDeqPtr 403 } 404 validVec(entryIdx) := out.valid 405 canIssueVec(entryIdx) := out.canIssue 406 fuTypeVec(entryIdx) := out.fuType 407 robIdxVec(entryIdx) := out.robIdx 408 dataSourceVec(entryIdx) := out.dataSource 409 isFirstIssueVec(entryIdx) := out.isFirstIssue 410 entries(entryIdx) := out.entry 411 deqPortIdxReadVec(entryIdx) := out.deqPortIdxRead 412 issueTimerVec(entryIdx) := out.issueTimerRead 413 srcLoadDependencyVec(entryIdx) := out.srcLoadDependency 414 loadDependencyVec(entryIdx) := out.entry.bits.status.mergedLoadDependency 415 if (params.hasIQWakeUp) { 416 srcWakeUpL1ExuOHVec.get(entryIdx) := out.srcWakeUpL1ExuOH.get 417 srcTimerVec.get(entryIdx) := out.srcTimer.get 418 cancelVec.get(entryIdx) := out.cancel.get 419 } 420 if (params.isVecMemIQ) { 421 uopIdxVec.get(entryIdx) := out.uopIdx.get 422 } 423 entryInValidVec(entryIdx) := out.entryInValid 424 entryOutDeqValidVec(entryIdx) := out.entryOutDeqValid 425 entryOutTransValidVec(entryIdx) := out.entryOutTransValid 426 } 427 428 // entries perf counter 429 // enq 430 for (i <- 0 until params.numEnq) { 431 XSPerfAccumulate(s"enqEntry_${i}_in_cnt", entryInValidVec(i)) 432 XSPerfAccumulate(s"enqEntry_${i}_out_deq_cnt", entryOutDeqValidVec(i)) 433 XSPerfAccumulate(s"enqEntry_${i}_out_trans_cnt", entryOutTransValidVec(i)) 434 } 435 // simple 436 for (i <- 0 until params.numSimp) { 437 XSPerfAccumulate(s"simpEntry_${i}_in_cnt", entryInValidVec(i + params.numEnq)) 438 XSPerfAccumulate(s"simpEntry_${i}_out_deq_cnt", entryOutDeqValidVec(i + params.numEnq)) 439 XSPerfAccumulate(s"simpEntry_${i}_out_trans_cnt", entryOutTransValidVec(i + params.numEnq)) 440 } 441 // complex 442 for (i <- 0 until params.numComp) { 443 XSPerfAccumulate(s"compEntry_${i}_in_cnt", entryInValidVec(i + params.numEnq + params.numSimp)) 444 XSPerfAccumulate(s"compEntry_${i}_out_deq_cnt", entryOutDeqValidVec(i + params.numEnq + params.numSimp)) 445 XSPerfAccumulate(s"compEntry_${i}_out_trans_cnt", entryOutTransValidVec(i + params.numEnq + params.numSimp)) 446 } 447 // total 448 XSPerfAccumulate(s"enqEntry_all_in_cnt", PopCount(entryInValidVec.take(params.numEnq))) 449 XSPerfAccumulate(s"enqEntry_all_out_deq_cnt", PopCount(entryOutDeqValidVec.take(params.numEnq))) 450 XSPerfAccumulate(s"enqEntry_all_out_trans_cnt", PopCount(entryOutTransValidVec.take(params.numEnq))) 451 452 XSPerfAccumulate(s"othersEntry_all_in_cnt", PopCount(entryInValidVec.drop(params.numEnq))) 453 XSPerfAccumulate(s"othersEntry_all_out_deq_cnt", PopCount(entryOutDeqValidVec.drop(params.numEnq))) 454 XSPerfAccumulate(s"othersEntry_all_out_trans_cnt", PopCount(entryOutTransValidVec.drop(params.numEnq))) 455} 456 457class EntriesIO(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 458 val flush = Flipped(ValidIO(new Redirect)) 459 //enq 460 val enq = Vec(params.numEnq, Flipped(ValidIO(new EntryBundle))) 461 val og0Resp = Vec(params.numDeq, Flipped(ValidIO(new EntryDeqRespBundle))) 462 val og1Resp = Vec(params.numDeq, Flipped(ValidIO(new EntryDeqRespBundle))) 463 val og2Resp = OptionWrapper(params.inVfSchd, Vec(params.numDeq, Flipped(ValidIO(new EntryDeqRespBundle)))) 464 //deq sel 465 val deqReady = Vec(params.numDeq, Input(Bool())) 466 val deqSelOH = Vec(params.numDeq, Flipped(ValidIO(UInt(params.numEntries.W)))) 467 val enqEntryOldestSel = Vec(params.numDeq, Flipped(ValidIO(UInt(params.numEnq.W)))) 468 val simpEntryOldestSel = OptionWrapper(params.hasCompAndSimp, Vec(params.numDeq, Flipped(ValidIO(UInt(params.numSimp.W))))) 469 val compEntryOldestSel = OptionWrapper(params.hasCompAndSimp, Vec(params.numDeq, Flipped(ValidIO(UInt(params.numComp.W))))) 470 val othersEntryOldestSel= OptionWrapper(params.isAllComp || params.isAllSimp, Vec(params.numDeq, Flipped(ValidIO(UInt((params.numEntries - params.numEnq).W))))) 471 val subDeqRequest = OptionWrapper(params.deqFuSame, Vec(params.numDeq, Input(UInt(params.numEntries.W)))) 472 val subDeqSelOH = OptionWrapper(params.deqFuSame, Vec(params.numDeq, Input(UInt(params.numEntries.W)))) 473 // wakeup 474 val wakeUpFromWB: MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = Flipped(params.genWBWakeUpSinkValidBundle) 475 val wakeUpFromIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(params.genIQWakeUpSinkValidBundle) 476 val og0Cancel = Input(ExuOH(backendParams.numExu)) 477 val og1Cancel = Input(ExuOH(backendParams.numExu)) 478 val ldCancel = Vec(backendParams.LdExuCnt, Flipped(new LoadCancelIO)) 479 //entries status 480 val valid = Output(UInt(params.numEntries.W)) 481 val canIssue = Output(UInt(params.numEntries.W)) 482 val fuType = Vec(params.numEntries, Output(FuType())) 483 val dataSources = Vec(params.numEntries, Vec(params.numRegSrc, Output(DataSource()))) 484 val loadDependency = Vec(params.numEntries, Vec(LoadPipelineWidth, UInt(3.W))) 485 val srcWakeUpL1ExuOH = OptionWrapper(params.hasIQWakeUp, Vec(params.numEntries, Vec(params.numRegSrc, Output(ExuOH())))) 486 val srcTimer = OptionWrapper(params.hasIQWakeUp, Vec(params.numEntries, Vec(params.numRegSrc, Output(UInt(3.W))))) 487 //deq status 488 val isFirstIssue = Vec(params.numDeq, Output(Bool())) 489 val deqEntry = Vec(params.numDeq, ValidIO(new EntryBundle)) 490 val cancelDeqVec = Vec(params.numDeq, Output(Bool())) 491 492 // load/hybird only 493 val fromLoad = OptionWrapper(params.isLdAddrIQ || params.isHyAddrIQ, new Bundle { 494 val finalIssueResp = Vec(params.numDeq, Flipped(ValidIO(new EntryDeqRespBundle))) 495 val memAddrIssueResp = Vec(params.numDeq, Flipped(ValidIO(new EntryDeqRespBundle))) 496 }) 497 // mem only 498 val fromMem = OptionWrapper(params.isMemAddrIQ, new Bundle { 499 val slowResp = Vec(params.numDeq, Flipped(ValidIO(new EntryDeqRespBundle))) 500 val fastResp = Vec(params.numDeq, Flipped(ValidIO(new EntryDeqRespBundle))) 501 }) 502 // vec mem only 503 val vecMemIn = OptionWrapper(params.isVecMemIQ, new Bundle { 504 val sqDeqPtr = Input(new SqPtr) 505 val lqDeqPtr = Input(new LqPtr) 506 }) 507 val robIdx = OptionWrapper(params.isVecMemIQ, Output(Vec(params.numEntries, new RobPtr))) 508 val uopIdx = OptionWrapper(params.isVecMemIQ, Output(Vec(params.numEntries, UopIdx()))) 509 510 // trans 511 val simpEntryDeqSelVec = OptionWrapper(params.hasCompAndSimp, Vec(params.numEnq, Input(UInt(params.numSimp.W)))) 512 val simpEntryEnqSelVec = OptionWrapper(params.hasCompAndSimp, Vec(params.numEnq, Output(UInt(params.numSimp.W)))) 513 val compEntryEnqSelVec = OptionWrapper(params.hasCompAndSimp, Vec(params.numEnq, Output(UInt(params.numComp.W)))) 514 val othersEntryEnqSelVec = OptionWrapper(params.isAllComp || params.isAllSimp, Vec(params.numEnq, Output(UInt((params.numEntries - params.numEnq).W)))) 515 516 // debug 517 val cancel = OptionWrapper(params.hasIQWakeUp, Output(Vec(params.numEntries, Bool()))) 518 519 def wakeup = wakeUpFromWB ++ wakeUpFromIQ 520} 521