1package xiangshan.backend.issue 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import utility.HasCircularQueuePtrHelper 7import utils._ 8import xiangshan._ 9import xiangshan.backend.Bundles._ 10import xiangshan.backend.datapath.DataConfig.VAddrData 11import xiangshan.backend.datapath.DataSource 12import xiangshan.backend.fu.FuType 13import xiangshan.backend.fu.vector.Utils.NOnes 14import xiangshan.backend.rob.RobPtr 15import xiangshan.mem.{LqPtr, MemWaitUpdateReq, SqPtr} 16import xiangshan.backend.issue.EntryBundles._ 17 18class Entries(implicit p: Parameters, params: IssueBlockParams) extends XSModule { 19 override def desiredName: String = params.getEntryName 20 21 require(params.numEnq <= 2, "number of enq should be no more than 2") 22 23 private val EnqEntryNum = params.numEnq 24 private val OthersEntryNum = params.numEntries - params.numEnq 25 private val SimpEntryNum = params.numSimp 26 private val CompEntryNum = params.numComp 27 val io = IO(new EntriesIO) 28 29 // only memAddrIQ use it 30 val memEtyResps: MixedVec[ValidIO[EntryDeqRespBundle]] = { 31 if (params.isLdAddrIQ && !params.isStAddrIQ) //LDU 32 MixedVecInit(io.og0Resp ++ io.og1Resp ++ io.finalIssueResp.get ++ io.memAddrIssueResp.get) 33 else if (params.isLdAddrIQ && params.isStAddrIQ || params.isHyAddrIQ) //HYU 34 MixedVecInit(io.og0Resp ++ io.og1Resp ++ io.finalIssueResp.get ++ io.memAddrIssueResp.get ++ io.fromMem.get.fastResp ++ io.fromMem.get.slowResp) 35 else if (params.isMemAddrIQ) //STU 36 MixedVecInit(io.og0Resp ++ io.og1Resp ++ io.fromMem.get.slowResp) 37 else MixedVecInit(Seq()) 38 } 39 40 val resps: Vec[Vec[ValidIO[EntryDeqRespBundle]]] = VecInit(io.og0Resp, io.og1Resp, 0.U.asTypeOf(io.og0Resp)) 41 42 //Module 43 val enqEntries = Seq.fill(EnqEntryNum)(Module(EnqEntry(isComp = true)(p, params))) 44 val othersEntriesSimp = Seq.fill(SimpEntryNum)(Module(OthersEntry(isComp = false)(p, params))) 45 val othersEntriesComp = Seq.fill(CompEntryNum)(Module(OthersEntry(isComp = true)(p, params))) 46 val othersEntries = othersEntriesSimp ++ othersEntriesComp 47 val othersTransPolicy = OptionWrapper(params.isAllComp || params.isAllSimp, Module(new EnqPolicy)) 48 val simpTransPolicy = OptionWrapper(params.hasCompAndSimp, Module(new EnqPolicy)) 49 val compTransPolicy = OptionWrapper(params.hasCompAndSimp, Module(new EnqPolicy)) 50 51 //Wire 52 //entries status 53 val entries = Wire(Vec(params.numEntries, ValidIO(new EntryBundle))) 54 val robIdxVec = Wire(Vec(params.numEntries, new RobPtr)) 55 val validVec = Wire(Vec(params.numEntries, Bool())) 56 val canIssueVec = Wire(Vec(params.numEntries, Bool())) 57 val fuTypeVec = Wire(Vec(params.numEntries, FuType())) 58 val isFirstIssueVec = Wire(Vec(params.numEntries, Bool())) 59 val issueTimerVec = Wire(Vec(params.numEntries, UInt(2.W))) 60 //src status 61 val dataSourceVec = Wire(Vec(params.numEntries, Vec(params.numRegSrc, DataSource()))) 62 val loadDependencyVec = Wire(Vec(params.numEntries, Vec(LoadPipelineWidth, UInt(3.W)))) 63 val srcLoadDependencyVec= Wire(Vec(params.numEntries, Vec(params.numRegSrc, Vec(LoadPipelineWidth, UInt(3.W))))) 64 val srcTimerVec = OptionWrapper(params.hasIQWakeUp, Wire(Vec(params.numEntries, Vec(params.numRegSrc, UInt(3.W))))) 65 val srcWakeUpL1ExuOHVec = OptionWrapper(params.hasIQWakeUp, Wire(Vec(params.numEntries, Vec(params.numRegSrc, ExuVec())))) 66 //deq sel 67 val deqSelVec = Wire(Vec(params.numEntries, Bool())) 68 val issueRespVec = Wire(Vec(params.numEntries, ValidIO(new EntryDeqRespBundle))) 69 val deqPortIdxWriteVec = Wire(Vec(params.numEntries, UInt(1.W))) 70 val deqPortIdxReadVec = Wire(Vec(params.numEntries, UInt(1.W))) 71 //trans sel 72 val othersEntryEnqReadyVec = Wire(Vec(OthersEntryNum, Bool())) 73 val othersEntryEnqVec = Wire(Vec(OthersEntryNum, Valid(new EntryBundle))) 74 val enqEntryTransVec = Wire(Vec(EnqEntryNum, Valid(new EntryBundle))) 75 val simpEntryTransVec = OptionWrapper(params.hasCompAndSimp, Wire(Vec(SimpEntryNum, Valid(new EntryBundle)))) 76 val compEnqVec = OptionWrapper(params.hasCompAndSimp, Wire(Vec(EnqEntryNum, Valid(new EntryBundle)))) 77 78 val enqCanTrans2Simp = OptionWrapper(params.hasCompAndSimp, Wire(Bool())) 79 val enqCanTrans2Comp = OptionWrapper(params.hasCompAndSimp, Wire(Bool())) 80 val simpCanTrans2Comp = OptionWrapper(params.hasCompAndSimp, Wire(Vec(EnqEntryNum, Bool()))) 81 val simpTransSelVec = OptionWrapper(params.hasCompAndSimp, Wire(Vec(EnqEntryNum, Valid(UInt(SimpEntryNum.W))))) 82 val compTransSelVec = OptionWrapper(params.hasCompAndSimp, Wire(Vec(EnqEntryNum, Valid(UInt(CompEntryNum.W))))) 83 val finalSimpTransSelVec = OptionWrapper(params.hasCompAndSimp, Wire(Vec(EnqEntryNum, UInt(SimpEntryNum.W)))) 84 val finalCompTransSelVec = OptionWrapper(params.hasCompAndSimp, Wire(Vec(EnqEntryNum, UInt(CompEntryNum.W)))) 85 86 val enqCanTrans2Others = OptionWrapper(params.isAllComp || params.isAllSimp, Wire(Bool())) 87 val othersTransSelVec = OptionWrapper(params.isAllComp || params.isAllSimp, Wire(Vec(EnqEntryNum, Valid(UInt(OthersEntryNum.W))))) 88 val finalOthersTransSelVec = OptionWrapper(params.isAllComp || params.isAllSimp, Wire(Vec(EnqEntryNum, UInt(OthersEntryNum.W)))) 89 90 val simpEntryEnqReadyVec = othersEntryEnqReadyVec.take(SimpEntryNum) 91 val compEntryEnqReadyVec = othersEntryEnqReadyVec.takeRight(CompEntryNum) 92 val simpEntryEnqVec = othersEntryEnqVec.take(SimpEntryNum) 93 val compEntryEnqVec = othersEntryEnqVec.takeRight(CompEntryNum) 94 //debug 95 val cancelVec = OptionWrapper(params.hasIQWakeUp, Wire(Vec(params.numEntries, Bool()))) 96 val entryInValidVec = Wire(Vec(params.numEntries, Bool())) 97 val entryOutDeqValidVec = Wire(Vec(params.numEntries, Bool())) 98 val entryOutTransValidVec = Wire(Vec(params.numEntries, Bool())) 99 //cancel bypass 100 val cancelBypassVec = Wire(Vec(params.numEntries, Bool())) 101 val uopIdxVec = OptionWrapper(params.isVecMemIQ, Wire(Vec(params.numEntries, UopIdx()))) 102 103 104 //enqEntries 105 enqEntries.zipWithIndex.foreach { case (enqEntry, entryIdx) => 106 enqEntry.io.commonIn.enq := io.enq(entryIdx) 107 enqEntry.io.commonIn.transSel := (if (params.isAllComp || params.isAllSimp) enqCanTrans2Others.get && othersTransSelVec.get(entryIdx).valid 108 else enqCanTrans2Simp.get && simpTransSelVec.get(entryIdx).valid || enqCanTrans2Comp.get && compTransSelVec.get(entryIdx).valid) 109 EntriesConnect(enqEntry.io.commonIn, enqEntry.io.commonOut, entryIdx) 110 enqEntry.io.enqDelayWakeUpFromWB := RegNext(io.wakeUpFromWB) 111 enqEntry.io.enqDelayWakeUpFromIQ := RegNext(io.wakeUpFromIQ) 112 enqEntry.io.enqDelayOg0Cancel := RegNext(io.og0Cancel.asUInt) 113 enqEntry.io.enqDelayLdCancel := RegNext(io.ldCancel) 114 enqEntryTransVec(entryIdx) := enqEntry.io.commonOut.transEntry 115 // TODO: move it into EntriesConnect 116 if (params.isVecMemIQ) { 117 enqEntry.io.commonIn.fromLsq.get.sqDeqPtr := io.vecMemIn.get.sqDeqPtr 118 enqEntry.io.commonIn.fromLsq.get.lqDeqPtr := io.vecMemIn.get.lqDeqPtr 119 } 120 } 121 //othersEntries 122 othersEntries.zipWithIndex.foreach { case (othersEntry, entryIdx) => 123 othersEntry.io.commonIn.enq := othersEntryEnqVec(entryIdx) 124 othersEntry.io.commonIn.transSel := (if (params.hasCompAndSimp && (entryIdx < SimpEntryNum)) 125 io.simpEntryDeqSelVec.get.zip(simpCanTrans2Comp.get).map(x => x._1(entryIdx) && x._2).reduce(_ | _) 126 else false.B) 127 EntriesConnect(othersEntry.io.commonIn, othersEntry.io.commonOut, entryIdx + EnqEntryNum) 128 othersEntryEnqReadyVec(entryIdx) := othersEntry.io.commonOut.enqReady 129 if (params.hasCompAndSimp && (entryIdx < SimpEntryNum)) { 130 simpEntryTransVec.get(entryIdx) := othersEntry.io.commonOut.transEntry 131 } 132 if (params.isVecMemIQ) { 133 othersEntry.io.commonIn.fromLsq.get.sqDeqPtr := io.vecMemIn.get.sqDeqPtr 134 othersEntry.io.commonIn.fromLsq.get.lqDeqPtr := io.vecMemIn.get.lqDeqPtr 135 } 136 } 137 138 139 deqSelVec.zip(deqPortIdxWriteVec).zipWithIndex.foreach { case ((deqSel, deqPortIdxWrite), i) => 140 val deqVec = io.deqSelOH.zip(io.deqReady).map(x => x._1.valid && x._1.bits(i) && x._2) 141 deqPortIdxWrite := OHToUInt(deqVec) 142 deqSel := deqVec.reduce(_ | _) 143 } 144 145 146 if (params.isAllComp || params.isAllSimp) { 147 //transPolicy 148 othersTransPolicy.get.io.canEnq := othersEntryEnqReadyVec.asUInt 149 150 // we only allow all or none of the enq entries transfering to others entries. 151 enqCanTrans2Others.get := PopCount(validVec.take(EnqEntryNum)) <= PopCount(othersEntryEnqReadyVec) 152 // othersTransSelVec(i) is the target others entry for enq entry [i]. 153 // note that dispatch does not guarantee the validity of enq entries with low index. 154 // that means in some cases enq entry [0] is invalid while enq entry [1] is valid. 155 // in this case, enq entry [1] should use result [0] of TransPolicy. 156 othersTransSelVec.get(0).valid := othersTransPolicy.get.io.enqSelOHVec(0).valid && validVec(0) 157 othersTransSelVec.get(0).bits := othersTransPolicy.get.io.enqSelOHVec(0).bits 158 if (params.numEnq == 2) { 159 othersTransSelVec.get(1).valid := Mux(!validVec(0), othersTransPolicy.get.io.enqSelOHVec(0).valid, othersTransPolicy.get.io.enqSelOHVec(1).valid) 160 othersTransSelVec.get(1).bits := Mux(!validVec(0), othersTransPolicy.get.io.enqSelOHVec(0).bits, othersTransPolicy.get.io.enqSelOHVec(1).bits) 161 } 162 163 finalOthersTransSelVec.get.zip(othersTransSelVec.get).zipWithIndex.foreach { case ((finalOH, selOH), enqIdx) => 164 finalOH := Fill(OthersEntryNum, enqCanTrans2Others.get && selOH.valid) & selOH.bits 165 } 166 167 //othersEntryEnq 168 othersEntryEnqVec.zipWithIndex.foreach { case (othersEntryEnq, othersIdx) => 169 val othersEnqOH = finalOthersTransSelVec.get.map(_(othersIdx)) 170 if (othersEnqOH.size == 1) 171 othersEntryEnq := Mux(othersEnqOH.head, enqEntryTransVec.head, 0.U.asTypeOf(enqEntryTransVec.head)) 172 else 173 othersEntryEnq := Mux1H(othersEnqOH, enqEntryTransVec) 174 } 175 } 176 else { 177 //transPolicy 178 simpTransPolicy.get.io.canEnq := VecInit(simpEntryEnqReadyVec).asUInt 179 compTransPolicy.get.io.canEnq := VecInit(validVec.takeRight(CompEntryNum).map(!_)).asUInt 180 181 // we only allow all or none of the enq entries transfering to comp/simp entries. 182 // when all of simp entries are empty and comp entries are enough, transfer to comp entries. 183 // otherwise, transfer to simp entries. 184 enqCanTrans2Comp.get := PopCount(validVec.take(EnqEntryNum)) <= PopCount(validVec.takeRight(CompEntryNum).map(!_)) && !validVec.drop(EnqEntryNum).take(SimpEntryNum).reduce(_ || _) 185 enqCanTrans2Simp.get := !enqCanTrans2Comp.get && PopCount(validVec.take(EnqEntryNum)) <= PopCount(simpEntryEnqReadyVec) 186 simpCanTrans2Comp.get.zipWithIndex.foreach { case (canTrans, idx) => 187 canTrans := !enqCanTrans2Comp.get && PopCount(validVec.takeRight(CompEntryNum).map(!_)) >= (idx + 1).U 188 } 189 190 // simp/compTransSelVec(i) is the target simp/comp entry for enq entry [i]. 191 // note that dispatch does not guarantee the validity of enq entries with low index. 192 // that means in some cases enq entry [0] is invalid while enq entry [1] is valid. 193 // in this case, enq entry [1] should use result [0] of TransPolicy. 194 simpTransSelVec.get(0).valid := simpTransPolicy.get.io.enqSelOHVec(0).valid && validVec(0) 195 simpTransSelVec.get(0).bits := simpTransPolicy.get.io.enqSelOHVec(0).bits 196 compTransSelVec.get(0).valid := compTransPolicy.get.io.enqSelOHVec(0).valid && validVec(0) 197 compTransSelVec.get(0).bits := compTransPolicy.get.io.enqSelOHVec(0).bits 198 if (params.numEnq == 2) { 199 simpTransSelVec.get(1).valid := Mux(!validVec(0), simpTransPolicy.get.io.enqSelOHVec(0).valid, simpTransPolicy.get.io.enqSelOHVec(1).valid) 200 simpTransSelVec.get(1).bits := Mux(!validVec(0), simpTransPolicy.get.io.enqSelOHVec(0).bits, simpTransPolicy.get.io.enqSelOHVec(1).bits) 201 compTransSelVec.get(1).valid := Mux(!validVec(0), compTransPolicy.get.io.enqSelOHVec(0).valid, compTransPolicy.get.io.enqSelOHVec(1).valid) 202 compTransSelVec.get(1).bits := Mux(!validVec(0), compTransPolicy.get.io.enqSelOHVec(0).bits, compTransPolicy.get.io.enqSelOHVec(1).bits) 203 } 204 205 finalSimpTransSelVec.get.zip(simpTransSelVec.get).zipWithIndex.foreach { case ((finalOH, selOH), enqIdx) => 206 finalOH := Fill(SimpEntryNum, enqCanTrans2Simp.get && selOH.valid) & selOH.bits 207 } 208 finalCompTransSelVec.get.zip(compTransSelVec.get).zip(compTransPolicy.get.io.enqSelOHVec).zipWithIndex.foreach { 209 case (((finalOH, selOH), origSelOH), enqIdx) => 210 finalOH := Mux(enqCanTrans2Comp.get, Fill(CompEntryNum, selOH.valid) & selOH.bits, Fill(CompEntryNum, origSelOH.valid) & origSelOH.bits) 211 } 212 213 //othersEntryEnq 214 simpEntryEnqVec.zipWithIndex.foreach { case (simpEntryEnq, simpIdx) => 215 val simpEnqOH = finalSimpTransSelVec.get.map(_(simpIdx)) 216 // shit Mux1H directly returns in(0) if the seq has only 1 elements 217 if (simpEnqOH.size == 1) 218 simpEntryEnq := Mux(simpEnqOH.head, enqEntryTransVec.head, 0.U.asTypeOf(enqEntryTransVec.head)) 219 else 220 simpEntryEnq := Mux1H(simpEnqOH, enqEntryTransVec) 221 } 222 223 compEnqVec.get.zip(enqEntryTransVec).zip(io.simpEntryDeqSelVec.get).foreach { case ((compEnq, enqEntry), deqSel) => 224 compEnq := Mux(enqCanTrans2Comp.get, enqEntry, Mux1H(deqSel, simpEntryTransVec.get)) 225 } 226 compEntryEnqVec.zipWithIndex.foreach { case (compEntryEnq, compIdx) => 227 val compEnqOH = finalCompTransSelVec.get.map(_(compIdx)) 228 // shit Mux1H directly returns in(0) if the seq has only 1 elements 229 if (compEnqOH.size == 1) 230 compEntryEnq := Mux(compEnqOH.head, compEnqVec.get.head, 0.U.asTypeOf(compEnqVec.get.head)) 231 else 232 compEntryEnq := Mux1H(compEnqOH, compEnqVec.get) 233 } 234 235 assert(PopCount(simpEntryEnqVec.map(_.valid)) <= params.numEnq.U, "the number of simpEntryEnq is more than numEnq\n") 236 assert(PopCount(compEntryEnqVec.map(_.valid)) <= params.numEnq.U, "the number of compEntryEnq is more than numEnq\n") 237 } 238 239 if(backendParams.debugEn) { 240 dontTouch(othersEntryEnqVec) 241 } 242 243 //issueRespVec 244 if (params.isVecMemIQ) { 245 // vector memory IQ 246 issueRespVec.zip(robIdxVec).zip(uopIdxVec.get).foreach { case ((issueResp, robIdx), uopIdx) => 247 val hitRespsVec = VecInit(resps.flatten.map(x => 248 x.valid && x.bits.robIdx === robIdx && x.bits.uopIdx.get === uopIdx 249 )) 250 issueResp.valid := hitRespsVec.reduce(_ | _) 251 issueResp.bits := Mux1H(hitRespsVec, resps.flatten.map(_.bits)) 252 } 253 } else if (params.isMemAddrIQ) { 254 // scalar memory IQ 255 issueRespVec.zip(robIdxVec).foreach { case (issueResp, robIdx) => 256 val hitRespsVec = VecInit(memEtyResps.map(x => x.valid && (x.bits.robIdx === robIdx)).toSeq) 257 issueResp.valid := hitRespsVec.reduce(_ | _) 258 issueResp.bits := Mux1H(hitRespsVec, memEtyResps.map(_.bits).toSeq) 259 } 260 } 261 else { 262 issueRespVec.zip(issueTimerVec).zip(deqPortIdxReadVec).foreach { case ((issueResp, issueTimer), deqPortIdx) => 263 val Resp = resps(issueTimer)(deqPortIdx) 264 issueResp := Resp 265 } 266 } 267 268 //deq 269 val enqEntryOldest = Wire(Vec(params.numDeq, ValidIO(new EntryBundle))) 270 val simpEntryOldest = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numDeq, ValidIO(new EntryBundle)))) 271 val compEntryOldest = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numDeq, ValidIO(new EntryBundle)))) 272 val othersEntryOldest = OptionWrapper(params.isAllComp || params.isAllSimp, Wire(Vec(params.numDeq, ValidIO(new EntryBundle)))) 273 val enqEntryOldestCancel = Wire(Vec(params.numDeq, Bool())) 274 val simpEntryOldestCancel = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numDeq, Bool()))) 275 val compEntryOldestCancel = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numDeq, Bool()))) 276 val othersEntryOldestCancel = OptionWrapper(params.isAllComp || params.isAllSimp, Wire(Vec(params.numDeq, Bool()))) 277 278 io.enqEntryOldestSel.zipWithIndex.map { case (sel, deqIdx) => 279 enqEntryOldest(deqIdx) := Mux1H(sel.bits, entries.take(EnqEntryNum)) 280 enqEntryOldestCancel(deqIdx) := Mux1H(sel.bits, cancelBypassVec.take(EnqEntryNum)) 281 } 282 283 if (params.isAllComp || params.isAllSimp) { 284 io.othersEntryOldestSel.get.zipWithIndex.map { case (sel, deqIdx) => 285 othersEntryOldest.get(deqIdx) := Mux1H(sel.bits, entries.drop(EnqEntryNum)) 286 othersEntryOldestCancel.get(deqIdx) := Mux1H(sel.bits, cancelBypassVec.drop(EnqEntryNum)) 287 } 288 } 289 else { 290 io.simpEntryOldestSel.get.zipWithIndex.map { case (sel, deqIdx) => 291 simpEntryOldest.get(deqIdx) := Mux1H(sel.bits, entries.drop(EnqEntryNum).take(SimpEntryNum)) 292 simpEntryOldestCancel.get(deqIdx) := Mux1H(sel.bits, cancelBypassVec.drop(EnqEntryNum).take(SimpEntryNum)) 293 } 294 io.compEntryOldestSel.get.zipWithIndex.map { case (sel, deqIdx) => 295 compEntryOldest.get(deqIdx) := Mux1H(sel.bits, entries.drop(EnqEntryNum).takeRight(CompEntryNum)) 296 compEntryOldestCancel.get(deqIdx) := Mux1H(sel.bits, cancelBypassVec.drop(EnqEntryNum).takeRight(CompEntryNum)) 297 } 298 } 299 300 if (params.deqFuSame) { 301 val subDeqPolicyEntryVec = Wire(Vec(params.numDeq, ValidIO(new EntryBundle))) 302 val subDeqPolicyValidVec = Wire(Vec(params.numDeq, Bool())) 303 val subDeqPolicyCancelBypassVec = Wire(Vec(params.numDeq, Bool())) 304 305 subDeqPolicyValidVec(0) := PopCount(io.subDeqRequest.get(0)) >= 1.U 306 subDeqPolicyValidVec(1) := PopCount(io.subDeqRequest.get(0)) >= 2.U 307 308 if (params.isAllComp || params.isAllSimp) { 309 subDeqPolicyEntryVec(0) := PriorityMux(io.subDeqRequest.get(0), entries) 310 subDeqPolicyEntryVec(1) := PriorityMux(Reverse(io.subDeqRequest.get(0)), entries.reverse) 311 subDeqPolicyCancelBypassVec(0) := PriorityMux(io.subDeqRequest.get(0), cancelBypassVec) 312 subDeqPolicyCancelBypassVec(1) := PriorityMux(Reverse(io.subDeqRequest.get(0)), cancelBypassVec.reverse) 313 314 io.deqEntry(0) := Mux(io.othersEntryOldestSel.get(0).valid, othersEntryOldest.get(0), subDeqPolicyEntryVec(1)) 315 io.deqEntry(1) := subDeqPolicyEntryVec(0) 316 io.cancelDeqVec(0) := Mux(io.othersEntryOldestSel.get(0).valid, othersEntryOldestCancel.get(0), subDeqPolicyCancelBypassVec(1)) 317 io.cancelDeqVec(1) := subDeqPolicyCancelBypassVec(0) 318 } 319 else { 320 subDeqPolicyEntryVec(0) := PriorityMux(Reverse(io.subDeqRequest.get(0)), entries.reverse) 321 subDeqPolicyEntryVec(1) := PriorityMux(io.subDeqRequest.get(0), entries) 322 subDeqPolicyCancelBypassVec(0) := PriorityMux(Reverse(io.subDeqRequest.get(0)), cancelBypassVec.reverse) 323 subDeqPolicyCancelBypassVec(1) := PriorityMux(io.subDeqRequest.get(0), cancelBypassVec) 324 325 io.deqEntry(0) := Mux(io.compEntryOldestSel.get(0).valid, 326 compEntryOldest.get(0), 327 Mux(io.simpEntryOldestSel.get(0).valid, simpEntryOldest.get(0), subDeqPolicyEntryVec(1))) 328 io.deqEntry(1) := subDeqPolicyEntryVec(0) 329 io.cancelDeqVec(0) := Mux(io.compEntryOldestSel.get(0).valid, 330 compEntryOldestCancel.get(0), 331 Mux(io.simpEntryOldestSel.get(0).valid, simpEntryOldestCancel.get(0), subDeqPolicyCancelBypassVec(1))) 332 io.cancelDeqVec(1) := subDeqPolicyCancelBypassVec(0) 333 } 334 335 when (subDeqPolicyValidVec(0)) { 336 assert(Mux1H(io.subDeqSelOH.get(0), entries).bits.status.robIdx === subDeqPolicyEntryVec(0).bits.status.robIdx, "subDeqSelOH(0) is not the same\n") 337 } 338 when (subDeqPolicyValidVec(1)) { 339 assert(Mux1H(io.subDeqSelOH.get(1), entries).bits.status.robIdx === subDeqPolicyEntryVec(1).bits.status.robIdx, "subDeqSelOH(1) is not the same\n") 340 } 341 } 342 else { 343 if (params.isAllComp || params.isAllSimp) { 344 io.othersEntryOldestSel.get.zipWithIndex.foreach { case (sel, i) => 345 io.deqEntry(i) := Mux(sel.valid, othersEntryOldest.get(i), enqEntryOldest(i)) 346 io.cancelDeqVec(i) := Mux(sel.valid, othersEntryOldestCancel.get(i), enqEntryOldestCancel(i)) 347 } 348 } 349 else { 350 io.compEntryOldestSel.get.zip(io.simpEntryOldestSel.get).zipWithIndex.foreach { case ((compSel, simpSel), i) => 351 io.deqEntry(i) := Mux(compSel.valid, 352 compEntryOldest.get(i), 353 Mux(simpSel.valid, simpEntryOldest.get(i), enqEntryOldest(i))) 354 io.cancelDeqVec(i) := Mux(compSel.valid, 355 compEntryOldestCancel.get(i), 356 Mux(simpSel.valid, simpEntryOldestCancel.get(i), enqEntryOldestCancel(i))) 357 } 358 } 359 } 360 361 if (params.hasIQWakeUp) { 362 cancelBypassVec.zip(srcWakeUpL1ExuOHVec.get).zip(srcTimerVec.get).zip(srcLoadDependencyVec).foreach{ case (((cancelBypass: Bool, l1ExuOH: Vec[Vec[Bool]]), srcTimer: Vec[UInt]), srcLoadDependency: Vec[Vec[UInt]]) => 363 val cancelByOg0 = l1ExuOH.zip(srcTimer).map { 364 case(exuOH, srcTimer) => 365 (exuOH.asUInt & io.og0Cancel.asUInt).orR && srcTimer === 1.U 366 }.reduce(_ | _) 367 val cancelByLd = srcLoadDependency.map(x => LoadShouldCancel(Some(x), io.ldCancel)).reduce(_ | _) 368 cancelBypass := cancelByOg0 || cancelByLd 369 } 370 } else { 371 cancelBypassVec.zip(srcLoadDependencyVec).foreach { case (cancelBypass, srcLoadDependency) => 372 val cancelByLd = srcLoadDependency.map(x => LoadShouldCancel(Some(x), io.ldCancel)).reduce(_ | _) 373 cancelBypass := cancelByLd 374 } 375 } 376 377 io.valid := validVec.asUInt 378 io.canIssue := canIssueVec.asUInt 379 io.fuType := fuTypeVec 380 io.dataSources := dataSourceVec 381 io.srcWakeUpL1ExuOH.foreach(_ := srcWakeUpL1ExuOHVec.get.map(x => VecInit(x.map(_.asUInt)))) 382 io.srcTimer.foreach(_ := srcTimerVec.get) 383 io.loadDependency := loadDependencyVec 384 io.isFirstIssue.zipWithIndex.foreach{ case (isFirstIssue, deqIdx) => 385 isFirstIssue := io.deqSelOH(deqIdx).valid && Mux1H(io.deqSelOH(deqIdx).bits, isFirstIssueVec) 386 } 387 io.simpEntryEnqSelVec.foreach(_ := finalSimpTransSelVec.get.zip(enqEntryTransVec).map(x => x._1 & Fill(SimpEntryNum, x._2.valid))) 388 io.compEntryEnqSelVec.foreach(_ := finalCompTransSelVec.get.zip(compEnqVec.get).map(x => x._1 & Fill(CompEntryNum, x._2.valid))) 389 io.othersEntryEnqSelVec.foreach(_ := finalOthersTransSelVec.get.zip(enqEntryTransVec).map(x => x._1 & Fill(OthersEntryNum, x._2.valid))) 390 io.robIdx.foreach(_ := robIdxVec) 391 io.uopIdx.foreach(_ := uopIdxVec.get) 392 io.rsFeedback := 0.U.asTypeOf(io.rsFeedback) //should be removed 393 io.cancel.foreach(_ := cancelVec.get) //for debug 394 395 def EntriesConnect(in: CommonInBundle, out: CommonOutBundle, entryIdx: Int) = { 396 in.flush := io.flush 397 in.wakeUpFromWB := io.wakeUpFromWB 398 in.wakeUpFromIQ := io.wakeUpFromIQ 399 in.og0Cancel := io.og0Cancel 400 in.og1Cancel := io.og1Cancel 401 in.ldCancel := io.ldCancel 402 in.deqSel := deqSelVec(entryIdx) 403 in.deqPortIdxWrite := deqPortIdxWriteVec(entryIdx) 404 in.issueResp := issueRespVec(entryIdx) 405 if (params.isMemAddrIQ) { 406 in.fromMem.get.stIssuePtr := io.fromMem.get.stIssuePtr 407 in.fromMem.get.memWaitUpdateReq := io.fromMem.get.memWaitUpdateReq 408 } 409 if (params.isVecMemIQ) { 410 in.fromLsq.get.sqDeqPtr := io.vecMemIn.get.sqDeqPtr 411 in.fromLsq.get.lqDeqPtr := io.vecMemIn.get.lqDeqPtr 412 } 413 validVec(entryIdx) := out.valid 414 canIssueVec(entryIdx) := out.canIssue 415 fuTypeVec(entryIdx) := out.fuType 416 robIdxVec(entryIdx) := out.robIdx 417 dataSourceVec(entryIdx) := out.dataSource 418 isFirstIssueVec(entryIdx) := out.isFirstIssue 419 entries(entryIdx) := out.entry 420 deqPortIdxReadVec(entryIdx) := out.deqPortIdxRead 421 issueTimerVec(entryIdx) := out.issueTimerRead 422 srcLoadDependencyVec(entryIdx) := out.srcLoadDependency 423 loadDependencyVec(entryIdx) := out.entry.bits.status.mergedLoadDependency 424 if (params.hasIQWakeUp) { 425 srcWakeUpL1ExuOHVec.get(entryIdx) := out.srcWakeUpL1ExuOH.get 426 srcTimerVec.get(entryIdx) := out.srcTimer.get 427 cancelVec.get(entryIdx) := out.cancel.get 428 } 429 if (params.isVecMemIQ) { 430 uopIdxVec.get(entryIdx) := out.uopIdx.get 431 } 432 entryInValidVec(entryIdx) := out.entryInValid 433 entryOutDeqValidVec(entryIdx) := out.entryOutDeqValid 434 entryOutTransValidVec(entryIdx) := out.entryOutTransValid 435 } 436 437 // entries perf counter 438 // enq 439 for (i <- 0 until params.numEnq) { 440 XSPerfAccumulate(s"enqEntry_${i}_in_cnt", entryInValidVec(i)) 441 XSPerfAccumulate(s"enqEntry_${i}_out_deq_cnt", entryOutDeqValidVec(i)) 442 XSPerfAccumulate(s"enqEntry_${i}_out_trans_cnt", entryOutTransValidVec(i)) 443 } 444 // simple 445 for (i <- 0 until params.numSimp) { 446 XSPerfAccumulate(s"simpEntry_${i}_in_cnt", entryInValidVec(i + params.numEnq)) 447 XSPerfAccumulate(s"simpEntry_${i}_out_deq_cnt", entryOutDeqValidVec(i + params.numEnq)) 448 XSPerfAccumulate(s"simpEntry_${i}_out_trans_cnt", entryOutTransValidVec(i + params.numEnq)) 449 } 450 // complex 451 for (i <- 0 until params.numComp) { 452 XSPerfAccumulate(s"compEntry_${i}_in_cnt", entryInValidVec(i + params.numEnq + params.numSimp)) 453 XSPerfAccumulate(s"compEntry_${i}_out_deq_cnt", entryOutDeqValidVec(i + params.numEnq + params.numSimp)) 454 XSPerfAccumulate(s"compEntry_${i}_out_trans_cnt", entryOutTransValidVec(i + params.numEnq + params.numSimp)) 455 } 456 // total 457 XSPerfAccumulate(s"enqEntry_all_in_cnt", PopCount(entryInValidVec.take(params.numEnq))) 458 XSPerfAccumulate(s"enqEntry_all_out_deq_cnt", PopCount(entryOutDeqValidVec.take(params.numEnq))) 459 XSPerfAccumulate(s"enqEntry_all_out_trans_cnt", PopCount(entryOutTransValidVec.take(params.numEnq))) 460 461 XSPerfAccumulate(s"othersEntry_all_in_cnt", PopCount(entryInValidVec.drop(params.numEnq))) 462 XSPerfAccumulate(s"othersEntry_all_out_deq_cnt", PopCount(entryOutDeqValidVec.drop(params.numEnq))) 463 XSPerfAccumulate(s"othersEntry_all_out_trans_cnt", PopCount(entryOutTransValidVec.drop(params.numEnq))) 464} 465 466class EntriesIO(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 467 val flush = Flipped(ValidIO(new Redirect)) 468 //enq 469 val enq = Vec(params.numEnq, Flipped(ValidIO(new EntryBundle))) 470 val og0Resp = Vec(params.numDeq, Flipped(ValidIO(new EntryDeqRespBundle))) 471 val og1Resp = Vec(params.numDeq, Flipped(ValidIO(new EntryDeqRespBundle))) 472 val finalIssueResp = OptionWrapper(params.LdExuCnt > 0, Vec(params.numDeq, Flipped(ValidIO(new EntryDeqRespBundle)))) 473 val memAddrIssueResp = OptionWrapper(params.LdExuCnt > 0, Vec(params.numDeq, Flipped(ValidIO(new EntryDeqRespBundle)))) 474 //deq sel 475 val deqReady = Vec(params.numDeq, Input(Bool())) 476 val deqSelOH = Vec(params.numDeq, Flipped(ValidIO(UInt(params.numEntries.W)))) 477 val enqEntryOldestSel = Vec(params.numDeq, Flipped(ValidIO(UInt(params.numEnq.W)))) 478 val simpEntryOldestSel = OptionWrapper(params.hasCompAndSimp, Vec(params.numDeq, Flipped(ValidIO(UInt(params.numSimp.W))))) 479 val compEntryOldestSel = OptionWrapper(params.hasCompAndSimp, Vec(params.numDeq, Flipped(ValidIO(UInt(params.numComp.W))))) 480 val othersEntryOldestSel= OptionWrapper(params.isAllComp || params.isAllSimp, Vec(params.numDeq, Flipped(ValidIO(UInt((params.numEntries - params.numEnq).W))))) 481 val subDeqRequest = OptionWrapper(params.deqFuSame, Vec(params.numDeq, Input(UInt(params.numEntries.W)))) 482 val subDeqSelOH = OptionWrapper(params.deqFuSame, Vec(params.numDeq, Input(UInt(params.numEntries.W)))) 483 // wakeup 484 val wakeUpFromWB: MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = Flipped(params.genWBWakeUpSinkValidBundle) 485 val wakeUpFromIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(params.genIQWakeUpSinkValidBundle) 486 val og0Cancel = Input(ExuOH(backendParams.numExu)) 487 val og1Cancel = Input(ExuOH(backendParams.numExu)) 488 val ldCancel = Vec(backendParams.LdExuCnt, Flipped(new LoadCancelIO)) 489 //entries status 490 val valid = Output(UInt(params.numEntries.W)) 491 val canIssue = Output(UInt(params.numEntries.W)) 492 val fuType = Vec(params.numEntries, Output(FuType())) 493 val dataSources = Vec(params.numEntries, Vec(params.numRegSrc, Output(DataSource()))) 494 val loadDependency = Vec(params.numEntries, Vec(LoadPipelineWidth, UInt(3.W))) 495 val srcWakeUpL1ExuOH = OptionWrapper(params.hasIQWakeUp, Vec(params.numEntries, Vec(params.numRegSrc, Output(ExuOH())))) 496 val srcTimer = OptionWrapper(params.hasIQWakeUp, Vec(params.numEntries, Vec(params.numRegSrc, Output(UInt(3.W))))) 497 //deq status 498 val isFirstIssue = Vec(params.numDeq, Output(Bool())) 499 val deqEntry = Vec(params.numDeq, ValidIO(new EntryBundle)) 500 val cancelDeqVec = Vec(params.numDeq, Output(Bool())) 501 // mem only 502 val fromMem = if (params.isMemAddrIQ) Some(new Bundle { 503 val stIssuePtr = Input(new SqPtr) 504 val memWaitUpdateReq = Flipped(new MemWaitUpdateReq) 505 val slowResp = Vec(params.numDeq, Flipped(ValidIO(new EntryDeqRespBundle))) 506 val fastResp = Vec(params.numDeq, Flipped(ValidIO(new EntryDeqRespBundle))) 507 }) else None 508 val vecMemIn = OptionWrapper(params.isVecMemIQ, new Bundle { 509 val sqDeqPtr = Input(new SqPtr) 510 val lqDeqPtr = Input(new LqPtr) 511 }) 512 513 val robIdx = OptionWrapper(params.isVecMemIQ, Output(Vec(params.numEntries, new RobPtr))) 514 val uopIdx = OptionWrapper(params.isVecMemIQ, Output(Vec(params.numEntries, UopIdx()))) 515 516 val rsFeedback = Output(Vec(5, Bool())) 517 // trans 518 val simpEntryDeqSelVec = OptionWrapper(params.hasCompAndSimp, Vec(params.numEnq, Input(UInt(params.numSimp.W)))) 519 val simpEntryEnqSelVec = OptionWrapper(params.hasCompAndSimp, Vec(params.numEnq, Output(UInt(params.numSimp.W)))) 520 val compEntryEnqSelVec = OptionWrapper(params.hasCompAndSimp, Vec(params.numEnq, Output(UInt(params.numComp.W)))) 521 val othersEntryEnqSelVec = OptionWrapper(params.isAllComp || params.isAllSimp, Vec(params.numEnq, Output(UInt((params.numEntries - params.numEnq).W)))) 522 523 // debug 524 val cancel = OptionWrapper(params.hasIQWakeUp, Output(Vec(params.numEntries, Bool()))) 525 526 def wakeup = wakeUpFromWB ++ wakeUpFromIQ 527} 528