1package xiangshan.backend.issue 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import utility.HasCircularQueuePtrHelper 7import utils._ 8import xiangshan._ 9import xiangshan.backend.Bundles._ 10import xiangshan.backend.datapath.DataConfig.VAddrData 11import xiangshan.backend.datapath.DataSource 12import xiangshan.backend.fu.FuType 13import xiangshan.backend.fu.vector.Utils.NOnes 14import xiangshan.backend.rob.RobPtr 15import xiangshan.mem.{LqPtr, MemWaitUpdateReq, SqPtr} 16import xiangshan.backend.issue.EntryBundles._ 17 18class Entries(implicit p: Parameters, params: IssueBlockParams) extends XSModule { 19 override def desiredName: String = params.getEntryName 20 21 require(params.numEnq <= 2, "number of enq should be no more than 2") 22 23 private val EnqEntryNum = params.numEnq 24 private val OthersEntryNum = params.numEntries - params.numEnq 25 private val SimpEntryNum = params.numSimp 26 private val CompEntryNum = params.numComp 27 val io = IO(new EntriesIO) 28 29 // only memAddrIQ use it 30 val memEtyResps: MixedVec[ValidIO[EntryDeqRespBundle]] = { 31 if (params.isLdAddrIQ && !params.isStAddrIQ) //LDU 32 MixedVecInit(io.og0Resp ++ io.og1Resp ++ io.fromLoad.get.finalIssueResp ++ io.fromLoad.get.memAddrIssueResp) 33 else if (params.isLdAddrIQ && params.isStAddrIQ || params.isHyAddrIQ) //HYU 34 MixedVecInit(io.og0Resp ++ io.og1Resp ++ io.fromLoad.get.finalIssueResp ++ io.fromLoad.get.memAddrIssueResp ++ io.fromMem.get.fastResp ++ io.fromMem.get.slowResp) 35 else if (params.isMemAddrIQ) //STU, VLDU, VSTU 36 MixedVecInit(io.og0Resp ++ io.og1Resp ++ io.fromMem.get.slowResp) 37 else MixedVecInit(Seq()) 38 } 39 40 val resps: Vec[Vec[ValidIO[EntryDeqRespBundle]]] = VecInit(io.og0Resp, io.og1Resp, 0.U.asTypeOf(io.og0Resp)) 41 42 //Module 43 val enqEntries = Seq.fill(EnqEntryNum)(Module(EnqEntry(isComp = true)(p, params))) 44 val othersEntriesSimp = Seq.fill(SimpEntryNum)(Module(OthersEntry(isComp = false)(p, params))) 45 val othersEntriesComp = Seq.fill(CompEntryNum)(Module(OthersEntry(isComp = true)(p, params))) 46 val othersEntries = othersEntriesSimp ++ othersEntriesComp 47 val othersTransPolicy = OptionWrapper(params.isAllComp || params.isAllSimp, Module(new EnqPolicy)) 48 val simpTransPolicy = OptionWrapper(params.hasCompAndSimp, Module(new EnqPolicy)) 49 val compTransPolicy = OptionWrapper(params.hasCompAndSimp, Module(new EnqPolicy)) 50 51 //Wire 52 //entries status 53 val entries = Wire(Vec(params.numEntries, ValidIO(new EntryBundle))) 54 val robIdxVec = Wire(Vec(params.numEntries, new RobPtr)) 55 val validVec = Wire(Vec(params.numEntries, Bool())) 56 val canIssueVec = Wire(Vec(params.numEntries, Bool())) 57 val fuTypeVec = Wire(Vec(params.numEntries, FuType())) 58 val isFirstIssueVec = Wire(Vec(params.numEntries, Bool())) 59 val issueTimerVec = Wire(Vec(params.numEntries, UInt(2.W))) 60 val uopIdxVec = OptionWrapper(params.isVecMemIQ, Wire(Vec(params.numEntries, UopIdx()))) 61 //src status 62 val dataSourceVec = Wire(Vec(params.numEntries, Vec(params.numRegSrc, DataSource()))) 63 val loadDependencyVec = Wire(Vec(params.numEntries, Vec(LoadPipelineWidth, UInt(3.W)))) 64 val srcLoadDependencyVec= Wire(Vec(params.numEntries, Vec(params.numRegSrc, Vec(LoadPipelineWidth, UInt(3.W))))) 65 val srcTimerVec = OptionWrapper(params.hasIQWakeUp, Wire(Vec(params.numEntries, Vec(params.numRegSrc, UInt(3.W))))) 66 val srcWakeUpL1ExuOHVec = OptionWrapper(params.hasIQWakeUp, Wire(Vec(params.numEntries, Vec(params.numRegSrc, ExuVec())))) 67 //deq sel 68 val deqSelVec = Wire(Vec(params.numEntries, Bool())) 69 val issueRespVec = Wire(Vec(params.numEntries, ValidIO(new EntryDeqRespBundle))) 70 val deqPortIdxWriteVec = Wire(Vec(params.numEntries, UInt(1.W))) 71 val deqPortIdxReadVec = Wire(Vec(params.numEntries, UInt(1.W))) 72 //trans sel 73 val othersEntryEnqReadyVec = Wire(Vec(OthersEntryNum, Bool())) 74 val othersEntryEnqVec = Wire(Vec(OthersEntryNum, Valid(new EntryBundle))) 75 val enqEntryTransVec = Wire(Vec(EnqEntryNum, Valid(new EntryBundle))) 76 val simpEntryTransVec = OptionWrapper(params.hasCompAndSimp, Wire(Vec(SimpEntryNum, Valid(new EntryBundle)))) 77 val compEnqVec = OptionWrapper(params.hasCompAndSimp, Wire(Vec(EnqEntryNum, Valid(new EntryBundle)))) 78 79 val enqCanTrans2Simp = OptionWrapper(params.hasCompAndSimp, Wire(Bool())) 80 val enqCanTrans2Comp = OptionWrapper(params.hasCompAndSimp, Wire(Bool())) 81 val simpCanTrans2Comp = OptionWrapper(params.hasCompAndSimp, Wire(Vec(EnqEntryNum, Bool()))) 82 val simpTransSelVec = OptionWrapper(params.hasCompAndSimp, Wire(Vec(EnqEntryNum, Valid(UInt(SimpEntryNum.W))))) 83 val compTransSelVec = OptionWrapper(params.hasCompAndSimp, Wire(Vec(EnqEntryNum, Valid(UInt(CompEntryNum.W))))) 84 val finalSimpTransSelVec = OptionWrapper(params.hasCompAndSimp, Wire(Vec(EnqEntryNum, UInt(SimpEntryNum.W)))) 85 val finalCompTransSelVec = OptionWrapper(params.hasCompAndSimp, Wire(Vec(EnqEntryNum, UInt(CompEntryNum.W)))) 86 87 val enqCanTrans2Others = OptionWrapper(params.isAllComp || params.isAllSimp, Wire(Bool())) 88 val othersTransSelVec = OptionWrapper(params.isAllComp || params.isAllSimp, Wire(Vec(EnqEntryNum, Valid(UInt(OthersEntryNum.W))))) 89 val finalOthersTransSelVec = OptionWrapper(params.isAllComp || params.isAllSimp, Wire(Vec(EnqEntryNum, UInt(OthersEntryNum.W)))) 90 91 val simpEntryEnqReadyVec = othersEntryEnqReadyVec.take(SimpEntryNum) 92 val compEntryEnqReadyVec = othersEntryEnqReadyVec.takeRight(CompEntryNum) 93 val simpEntryEnqVec = othersEntryEnqVec.take(SimpEntryNum) 94 val compEntryEnqVec = othersEntryEnqVec.takeRight(CompEntryNum) 95 //debug 96 val cancelVec = OptionWrapper(params.hasIQWakeUp, Wire(Vec(params.numEntries, Bool()))) 97 val entryInValidVec = Wire(Vec(params.numEntries, Bool())) 98 val entryOutDeqValidVec = Wire(Vec(params.numEntries, Bool())) 99 val entryOutTransValidVec = Wire(Vec(params.numEntries, Bool())) 100 //cancel bypass 101 val cancelBypassVec = Wire(Vec(params.numEntries, Bool())) 102 103 104 //enqEntries 105 enqEntries.zipWithIndex.foreach { case (enqEntry, entryIdx) => 106 enqEntry.io.commonIn.enq := io.enq(entryIdx) 107 enqEntry.io.commonIn.transSel := (if (params.isAllComp || params.isAllSimp) enqCanTrans2Others.get && othersTransSelVec.get(entryIdx).valid 108 else enqCanTrans2Simp.get && simpTransSelVec.get(entryIdx).valid || enqCanTrans2Comp.get && compTransSelVec.get(entryIdx).valid) 109 EntriesConnect(enqEntry.io.commonIn, enqEntry.io.commonOut, entryIdx) 110 enqEntry.io.enqDelayWakeUpFromWB := RegEnable(io.wakeUpFromWB, io.enq(entryIdx).valid) 111 enqEntry.io.enqDelayWakeUpFromIQ := RegEnable(io.wakeUpFromIQ, io.enq(entryIdx).valid) 112 enqEntry.io.enqDelayOg0Cancel := RegNext(io.og0Cancel.asUInt) 113 enqEntry.io.enqDelayLdCancel := RegNext(io.ldCancel) 114 enqEntryTransVec(entryIdx) := enqEntry.io.commonOut.transEntry 115 } 116 //othersEntries 117 othersEntries.zipWithIndex.foreach { case (othersEntry, entryIdx) => 118 othersEntry.io.commonIn.enq := othersEntryEnqVec(entryIdx) 119 othersEntry.io.commonIn.transSel := (if (params.hasCompAndSimp && (entryIdx < SimpEntryNum)) 120 io.simpEntryDeqSelVec.get.zip(simpCanTrans2Comp.get).map(x => x._1(entryIdx) && x._2).reduce(_ | _) 121 else false.B) 122 EntriesConnect(othersEntry.io.commonIn, othersEntry.io.commonOut, entryIdx + EnqEntryNum) 123 othersEntryEnqReadyVec(entryIdx) := othersEntry.io.commonOut.enqReady 124 if (params.hasCompAndSimp && (entryIdx < SimpEntryNum)) { 125 simpEntryTransVec.get(entryIdx) := othersEntry.io.commonOut.transEntry 126 } 127 } 128 129 130 deqSelVec.zip(deqPortIdxWriteVec).zipWithIndex.foreach { case ((deqSel, deqPortIdxWrite), i) => 131 val deqVec = io.deqSelOH.zip(io.deqReady).map(x => x._1.valid && x._1.bits(i) && x._2) 132 deqPortIdxWrite := OHToUInt(deqVec) 133 deqSel := deqVec.reduce(_ | _) 134 } 135 136 137 if (params.isAllComp || params.isAllSimp) { 138 //transPolicy 139 othersTransPolicy.get.io.canEnq := othersEntryEnqReadyVec.asUInt 140 141 // we only allow all or none of the enq entries transfering to others entries. 142 enqCanTrans2Others.get := PopCount(validVec.take(EnqEntryNum)) <= PopCount(othersEntryEnqReadyVec) 143 // othersTransSelVec(i) is the target others entry for enq entry [i]. 144 // note that dispatch does not guarantee the validity of enq entries with low index. 145 // that means in some cases enq entry [0] is invalid while enq entry [1] is valid. 146 // in this case, enq entry [1] should use result [0] of TransPolicy. 147 othersTransSelVec.get(0).valid := othersTransPolicy.get.io.enqSelOHVec(0).valid && validVec(0) 148 othersTransSelVec.get(0).bits := othersTransPolicy.get.io.enqSelOHVec(0).bits 149 if (params.numEnq == 2) { 150 othersTransSelVec.get(1).valid := Mux(!validVec(0), othersTransPolicy.get.io.enqSelOHVec(0).valid, othersTransPolicy.get.io.enqSelOHVec(1).valid) 151 othersTransSelVec.get(1).bits := Mux(!validVec(0), othersTransPolicy.get.io.enqSelOHVec(0).bits, othersTransPolicy.get.io.enqSelOHVec(1).bits) 152 } 153 154 finalOthersTransSelVec.get.zip(othersTransSelVec.get).zipWithIndex.foreach { case ((finalOH, selOH), enqIdx) => 155 finalOH := Fill(OthersEntryNum, enqCanTrans2Others.get && selOH.valid) & selOH.bits 156 } 157 158 //othersEntryEnq 159 othersEntryEnqVec.zipWithIndex.foreach { case (othersEntryEnq, othersIdx) => 160 val othersEnqOH = finalOthersTransSelVec.get.map(_(othersIdx)) 161 if (othersEnqOH.size == 1) 162 othersEntryEnq := Mux(othersEnqOH.head, enqEntryTransVec.head, 0.U.asTypeOf(enqEntryTransVec.head)) 163 else 164 othersEntryEnq := Mux1H(othersEnqOH, enqEntryTransVec) 165 } 166 } 167 else { 168 //transPolicy 169 simpTransPolicy.get.io.canEnq := VecInit(simpEntryEnqReadyVec).asUInt 170 compTransPolicy.get.io.canEnq := VecInit(validVec.takeRight(CompEntryNum).map(!_)).asUInt 171 172 // we only allow all or none of the enq entries transfering to comp/simp entries. 173 // when all of simp entries are empty and comp entries are enough, transfer to comp entries. 174 // otherwise, transfer to simp entries. 175 enqCanTrans2Comp.get := PopCount(validVec.take(EnqEntryNum)) <= PopCount(validVec.takeRight(CompEntryNum).map(!_)) && !validVec.drop(EnqEntryNum).take(SimpEntryNum).reduce(_ || _) 176 enqCanTrans2Simp.get := !enqCanTrans2Comp.get && PopCount(validVec.take(EnqEntryNum)) <= PopCount(simpEntryEnqReadyVec) 177 simpCanTrans2Comp.get.zipWithIndex.foreach { case (canTrans, idx) => 178 canTrans := !enqCanTrans2Comp.get && PopCount(validVec.takeRight(CompEntryNum).map(!_)) >= (idx + 1).U 179 } 180 181 // simp/compTransSelVec(i) is the target simp/comp entry for enq entry [i]. 182 // note that dispatch does not guarantee the validity of enq entries with low index. 183 // that means in some cases enq entry [0] is invalid while enq entry [1] is valid. 184 // in this case, enq entry [1] should use result [0] of TransPolicy. 185 simpTransSelVec.get(0).valid := simpTransPolicy.get.io.enqSelOHVec(0).valid && validVec(0) 186 simpTransSelVec.get(0).bits := simpTransPolicy.get.io.enqSelOHVec(0).bits 187 compTransSelVec.get(0).valid := compTransPolicy.get.io.enqSelOHVec(0).valid && validVec(0) 188 compTransSelVec.get(0).bits := compTransPolicy.get.io.enqSelOHVec(0).bits 189 if (params.numEnq == 2) { 190 simpTransSelVec.get(1).valid := Mux(!validVec(0), simpTransPolicy.get.io.enqSelOHVec(0).valid, simpTransPolicy.get.io.enqSelOHVec(1).valid) 191 simpTransSelVec.get(1).bits := Mux(!validVec(0), simpTransPolicy.get.io.enqSelOHVec(0).bits, simpTransPolicy.get.io.enqSelOHVec(1).bits) 192 compTransSelVec.get(1).valid := Mux(!validVec(0), compTransPolicy.get.io.enqSelOHVec(0).valid, compTransPolicy.get.io.enqSelOHVec(1).valid) 193 compTransSelVec.get(1).bits := Mux(!validVec(0), compTransPolicy.get.io.enqSelOHVec(0).bits, compTransPolicy.get.io.enqSelOHVec(1).bits) 194 } 195 196 finalSimpTransSelVec.get.zip(simpTransSelVec.get).zipWithIndex.foreach { case ((finalOH, selOH), enqIdx) => 197 finalOH := Fill(SimpEntryNum, enqCanTrans2Simp.get && selOH.valid) & selOH.bits 198 } 199 finalCompTransSelVec.get.zip(compTransSelVec.get).zip(compTransPolicy.get.io.enqSelOHVec).zipWithIndex.foreach { 200 case (((finalOH, selOH), origSelOH), enqIdx) => 201 finalOH := Mux(enqCanTrans2Comp.get, Fill(CompEntryNum, selOH.valid) & selOH.bits, Fill(CompEntryNum, origSelOH.valid) & origSelOH.bits) 202 } 203 204 //othersEntryEnq 205 simpEntryEnqVec.zipWithIndex.foreach { case (simpEntryEnq, simpIdx) => 206 val simpEnqOH = finalSimpTransSelVec.get.map(_(simpIdx)) 207 // shit Mux1H directly returns in(0) if the seq has only 1 elements 208 if (simpEnqOH.size == 1) 209 simpEntryEnq := Mux(simpEnqOH.head, enqEntryTransVec.head, 0.U.asTypeOf(enqEntryTransVec.head)) 210 else 211 simpEntryEnq := Mux1H(simpEnqOH, enqEntryTransVec) 212 } 213 214 compEnqVec.get.zip(enqEntryTransVec).zip(io.simpEntryDeqSelVec.get).foreach { case ((compEnq, enqEntry), deqSel) => 215 compEnq := Mux(enqCanTrans2Comp.get, enqEntry, Mux1H(deqSel, simpEntryTransVec.get)) 216 } 217 compEntryEnqVec.zipWithIndex.foreach { case (compEntryEnq, compIdx) => 218 val compEnqOH = finalCompTransSelVec.get.map(_(compIdx)) 219 // shit Mux1H directly returns in(0) if the seq has only 1 elements 220 if (compEnqOH.size == 1) 221 compEntryEnq := Mux(compEnqOH.head, compEnqVec.get.head, 0.U.asTypeOf(compEnqVec.get.head)) 222 else 223 compEntryEnq := Mux1H(compEnqOH, compEnqVec.get) 224 } 225 226 assert(PopCount(simpEntryEnqVec.map(_.valid)) <= params.numEnq.U, "the number of simpEntryEnq is more than numEnq\n") 227 assert(PopCount(compEntryEnqVec.map(_.valid)) <= params.numEnq.U, "the number of compEntryEnq is more than numEnq\n") 228 } 229 230 if(backendParams.debugEn) { 231 dontTouch(othersEntryEnqVec) 232 } 233 234 //issueRespVec 235 if (params.isVecMemIQ) { 236 // vector memory IQ 237 issueRespVec.zip(robIdxVec).zip(uopIdxVec.get).foreach { case ((issueResp, robIdx), uopIdx) => 238 val hitRespsVec = VecInit(resps.flatten.map(x => 239 x.valid && x.bits.robIdx === robIdx && x.bits.uopIdx.get === uopIdx 240 )) 241 issueResp.valid := hitRespsVec.reduce(_ | _) 242 issueResp.bits := Mux1H(hitRespsVec, resps.flatten.map(_.bits)) 243 } 244 } else if (params.isMemAddrIQ) { 245 // scalar memory IQ 246 issueRespVec.zip(robIdxVec).foreach { case (issueResp, robIdx) => 247 val hitRespsVec = VecInit(memEtyResps.map(x => x.valid && (x.bits.robIdx === robIdx)).toSeq) 248 issueResp.valid := hitRespsVec.reduce(_ | _) 249 issueResp.bits := Mux1H(hitRespsVec, memEtyResps.map(_.bits).toSeq) 250 } 251 } 252 else { 253 issueRespVec.zip(issueTimerVec).zip(deqPortIdxReadVec).foreach { case ((issueResp, issueTimer), deqPortIdx) => 254 val Resp = resps(issueTimer)(deqPortIdx) 255 issueResp := Resp 256 } 257 } 258 259 //deq 260 val enqEntryOldest = Wire(Vec(params.numDeq, ValidIO(new EntryBundle))) 261 val simpEntryOldest = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numDeq, ValidIO(new EntryBundle)))) 262 val compEntryOldest = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numDeq, ValidIO(new EntryBundle)))) 263 val othersEntryOldest = OptionWrapper(params.isAllComp || params.isAllSimp, Wire(Vec(params.numDeq, ValidIO(new EntryBundle)))) 264 val enqEntryOldestCancel = Wire(Vec(params.numDeq, Bool())) 265 val simpEntryOldestCancel = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numDeq, Bool()))) 266 val compEntryOldestCancel = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numDeq, Bool()))) 267 val othersEntryOldestCancel = OptionWrapper(params.isAllComp || params.isAllSimp, Wire(Vec(params.numDeq, Bool()))) 268 269 io.enqEntryOldestSel.zipWithIndex.map { case (sel, deqIdx) => 270 enqEntryOldest(deqIdx) := Mux1H(sel.bits, entries.take(EnqEntryNum)) 271 enqEntryOldestCancel(deqIdx) := Mux1H(sel.bits, cancelBypassVec.take(EnqEntryNum)) 272 } 273 274 if (params.isAllComp || params.isAllSimp) { 275 io.othersEntryOldestSel.get.zipWithIndex.map { case (sel, deqIdx) => 276 othersEntryOldest.get(deqIdx) := Mux1H(sel.bits, entries.drop(EnqEntryNum)) 277 othersEntryOldestCancel.get(deqIdx) := Mux1H(sel.bits, cancelBypassVec.drop(EnqEntryNum)) 278 } 279 } 280 else { 281 io.simpEntryOldestSel.get.zipWithIndex.map { case (sel, deqIdx) => 282 simpEntryOldest.get(deqIdx) := Mux1H(sel.bits, entries.drop(EnqEntryNum).take(SimpEntryNum)) 283 simpEntryOldestCancel.get(deqIdx) := Mux1H(sel.bits, cancelBypassVec.drop(EnqEntryNum).take(SimpEntryNum)) 284 } 285 io.compEntryOldestSel.get.zipWithIndex.map { case (sel, deqIdx) => 286 compEntryOldest.get(deqIdx) := Mux1H(sel.bits, entries.drop(EnqEntryNum).takeRight(CompEntryNum)) 287 compEntryOldestCancel.get(deqIdx) := Mux1H(sel.bits, cancelBypassVec.drop(EnqEntryNum).takeRight(CompEntryNum)) 288 } 289 } 290 291 if (params.deqFuSame) { 292 val subDeqPolicyEntryVec = Wire(Vec(params.numDeq, ValidIO(new EntryBundle))) 293 val subDeqPolicyValidVec = Wire(Vec(params.numDeq, Bool())) 294 val subDeqPolicyCancelBypassVec = Wire(Vec(params.numDeq, Bool())) 295 296 subDeqPolicyValidVec(0) := PopCount(io.subDeqRequest.get(0)) >= 1.U 297 subDeqPolicyValidVec(1) := PopCount(io.subDeqRequest.get(0)) >= 2.U 298 299 if (params.isAllComp || params.isAllSimp) { 300 subDeqPolicyEntryVec(0) := PriorityMux(io.subDeqRequest.get(0), entries) 301 subDeqPolicyEntryVec(1) := PriorityMux(Reverse(io.subDeqRequest.get(0)), entries.reverse) 302 subDeqPolicyCancelBypassVec(0) := PriorityMux(io.subDeqRequest.get(0), cancelBypassVec) 303 subDeqPolicyCancelBypassVec(1) := PriorityMux(Reverse(io.subDeqRequest.get(0)), cancelBypassVec.reverse) 304 305 io.deqEntry(0) := Mux(io.othersEntryOldestSel.get(0).valid, othersEntryOldest.get(0), subDeqPolicyEntryVec(1)) 306 io.deqEntry(1) := subDeqPolicyEntryVec(0) 307 io.cancelDeqVec(0) := Mux(io.othersEntryOldestSel.get(0).valid, othersEntryOldestCancel.get(0), subDeqPolicyCancelBypassVec(1)) 308 io.cancelDeqVec(1) := subDeqPolicyCancelBypassVec(0) 309 } 310 else { 311 subDeqPolicyEntryVec(0) := PriorityMux(Reverse(io.subDeqRequest.get(0)), entries.reverse) 312 subDeqPolicyEntryVec(1) := PriorityMux(io.subDeqRequest.get(0), entries) 313 subDeqPolicyCancelBypassVec(0) := PriorityMux(Reverse(io.subDeqRequest.get(0)), cancelBypassVec.reverse) 314 subDeqPolicyCancelBypassVec(1) := PriorityMux(io.subDeqRequest.get(0), cancelBypassVec) 315 316 io.deqEntry(0) := Mux(io.compEntryOldestSel.get(0).valid, 317 compEntryOldest.get(0), 318 Mux(io.simpEntryOldestSel.get(0).valid, simpEntryOldest.get(0), subDeqPolicyEntryVec(1))) 319 io.deqEntry(1) := subDeqPolicyEntryVec(0) 320 io.cancelDeqVec(0) := Mux(io.compEntryOldestSel.get(0).valid, 321 compEntryOldestCancel.get(0), 322 Mux(io.simpEntryOldestSel.get(0).valid, simpEntryOldestCancel.get(0), subDeqPolicyCancelBypassVec(1))) 323 io.cancelDeqVec(1) := subDeqPolicyCancelBypassVec(0) 324 } 325 326 when (subDeqPolicyValidVec(0)) { 327 assert(Mux1H(io.subDeqSelOH.get(0), entries).bits.status.robIdx === subDeqPolicyEntryVec(0).bits.status.robIdx, "subDeqSelOH(0) is not the same\n") 328 } 329 when (subDeqPolicyValidVec(1)) { 330 assert(Mux1H(io.subDeqSelOH.get(1), entries).bits.status.robIdx === subDeqPolicyEntryVec(1).bits.status.robIdx, "subDeqSelOH(1) is not the same\n") 331 } 332 } 333 else { 334 if (params.isAllComp || params.isAllSimp) { 335 io.othersEntryOldestSel.get.zipWithIndex.foreach { case (sel, i) => 336 io.deqEntry(i) := Mux(sel.valid, othersEntryOldest.get(i), enqEntryOldest(i)) 337 io.cancelDeqVec(i) := Mux(sel.valid, othersEntryOldestCancel.get(i), enqEntryOldestCancel(i)) 338 } 339 } 340 else { 341 io.compEntryOldestSel.get.zip(io.simpEntryOldestSel.get).zipWithIndex.foreach { case ((compSel, simpSel), i) => 342 io.deqEntry(i) := Mux(compSel.valid, 343 compEntryOldest.get(i), 344 Mux(simpSel.valid, simpEntryOldest.get(i), enqEntryOldest(i))) 345 io.cancelDeqVec(i) := Mux(compSel.valid, 346 compEntryOldestCancel.get(i), 347 Mux(simpSel.valid, simpEntryOldestCancel.get(i), enqEntryOldestCancel(i))) 348 } 349 } 350 } 351 352 if (params.hasIQWakeUp) { 353 cancelBypassVec.zip(srcWakeUpL1ExuOHVec.get).zip(srcTimerVec.get).zip(srcLoadDependencyVec).foreach{ case (((cancelBypass: Bool, l1ExuOH: Vec[Vec[Bool]]), srcTimer: Vec[UInt]), srcLoadDependency: Vec[Vec[UInt]]) => 354 val cancelByOg0 = l1ExuOH.zip(srcTimer).map { 355 case(exuOH, srcTimer) => 356 (exuOH.asUInt & io.og0Cancel.asUInt).orR && srcTimer === 1.U 357 }.reduce(_ | _) 358 val cancelByLd = srcLoadDependency.map(x => LoadShouldCancel(Some(x), io.ldCancel)).reduce(_ | _) 359 cancelBypass := cancelByLd 360 } 361 } else { 362 cancelBypassVec.zip(srcLoadDependencyVec).foreach { case (cancelBypass, srcLoadDependency) => 363 val cancelByLd = srcLoadDependency.map(x => LoadShouldCancel(Some(x), io.ldCancel)).reduce(_ | _) 364 cancelBypass := cancelByLd 365 } 366 } 367 368 io.valid := validVec.asUInt 369 io.canIssue := canIssueVec.asUInt 370 io.fuType := fuTypeVec 371 io.dataSources := dataSourceVec 372 io.srcWakeUpL1ExuOH.foreach(_ := srcWakeUpL1ExuOHVec.get.map(x => VecInit(x.map(_.asUInt)))) 373 io.srcTimer.foreach(_ := srcTimerVec.get) 374 io.loadDependency := loadDependencyVec 375 io.isFirstIssue.zipWithIndex.foreach{ case (isFirstIssue, deqIdx) => 376 isFirstIssue := io.deqSelOH(deqIdx).valid && Mux1H(io.deqSelOH(deqIdx).bits, isFirstIssueVec) 377 } 378 io.simpEntryEnqSelVec.foreach(_ := finalSimpTransSelVec.get.zip(enqEntryTransVec).map(x => x._1 & Fill(SimpEntryNum, x._2.valid))) 379 io.compEntryEnqSelVec.foreach(_ := finalCompTransSelVec.get.zip(compEnqVec.get).map(x => x._1 & Fill(CompEntryNum, x._2.valid))) 380 io.othersEntryEnqSelVec.foreach(_ := finalOthersTransSelVec.get.zip(enqEntryTransVec).map(x => x._1 & Fill(OthersEntryNum, x._2.valid))) 381 io.robIdx.foreach(_ := robIdxVec) 382 io.uopIdx.foreach(_ := uopIdxVec.get) 383 io.cancel.foreach(_ := cancelVec.get) //for debug 384 385 def EntriesConnect(in: CommonInBundle, out: CommonOutBundle, entryIdx: Int) = { 386 in.flush := io.flush 387 in.wakeUpFromWB := io.wakeUpFromWB 388 in.wakeUpFromIQ := io.wakeUpFromIQ 389 in.og0Cancel := io.og0Cancel 390 in.og1Cancel := io.og1Cancel 391 in.ldCancel := io.ldCancel 392 in.deqSel := deqSelVec(entryIdx) 393 in.deqPortIdxWrite := deqPortIdxWriteVec(entryIdx) 394 in.issueResp := issueRespVec(entryIdx) 395 if (params.isVecMemIQ) { 396 in.fromLsq.get.sqDeqPtr := io.vecMemIn.get.sqDeqPtr 397 in.fromLsq.get.lqDeqPtr := io.vecMemIn.get.lqDeqPtr 398 } 399 validVec(entryIdx) := out.valid 400 canIssueVec(entryIdx) := out.canIssue 401 fuTypeVec(entryIdx) := out.fuType 402 robIdxVec(entryIdx) := out.robIdx 403 dataSourceVec(entryIdx) := out.dataSource 404 isFirstIssueVec(entryIdx) := out.isFirstIssue 405 entries(entryIdx) := out.entry 406 deqPortIdxReadVec(entryIdx) := out.deqPortIdxRead 407 issueTimerVec(entryIdx) := out.issueTimerRead 408 srcLoadDependencyVec(entryIdx) := out.srcLoadDependency 409 loadDependencyVec(entryIdx) := out.entry.bits.status.mergedLoadDependency 410 if (params.hasIQWakeUp) { 411 srcWakeUpL1ExuOHVec.get(entryIdx) := out.srcWakeUpL1ExuOH.get 412 srcTimerVec.get(entryIdx) := out.srcTimer.get 413 cancelVec.get(entryIdx) := out.cancel.get 414 } 415 if (params.isVecMemIQ) { 416 uopIdxVec.get(entryIdx) := out.uopIdx.get 417 } 418 entryInValidVec(entryIdx) := out.entryInValid 419 entryOutDeqValidVec(entryIdx) := out.entryOutDeqValid 420 entryOutTransValidVec(entryIdx) := out.entryOutTransValid 421 } 422 423 // entries perf counter 424 // enq 425 for (i <- 0 until params.numEnq) { 426 XSPerfAccumulate(s"enqEntry_${i}_in_cnt", entryInValidVec(i)) 427 XSPerfAccumulate(s"enqEntry_${i}_out_deq_cnt", entryOutDeqValidVec(i)) 428 XSPerfAccumulate(s"enqEntry_${i}_out_trans_cnt", entryOutTransValidVec(i)) 429 } 430 // simple 431 for (i <- 0 until params.numSimp) { 432 XSPerfAccumulate(s"simpEntry_${i}_in_cnt", entryInValidVec(i + params.numEnq)) 433 XSPerfAccumulate(s"simpEntry_${i}_out_deq_cnt", entryOutDeqValidVec(i + params.numEnq)) 434 XSPerfAccumulate(s"simpEntry_${i}_out_trans_cnt", entryOutTransValidVec(i + params.numEnq)) 435 } 436 // complex 437 for (i <- 0 until params.numComp) { 438 XSPerfAccumulate(s"compEntry_${i}_in_cnt", entryInValidVec(i + params.numEnq + params.numSimp)) 439 XSPerfAccumulate(s"compEntry_${i}_out_deq_cnt", entryOutDeqValidVec(i + params.numEnq + params.numSimp)) 440 XSPerfAccumulate(s"compEntry_${i}_out_trans_cnt", entryOutTransValidVec(i + params.numEnq + params.numSimp)) 441 } 442 // total 443 XSPerfAccumulate(s"enqEntry_all_in_cnt", PopCount(entryInValidVec.take(params.numEnq))) 444 XSPerfAccumulate(s"enqEntry_all_out_deq_cnt", PopCount(entryOutDeqValidVec.take(params.numEnq))) 445 XSPerfAccumulate(s"enqEntry_all_out_trans_cnt", PopCount(entryOutTransValidVec.take(params.numEnq))) 446 447 XSPerfAccumulate(s"othersEntry_all_in_cnt", PopCount(entryInValidVec.drop(params.numEnq))) 448 XSPerfAccumulate(s"othersEntry_all_out_deq_cnt", PopCount(entryOutDeqValidVec.drop(params.numEnq))) 449 XSPerfAccumulate(s"othersEntry_all_out_trans_cnt", PopCount(entryOutTransValidVec.drop(params.numEnq))) 450} 451 452class EntriesIO(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 453 val flush = Flipped(ValidIO(new Redirect)) 454 //enq 455 val enq = Vec(params.numEnq, Flipped(ValidIO(new EntryBundle))) 456 val og0Resp = Vec(params.numDeq, Flipped(ValidIO(new EntryDeqRespBundle))) 457 val og1Resp = Vec(params.numDeq, Flipped(ValidIO(new EntryDeqRespBundle))) 458 //deq sel 459 val deqReady = Vec(params.numDeq, Input(Bool())) 460 val deqSelOH = Vec(params.numDeq, Flipped(ValidIO(UInt(params.numEntries.W)))) 461 val enqEntryOldestSel = Vec(params.numDeq, Flipped(ValidIO(UInt(params.numEnq.W)))) 462 val simpEntryOldestSel = OptionWrapper(params.hasCompAndSimp, Vec(params.numDeq, Flipped(ValidIO(UInt(params.numSimp.W))))) 463 val compEntryOldestSel = OptionWrapper(params.hasCompAndSimp, Vec(params.numDeq, Flipped(ValidIO(UInt(params.numComp.W))))) 464 val othersEntryOldestSel= OptionWrapper(params.isAllComp || params.isAllSimp, Vec(params.numDeq, Flipped(ValidIO(UInt((params.numEntries - params.numEnq).W))))) 465 val subDeqRequest = OptionWrapper(params.deqFuSame, Vec(params.numDeq, Input(UInt(params.numEntries.W)))) 466 val subDeqSelOH = OptionWrapper(params.deqFuSame, Vec(params.numDeq, Input(UInt(params.numEntries.W)))) 467 // wakeup 468 val wakeUpFromWB: MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = Flipped(params.genWBWakeUpSinkValidBundle) 469 val wakeUpFromIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(params.genIQWakeUpSinkValidBundle) 470 val og0Cancel = Input(ExuOH(backendParams.numExu)) 471 val og1Cancel = Input(ExuOH(backendParams.numExu)) 472 val ldCancel = Vec(backendParams.LdExuCnt, Flipped(new LoadCancelIO)) 473 //entries status 474 val valid = Output(UInt(params.numEntries.W)) 475 val canIssue = Output(UInt(params.numEntries.W)) 476 val fuType = Vec(params.numEntries, Output(FuType())) 477 val dataSources = Vec(params.numEntries, Vec(params.numRegSrc, Output(DataSource()))) 478 val loadDependency = Vec(params.numEntries, Vec(LoadPipelineWidth, UInt(3.W))) 479 val srcWakeUpL1ExuOH = OptionWrapper(params.hasIQWakeUp, Vec(params.numEntries, Vec(params.numRegSrc, Output(ExuOH())))) 480 val srcTimer = OptionWrapper(params.hasIQWakeUp, Vec(params.numEntries, Vec(params.numRegSrc, Output(UInt(3.W))))) 481 //deq status 482 val isFirstIssue = Vec(params.numDeq, Output(Bool())) 483 val deqEntry = Vec(params.numDeq, ValidIO(new EntryBundle)) 484 val cancelDeqVec = Vec(params.numDeq, Output(Bool())) 485 486 // load/hybird only 487 val fromLoad = OptionWrapper(params.isLdAddrIQ || params.isHyAddrIQ, new Bundle { 488 val finalIssueResp = Vec(params.numDeq, Flipped(ValidIO(new EntryDeqRespBundle))) 489 val memAddrIssueResp = Vec(params.numDeq, Flipped(ValidIO(new EntryDeqRespBundle))) 490 }) 491 // mem only 492 val fromMem = OptionWrapper(params.isMemAddrIQ, new Bundle { 493 val slowResp = Vec(params.numDeq, Flipped(ValidIO(new EntryDeqRespBundle))) 494 val fastResp = Vec(params.numDeq, Flipped(ValidIO(new EntryDeqRespBundle))) 495 }) 496 // vec mem only 497 val vecMemIn = OptionWrapper(params.isVecMemIQ, new Bundle { 498 val sqDeqPtr = Input(new SqPtr) 499 val lqDeqPtr = Input(new LqPtr) 500 }) 501 val robIdx = OptionWrapper(params.isVecMemIQ, Output(Vec(params.numEntries, new RobPtr))) 502 val uopIdx = OptionWrapper(params.isVecMemIQ, Output(Vec(params.numEntries, UopIdx()))) 503 504 // trans 505 val simpEntryDeqSelVec = OptionWrapper(params.hasCompAndSimp, Vec(params.numEnq, Input(UInt(params.numSimp.W)))) 506 val simpEntryEnqSelVec = OptionWrapper(params.hasCompAndSimp, Vec(params.numEnq, Output(UInt(params.numSimp.W)))) 507 val compEntryEnqSelVec = OptionWrapper(params.hasCompAndSimp, Vec(params.numEnq, Output(UInt(params.numComp.W)))) 508 val othersEntryEnqSelVec = OptionWrapper(params.isAllComp || params.isAllSimp, Vec(params.numEnq, Output(UInt((params.numEntries - params.numEnq).W)))) 509 510 // debug 511 val cancel = OptionWrapper(params.hasIQWakeUp, Output(Vec(params.numEntries, Bool()))) 512 513 def wakeup = wakeUpFromWB ++ wakeUpFromIQ 514} 515