1package xiangshan.backend.issue 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import utility.HasCircularQueuePtrHelper 7import utils._ 8import utility._ 9import xiangshan._ 10import xiangshan.backend.Bundles._ 11import xiangshan.backend.datapath.DataConfig.VAddrData 12import xiangshan.backend.datapath.DataSource 13import xiangshan.backend.fu.FuType 14import xiangshan.backend.fu.vector.Utils.NOnes 15import xiangshan.backend.rob.RobPtr 16import xiangshan.mem.{LqPtr, MemWaitUpdateReq, SqPtr} 17import xiangshan.backend.issue.EntryBundles._ 18 19class Entries(implicit p: Parameters, params: IssueBlockParams) extends XSModule { 20 override def desiredName: String = params.getEntryName 21 22 require(params.numEnq <= 2, "number of enq should be no more than 2") 23 24 private val EnqEntryNum = params.numEnq 25 private val OthersEntryNum = params.numEntries - params.numEnq 26 private val SimpEntryNum = params.numSimp 27 private val CompEntryNum = params.numComp 28 val io = IO(new EntriesIO) 29 30 // only memAddrIQ use it 31 val memEtyResps: MixedVec[ValidIO[EntryDeqRespBundle]] = { 32 if (params.isLdAddrIQ && !params.isStAddrIQ) //LDU 33 MixedVecInit(io.og0Resp ++ io.og1Resp ++ io.fromLoad.get.finalIssueResp ++ io.fromLoad.get.memAddrIssueResp) 34 else if (params.isLdAddrIQ && params.isStAddrIQ || params.isHyAddrIQ) //HYU 35 MixedVecInit(io.og0Resp ++ io.og1Resp ++ io.fromLoad.get.finalIssueResp ++ io.fromLoad.get.memAddrIssueResp ++ io.fromMem.get.fastResp ++ io.fromMem.get.slowResp) 36 else if (params.isMemAddrIQ) //STU, VLDU, VSTU 37 MixedVecInit(io.og0Resp ++ io.og1Resp ++ io.fromMem.get.slowResp) 38 else MixedVecInit(Seq()) 39 } 40 41 val resps: Vec[Vec[ValidIO[EntryDeqRespBundle]]] = { 42 if (params.inVfSchd) 43 VecInit(io.og0Resp, io.og1Resp, io.og2Resp.get, 0.U.asTypeOf(io.og0Resp)) 44 else 45 VecInit(io.og0Resp, io.og1Resp, 0.U.asTypeOf(io.og0Resp), 0.U.asTypeOf(io.og0Resp)) 46 } 47 48 //Module 49 val enqEntries = Seq.fill(EnqEntryNum)(Module(EnqEntry(isComp = true)(p, params))) 50 val othersEntriesSimp = Seq.fill(SimpEntryNum)(Module(OthersEntry(isComp = false)(p, params))) 51 val othersEntriesComp = Seq.fill(CompEntryNum)(Module(OthersEntry(isComp = true)(p, params))) 52 val othersEntries = othersEntriesSimp ++ othersEntriesComp 53 val othersTransPolicy = OptionWrapper(params.isAllComp || params.isAllSimp, Module(new EnqPolicy)) 54 val simpTransPolicy = OptionWrapper(params.hasCompAndSimp, Module(new EnqPolicy)) 55 val compTransPolicy = OptionWrapper(params.hasCompAndSimp, Module(new EnqPolicy)) 56 57 //Wire 58 //entries status 59 val entries = Wire(Vec(params.numEntries, ValidIO(new EntryBundle))) 60 val robIdxVec = Wire(Vec(params.numEntries, new RobPtr)) 61 val validVec = Wire(Vec(params.numEntries, Bool())) 62 val canIssueVec = Wire(Vec(params.numEntries, Bool())) 63 val fuTypeVec = Wire(Vec(params.numEntries, FuType())) 64 val isFirstIssueVec = Wire(Vec(params.numEntries, Bool())) 65 val issueTimerVec = Wire(Vec(params.numEntries, UInt(2.W))) 66 val uopIdxVec = OptionWrapper(params.isVecMemIQ, Wire(Vec(params.numEntries, UopIdx()))) 67 //src status 68 val dataSourceVec = Wire(Vec(params.numEntries, Vec(params.numRegSrc, DataSource()))) 69 val loadDependencyVec = Wire(Vec(params.numEntries, Vec(LoadPipelineWidth, UInt(3.W)))) 70 val srcLoadDependencyVec= Wire(Vec(params.numEntries, Vec(params.numRegSrc, Vec(LoadPipelineWidth, UInt(3.W))))) 71 val srcWakeUpL1ExuOHVec = OptionWrapper(params.hasIQWakeUp, Wire(Vec(params.numEntries, Vec(params.numRegSrc, ExuVec())))) 72 //deq sel 73 val deqSelVec = Wire(Vec(params.numEntries, Bool())) 74 val issueRespVec = Wire(Vec(params.numEntries, ValidIO(new EntryDeqRespBundle))) 75 val deqPortIdxWriteVec = Wire(Vec(params.numEntries, UInt(1.W))) 76 val deqPortIdxReadVec = Wire(Vec(params.numEntries, UInt(1.W))) 77 //trans sel 78 val othersEntryEnqReadyVec = Wire(Vec(OthersEntryNum, Bool())) 79 val othersEntryEnqVec = Wire(Vec(OthersEntryNum, Valid(new EntryBundle))) 80 val enqEntryTransVec = Wire(Vec(EnqEntryNum, Valid(new EntryBundle))) 81 val simpEntryTransVec = OptionWrapper(params.hasCompAndSimp, Wire(Vec(SimpEntryNum, Valid(new EntryBundle)))) 82 val compEnqVec = OptionWrapper(params.hasCompAndSimp, Wire(Vec(EnqEntryNum, Valid(new EntryBundle)))) 83 84 val enqCanTrans2Simp = OptionWrapper(params.hasCompAndSimp, Wire(Bool())) 85 val enqCanTrans2Comp = OptionWrapper(params.hasCompAndSimp, Wire(Bool())) 86 val simpCanTrans2Comp = OptionWrapper(params.hasCompAndSimp, Wire(Vec(EnqEntryNum, Bool()))) 87 val simpTransSelVec = OptionWrapper(params.hasCompAndSimp, Wire(Vec(EnqEntryNum, Valid(UInt(SimpEntryNum.W))))) 88 val compTransSelVec = OptionWrapper(params.hasCompAndSimp, Wire(Vec(EnqEntryNum, Valid(UInt(CompEntryNum.W))))) 89 val finalSimpTransSelVec = OptionWrapper(params.hasCompAndSimp, Wire(Vec(EnqEntryNum, UInt(SimpEntryNum.W)))) 90 val finalCompTransSelVec = OptionWrapper(params.hasCompAndSimp, Wire(Vec(EnqEntryNum, UInt(CompEntryNum.W)))) 91 92 val enqCanTrans2Others = OptionWrapper(params.isAllComp || params.isAllSimp, Wire(Bool())) 93 val othersTransSelVec = OptionWrapper(params.isAllComp || params.isAllSimp, Wire(Vec(EnqEntryNum, Valid(UInt(OthersEntryNum.W))))) 94 val finalOthersTransSelVec = OptionWrapper(params.isAllComp || params.isAllSimp, Wire(Vec(EnqEntryNum, UInt(OthersEntryNum.W)))) 95 96 val simpEntryEnqReadyVec = othersEntryEnqReadyVec.take(SimpEntryNum) 97 val compEntryEnqReadyVec = othersEntryEnqReadyVec.takeRight(CompEntryNum) 98 val simpEntryEnqVec = othersEntryEnqVec.take(SimpEntryNum) 99 val compEntryEnqVec = othersEntryEnqVec.takeRight(CompEntryNum) 100 //debug 101 val entryInValidVec = Wire(Vec(params.numEntries, Bool())) 102 val entryOutDeqValidVec = Wire(Vec(params.numEntries, Bool())) 103 val entryOutTransValidVec = Wire(Vec(params.numEntries, Bool())) 104 val perfLdCancelVec = OptionWrapper(params.hasIQWakeUp, Wire(Vec(params.numEntries, Vec(params.numRegSrc, Bool())))) 105 val perfOg0CancelVec = OptionWrapper(params.hasIQWakeUp, Wire(Vec(params.numEntries, Vec(params.numRegSrc, Bool())))) 106 val perfWakeupByWBVec = Wire(Vec(params.numEntries, Vec(params.numRegSrc, Bool()))) 107 val perfWakeupByIQVec = OptionWrapper(params.hasIQWakeUp, Wire(Vec(params.numEntries, Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool()))))) 108 //cancel bypass 109 val cancelBypassVec = Wire(Vec(params.numEntries, Bool())) 110 111 112 //enqEntries 113 enqEntries.zipWithIndex.foreach { case (enqEntry, entryIdx) => 114 enqEntry.io.commonIn.enq := io.enq(entryIdx) 115 enqEntry.io.commonIn.transSel := (if (params.isAllComp || params.isAllSimp) enqCanTrans2Others.get && othersTransSelVec.get(entryIdx).valid 116 else enqCanTrans2Simp.get && simpTransSelVec.get(entryIdx).valid || enqCanTrans2Comp.get && compTransSelVec.get(entryIdx).valid) 117 EntriesConnect(enqEntry.io.commonIn, enqEntry.io.commonOut, entryIdx) 118 enqEntry.io.enqDelayIn1.wakeUpFromWB := RegEnable(io.wakeUpFromWB, io.enq(entryIdx).valid) 119 enqEntry.io.enqDelayIn1.wakeUpFromIQ := RegEnable(io.wakeUpFromIQ, io.enq(entryIdx).valid) 120 enqEntry.io.enqDelayIn1.og0Cancel := RegNext(io.og0Cancel.asUInt) 121 enqEntry.io.enqDelayIn1.ldCancel := RegNext(io.ldCancel) 122 // note: these signals with 2 cycle delay should not be enabled by io.enq.valid 123 enqEntry.io.enqDelayIn2.wakeUpFromWB := DelayN(io.wakeUpFromWB, 2) 124 enqEntry.io.enqDelayIn2.wakeUpFromIQ := DelayN(io.wakeUpFromIQ, 2) 125 enqEntry.io.enqDelayIn2.og0Cancel := DelayN(io.og0Cancel.asUInt, 2) 126 enqEntry.io.enqDelayIn2.ldCancel := DelayN(io.ldCancel, 2) 127 enqEntryTransVec(entryIdx) := enqEntry.io.commonOut.transEntry 128 } 129 //othersEntries 130 othersEntries.zipWithIndex.foreach { case (othersEntry, entryIdx) => 131 othersEntry.io.commonIn.enq := othersEntryEnqVec(entryIdx) 132 othersEntry.io.commonIn.transSel := (if (params.hasCompAndSimp && (entryIdx < SimpEntryNum)) 133 io.simpEntryDeqSelVec.get.zip(simpCanTrans2Comp.get).map(x => x._1(entryIdx) && x._2).reduce(_ | _) 134 else false.B) 135 EntriesConnect(othersEntry.io.commonIn, othersEntry.io.commonOut, entryIdx + EnqEntryNum) 136 othersEntryEnqReadyVec(entryIdx) := othersEntry.io.commonOut.enqReady 137 if (params.hasCompAndSimp && (entryIdx < SimpEntryNum)) { 138 simpEntryTransVec.get(entryIdx) := othersEntry.io.commonOut.transEntry 139 } 140 } 141 142 143 deqSelVec.zip(deqPortIdxWriteVec).zipWithIndex.foreach { case ((deqSel, deqPortIdxWrite), i) => 144 val deqVec = io.deqSelOH.zip(io.deqReady).map(x => x._1.valid && x._1.bits(i) && x._2) 145 deqPortIdxWrite := OHToUInt(deqVec) 146 deqSel := deqVec.reduce(_ | _) 147 } 148 149 150 if (params.isAllComp || params.isAllSimp) { 151 //transPolicy 152 othersTransPolicy.get.io.canEnq := othersEntryEnqReadyVec.asUInt 153 154 // we only allow all or none of the enq entries transfering to others entries. 155 enqCanTrans2Others.get := PopCount(validVec.take(EnqEntryNum)) <= PopCount(othersEntryEnqReadyVec) 156 // othersTransSelVec(i) is the target others entry for enq entry [i]. 157 // note that dispatch does not guarantee the validity of enq entries with low index. 158 // that means in some cases enq entry [0] is invalid while enq entry [1] is valid. 159 // in this case, enq entry [1] should use result [0] of TransPolicy. 160 othersTransSelVec.get(0).valid := othersTransPolicy.get.io.enqSelOHVec(0).valid && validVec(0) 161 othersTransSelVec.get(0).bits := othersTransPolicy.get.io.enqSelOHVec(0).bits 162 if (params.numEnq == 2) { 163 othersTransSelVec.get(1).valid := Mux(!validVec(0), othersTransPolicy.get.io.enqSelOHVec(0).valid, othersTransPolicy.get.io.enqSelOHVec(1).valid) 164 othersTransSelVec.get(1).bits := Mux(!validVec(0), othersTransPolicy.get.io.enqSelOHVec(0).bits, othersTransPolicy.get.io.enqSelOHVec(1).bits) 165 } 166 167 finalOthersTransSelVec.get.zip(othersTransSelVec.get).zipWithIndex.foreach { case ((finalOH, selOH), enqIdx) => 168 finalOH := Fill(OthersEntryNum, enqCanTrans2Others.get && selOH.valid) & selOH.bits 169 } 170 171 //othersEntryEnq 172 othersEntryEnqVec.zipWithIndex.foreach { case (othersEntryEnq, othersIdx) => 173 val othersEnqOH = finalOthersTransSelVec.get.map(_(othersIdx)) 174 if (othersEnqOH.size == 1) 175 othersEntryEnq := Mux(othersEnqOH.head, enqEntryTransVec.head, 0.U.asTypeOf(enqEntryTransVec.head)) 176 else 177 othersEntryEnq := Mux1H(othersEnqOH, enqEntryTransVec) 178 } 179 } 180 else { 181 //transPolicy 182 simpTransPolicy.get.io.canEnq := VecInit(simpEntryEnqReadyVec).asUInt 183 compTransPolicy.get.io.canEnq := VecInit(validVec.takeRight(CompEntryNum).map(!_)).asUInt 184 185 // we only allow all or none of the enq entries transfering to comp/simp entries. 186 // when all of simp entries are empty and comp entries are enough, transfer to comp entries. 187 // otherwise, transfer to simp entries. 188 enqCanTrans2Comp.get := PopCount(validVec.take(EnqEntryNum)) <= PopCount(validVec.takeRight(CompEntryNum).map(!_)) && !validVec.drop(EnqEntryNum).take(SimpEntryNum).reduce(_ || _) 189 enqCanTrans2Simp.get := !enqCanTrans2Comp.get && PopCount(validVec.take(EnqEntryNum)) <= PopCount(simpEntryEnqReadyVec) 190 simpCanTrans2Comp.get.zipWithIndex.foreach { case (canTrans, idx) => 191 canTrans := !enqCanTrans2Comp.get && PopCount(validVec.takeRight(CompEntryNum).map(!_)) >= (idx + 1).U 192 } 193 194 // simp/compTransSelVec(i) is the target simp/comp entry for enq entry [i]. 195 // note that dispatch does not guarantee the validity of enq entries with low index. 196 // that means in some cases enq entry [0] is invalid while enq entry [1] is valid. 197 // in this case, enq entry [1] should use result [0] of TransPolicy. 198 simpTransSelVec.get(0).valid := simpTransPolicy.get.io.enqSelOHVec(0).valid && validVec(0) 199 simpTransSelVec.get(0).bits := simpTransPolicy.get.io.enqSelOHVec(0).bits 200 compTransSelVec.get(0).valid := compTransPolicy.get.io.enqSelOHVec(0).valid && validVec(0) 201 compTransSelVec.get(0).bits := compTransPolicy.get.io.enqSelOHVec(0).bits 202 if (params.numEnq == 2) { 203 simpTransSelVec.get(1).valid := Mux(!validVec(0), simpTransPolicy.get.io.enqSelOHVec(0).valid, simpTransPolicy.get.io.enqSelOHVec(1).valid) 204 simpTransSelVec.get(1).bits := Mux(!validVec(0), simpTransPolicy.get.io.enqSelOHVec(0).bits, simpTransPolicy.get.io.enqSelOHVec(1).bits) 205 compTransSelVec.get(1).valid := Mux(!validVec(0), compTransPolicy.get.io.enqSelOHVec(0).valid, compTransPolicy.get.io.enqSelOHVec(1).valid) 206 compTransSelVec.get(1).bits := Mux(!validVec(0), compTransPolicy.get.io.enqSelOHVec(0).bits, compTransPolicy.get.io.enqSelOHVec(1).bits) 207 } 208 209 finalSimpTransSelVec.get.zip(simpTransSelVec.get).zipWithIndex.foreach { case ((finalOH, selOH), enqIdx) => 210 finalOH := Fill(SimpEntryNum, enqCanTrans2Simp.get && selOH.valid) & selOH.bits 211 } 212 finalCompTransSelVec.get.zip(compTransSelVec.get).zip(compTransPolicy.get.io.enqSelOHVec).zipWithIndex.foreach { 213 case (((finalOH, selOH), origSelOH), enqIdx) => 214 finalOH := Mux(enqCanTrans2Comp.get, Fill(CompEntryNum, selOH.valid) & selOH.bits, Fill(CompEntryNum, origSelOH.valid) & origSelOH.bits) 215 } 216 217 //othersEntryEnq 218 simpEntryEnqVec.zipWithIndex.foreach { case (simpEntryEnq, simpIdx) => 219 val simpEnqOH = finalSimpTransSelVec.get.map(_(simpIdx)) 220 // shit Mux1H directly returns in(0) if the seq has only 1 elements 221 if (simpEnqOH.size == 1) 222 simpEntryEnq := Mux(simpEnqOH.head, enqEntryTransVec.head, 0.U.asTypeOf(enqEntryTransVec.head)) 223 else 224 simpEntryEnq := Mux1H(simpEnqOH, enqEntryTransVec) 225 } 226 227 compEnqVec.get.zip(enqEntryTransVec).zip(io.simpEntryDeqSelVec.get).foreach { case ((compEnq, enqEntry), deqSel) => 228 compEnq := Mux(enqCanTrans2Comp.get, enqEntry, Mux1H(deqSel, simpEntryTransVec.get)) 229 } 230 compEntryEnqVec.zipWithIndex.foreach { case (compEntryEnq, compIdx) => 231 val compEnqOH = finalCompTransSelVec.get.map(_(compIdx)) 232 // shit Mux1H directly returns in(0) if the seq has only 1 elements 233 if (compEnqOH.size == 1) 234 compEntryEnq := Mux(compEnqOH.head, compEnqVec.get.head, 0.U.asTypeOf(compEnqVec.get.head)) 235 else 236 compEntryEnq := Mux1H(compEnqOH, compEnqVec.get) 237 } 238 239 assert(PopCount(simpEntryEnqVec.map(_.valid)) <= params.numEnq.U, "the number of simpEntryEnq is more than numEnq\n") 240 assert(PopCount(compEntryEnqVec.map(_.valid)) <= params.numEnq.U, "the number of compEntryEnq is more than numEnq\n") 241 } 242 243 if(backendParams.debugEn) { 244 dontTouch(othersEntryEnqVec) 245 } 246 247 //issueRespVec 248 if (params.isVecMemIQ) { 249 // vector memory IQ 250 issueRespVec.zip(robIdxVec).zip(uopIdxVec.get).foreach { case ((issueResp, robIdx), uopIdx) => 251 val hitRespsVec = VecInit(resps.flatten.map(x => 252 x.valid && x.bits.robIdx === robIdx && x.bits.uopIdx.get === uopIdx 253 )) 254 issueResp.valid := hitRespsVec.reduce(_ | _) 255 issueResp.bits := Mux1H(hitRespsVec, resps.flatten.map(_.bits)) 256 } 257 } else if (params.isMemAddrIQ) { 258 // scalar memory IQ 259 issueRespVec.zip(robIdxVec).foreach { case (issueResp, robIdx) => 260 val hitRespsVec = VecInit(memEtyResps.map(x => x.valid && (x.bits.robIdx === robIdx)).toSeq) 261 issueResp.valid := hitRespsVec.reduce(_ | _) 262 issueResp.bits := Mux1H(hitRespsVec, memEtyResps.map(_.bits).toSeq) 263 } 264 } 265 else { 266 issueRespVec.zip(issueTimerVec).zip(deqPortIdxReadVec).foreach { case ((issueResp, issueTimer), deqPortIdx) => 267 val Resp = resps(issueTimer)(deqPortIdx) 268 issueResp := Resp 269 } 270 } 271 272 //deq 273 val enqEntryOldest = Wire(Vec(params.numDeq, ValidIO(new EntryBundle))) 274 val simpEntryOldest = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numDeq, ValidIO(new EntryBundle)))) 275 val compEntryOldest = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numDeq, ValidIO(new EntryBundle)))) 276 val othersEntryOldest = OptionWrapper(params.isAllComp || params.isAllSimp, Wire(Vec(params.numDeq, ValidIO(new EntryBundle)))) 277 val enqEntryOldestCancel = Wire(Vec(params.numDeq, Bool())) 278 val simpEntryOldestCancel = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numDeq, Bool()))) 279 val compEntryOldestCancel = OptionWrapper(params.hasCompAndSimp, Wire(Vec(params.numDeq, Bool()))) 280 val othersEntryOldestCancel = OptionWrapper(params.isAllComp || params.isAllSimp, Wire(Vec(params.numDeq, Bool()))) 281 282 io.enqEntryOldestSel.zipWithIndex.map { case (sel, deqIdx) => 283 enqEntryOldest(deqIdx) := Mux1H(sel.bits, entries.take(EnqEntryNum)) 284 enqEntryOldestCancel(deqIdx) := Mux1H(sel.bits, cancelBypassVec.take(EnqEntryNum)) 285 } 286 287 if (params.isAllComp || params.isAllSimp) { 288 io.othersEntryOldestSel.get.zipWithIndex.map { case (sel, deqIdx) => 289 othersEntryOldest.get(deqIdx) := Mux1H(sel.bits, entries.drop(EnqEntryNum)) 290 othersEntryOldestCancel.get(deqIdx) := Mux1H(sel.bits, cancelBypassVec.drop(EnqEntryNum)) 291 } 292 } 293 else { 294 io.simpEntryOldestSel.get.zipWithIndex.map { case (sel, deqIdx) => 295 simpEntryOldest.get(deqIdx) := Mux1H(sel.bits, entries.drop(EnqEntryNum).take(SimpEntryNum)) 296 simpEntryOldestCancel.get(deqIdx) := Mux1H(sel.bits, cancelBypassVec.drop(EnqEntryNum).take(SimpEntryNum)) 297 } 298 io.compEntryOldestSel.get.zipWithIndex.map { case (sel, deqIdx) => 299 compEntryOldest.get(deqIdx) := Mux1H(sel.bits, entries.drop(EnqEntryNum).takeRight(CompEntryNum)) 300 compEntryOldestCancel.get(deqIdx) := Mux1H(sel.bits, cancelBypassVec.drop(EnqEntryNum).takeRight(CompEntryNum)) 301 } 302 } 303 304 if (params.deqFuSame) { 305 val subDeqPolicyEntryVec = Wire(Vec(params.numDeq, ValidIO(new EntryBundle))) 306 val subDeqPolicyValidVec = Wire(Vec(params.numDeq, Bool())) 307 val subDeqPolicyCancelBypassVec = Wire(Vec(params.numDeq, Bool())) 308 309 subDeqPolicyValidVec(0) := PopCount(io.subDeqRequest.get(0)) >= 1.U 310 subDeqPolicyValidVec(1) := PopCount(io.subDeqRequest.get(0)) >= 2.U 311 312 if (params.isAllComp || params.isAllSimp) { 313 subDeqPolicyEntryVec(0) := PriorityMux(io.subDeqRequest.get(0), entries) 314 subDeqPolicyEntryVec(1) := PriorityMux(Reverse(io.subDeqRequest.get(0)), entries.reverse) 315 subDeqPolicyCancelBypassVec(0) := PriorityMux(io.subDeqRequest.get(0), cancelBypassVec) 316 subDeqPolicyCancelBypassVec(1) := PriorityMux(Reverse(io.subDeqRequest.get(0)), cancelBypassVec.reverse) 317 318 io.deqEntry(0) := Mux(io.othersEntryOldestSel.get(0).valid, othersEntryOldest.get(0), subDeqPolicyEntryVec(1)) 319 io.deqEntry(1) := subDeqPolicyEntryVec(0) 320 io.cancelDeqVec(0) := Mux(io.othersEntryOldestSel.get(0).valid, othersEntryOldestCancel.get(0), subDeqPolicyCancelBypassVec(1)) 321 io.cancelDeqVec(1) := subDeqPolicyCancelBypassVec(0) 322 } 323 else { 324 subDeqPolicyEntryVec(0) := PriorityMux(Reverse(io.subDeqRequest.get(0)), entries.reverse) 325 subDeqPolicyEntryVec(1) := PriorityMux(io.subDeqRequest.get(0), entries) 326 subDeqPolicyCancelBypassVec(0) := PriorityMux(Reverse(io.subDeqRequest.get(0)), cancelBypassVec.reverse) 327 subDeqPolicyCancelBypassVec(1) := PriorityMux(io.subDeqRequest.get(0), cancelBypassVec) 328 329 io.deqEntry(0) := Mux(io.compEntryOldestSel.get(0).valid, 330 compEntryOldest.get(0), 331 Mux(io.simpEntryOldestSel.get(0).valid, simpEntryOldest.get(0), subDeqPolicyEntryVec(1))) 332 io.deqEntry(1) := subDeqPolicyEntryVec(0) 333 io.cancelDeqVec(0) := Mux(io.compEntryOldestSel.get(0).valid, 334 compEntryOldestCancel.get(0), 335 Mux(io.simpEntryOldestSel.get(0).valid, simpEntryOldestCancel.get(0), subDeqPolicyCancelBypassVec(1))) 336 io.cancelDeqVec(1) := subDeqPolicyCancelBypassVec(0) 337 } 338 339 when (subDeqPolicyValidVec(0)) { 340 assert(Mux1H(io.subDeqSelOH.get(0), entries).bits.status.robIdx === subDeqPolicyEntryVec(0).bits.status.robIdx, "subDeqSelOH(0) is not the same\n") 341 } 342 when (subDeqPolicyValidVec(1)) { 343 assert(Mux1H(io.subDeqSelOH.get(1), entries).bits.status.robIdx === subDeqPolicyEntryVec(1).bits.status.robIdx, "subDeqSelOH(1) is not the same\n") 344 } 345 } 346 else { 347 if (params.isAllComp || params.isAllSimp) { 348 io.othersEntryOldestSel.get.zipWithIndex.foreach { case (sel, i) => 349 io.deqEntry(i) := Mux(sel.valid, othersEntryOldest.get(i), enqEntryOldest(i)) 350 io.cancelDeqVec(i) := Mux(sel.valid, othersEntryOldestCancel.get(i), enqEntryOldestCancel(i)) 351 } 352 } 353 else { 354 io.compEntryOldestSel.get.zip(io.simpEntryOldestSel.get).zipWithIndex.foreach { case ((compSel, simpSel), i) => 355 io.deqEntry(i) := Mux(compSel.valid, 356 compEntryOldest.get(i), 357 Mux(simpSel.valid, simpEntryOldest.get(i), enqEntryOldest(i))) 358 io.cancelDeqVec(i) := Mux(compSel.valid, 359 compEntryOldestCancel.get(i), 360 Mux(simpSel.valid, simpEntryOldestCancel.get(i), enqEntryOldestCancel(i))) 361 } 362 } 363 } 364 365 cancelBypassVec.zip(srcLoadDependencyVec).foreach { case (cancelBypass, srcLoadDependency) => 366 val cancelByLd = srcLoadDependency.map(x => LoadShouldCancel(Some(x), io.ldCancel)).reduce(_ | _) 367 cancelBypass := cancelByLd 368 } 369 370 io.valid := validVec.asUInt 371 io.canIssue := canIssueVec.asUInt 372 io.fuType := fuTypeVec 373 io.dataSources := dataSourceVec 374 io.srcWakeUpL1ExuOH.foreach(_ := srcWakeUpL1ExuOHVec.get.map(x => VecInit(x.map(_.asUInt)))) 375 io.loadDependency := loadDependencyVec 376 io.isFirstIssue.zipWithIndex.foreach{ case (isFirstIssue, deqIdx) => 377 isFirstIssue := io.deqSelOH(deqIdx).valid && Mux1H(io.deqSelOH(deqIdx).bits, isFirstIssueVec) 378 } 379 io.simpEntryEnqSelVec.foreach(_ := finalSimpTransSelVec.get.zip(enqEntryTransVec).map(x => x._1 & Fill(SimpEntryNum, x._2.valid))) 380 io.compEntryEnqSelVec.foreach(_ := finalCompTransSelVec.get.zip(compEnqVec.get).map(x => x._1 & Fill(CompEntryNum, x._2.valid))) 381 io.othersEntryEnqSelVec.foreach(_ := finalOthersTransSelVec.get.zip(enqEntryTransVec).map(x => x._1 & Fill(OthersEntryNum, x._2.valid))) 382 io.robIdx.foreach(_ := robIdxVec) 383 io.uopIdx.foreach(_ := uopIdxVec.get) 384 385 def EntriesConnect(in: CommonInBundle, out: CommonOutBundle, entryIdx: Int) = { 386 in.flush := io.flush 387 in.wakeUpFromWB := io.wakeUpFromWB 388 in.wakeUpFromIQ := io.wakeUpFromIQ 389 in.og0Cancel := io.og0Cancel 390 in.og1Cancel := io.og1Cancel 391 in.ldCancel := io.ldCancel 392 in.deqSel := deqSelVec(entryIdx) 393 in.deqPortIdxWrite := deqPortIdxWriteVec(entryIdx) 394 in.issueResp := issueRespVec(entryIdx) 395 if (params.isVecMemIQ) { 396 in.fromLsq.get.sqDeqPtr := io.vecMemIn.get.sqDeqPtr 397 in.fromLsq.get.lqDeqPtr := io.vecMemIn.get.lqDeqPtr 398 } 399 validVec(entryIdx) := out.valid 400 canIssueVec(entryIdx) := out.canIssue 401 fuTypeVec(entryIdx) := out.fuType 402 robIdxVec(entryIdx) := out.robIdx 403 dataSourceVec(entryIdx) := out.dataSource 404 isFirstIssueVec(entryIdx) := out.isFirstIssue 405 entries(entryIdx) := out.entry 406 deqPortIdxReadVec(entryIdx) := out.deqPortIdxRead 407 issueTimerVec(entryIdx) := out.issueTimerRead 408 srcLoadDependencyVec(entryIdx) := out.srcLoadDependency 409 loadDependencyVec(entryIdx) := out.entry.bits.status.mergedLoadDependency 410 if (params.hasIQWakeUp) { 411 srcWakeUpL1ExuOHVec.get(entryIdx) := out.srcWakeUpL1ExuOH.get 412 } 413 if (params.isVecMemIQ) { 414 uopIdxVec.get(entryIdx) := out.uopIdx.get 415 } 416 entryInValidVec(entryIdx) := out.entryInValid 417 entryOutDeqValidVec(entryIdx) := out.entryOutDeqValid 418 entryOutTransValidVec(entryIdx) := out.entryOutTransValid 419 perfWakeupByWBVec(entryIdx) := out.perfWakeupByWB 420 if (params.hasIQWakeUp) { 421 perfLdCancelVec.get(entryIdx) := out.perfLdCancel.get 422 perfOg0CancelVec.get(entryIdx) := out.perfOg0Cancel.get 423 perfWakeupByIQVec.get(entryIdx) := out.perfWakeupByIQ.get 424 } 425 } 426 427 // entries perf counter 428 // enq 429 for (i <- 0 until params.numEnq) { 430 XSPerfAccumulate(s"enqEntry_${i}_in_cnt", entryInValidVec(i)) 431 XSPerfAccumulate(s"enqEntry_${i}_out_deq_cnt", entryOutDeqValidVec(i)) 432 XSPerfAccumulate(s"enqEntry_${i}_out_trans_cnt", entryOutTransValidVec(i)) 433 } 434 // simple 435 for (i <- 0 until params.numSimp) { 436 XSPerfAccumulate(s"simpEntry_${i}_in_cnt", entryInValidVec(i + params.numEnq)) 437 XSPerfAccumulate(s"simpEntry_${i}_out_deq_cnt", entryOutDeqValidVec(i + params.numEnq)) 438 XSPerfAccumulate(s"simpEntry_${i}_out_trans_cnt", entryOutTransValidVec(i + params.numEnq)) 439 } 440 // complex 441 for (i <- 0 until params.numComp) { 442 XSPerfAccumulate(s"compEntry_${i}_in_cnt", entryInValidVec(i + params.numEnq + params.numSimp)) 443 XSPerfAccumulate(s"compEntry_${i}_out_deq_cnt", entryOutDeqValidVec(i + params.numEnq + params.numSimp)) 444 XSPerfAccumulate(s"compEntry_${i}_out_trans_cnt", entryOutTransValidVec(i + params.numEnq + params.numSimp)) 445 } 446 // total 447 XSPerfAccumulate(s"enqEntry_all_in_cnt", PopCount(entryInValidVec.take(params.numEnq))) 448 XSPerfAccumulate(s"enqEntry_all_out_deq_cnt", PopCount(entryOutDeqValidVec.take(params.numEnq))) 449 XSPerfAccumulate(s"enqEntry_all_out_trans_cnt", PopCount(entryOutTransValidVec.take(params.numEnq))) 450 for (srcIdx <- 0 until params.numRegSrc) { 451 XSPerfAccumulate(s"enqEntry_all_wakeup_wb_src${srcIdx}_cnt", PopCount(perfWakeupByWBVec.take(params.numEnq).map(_(srcIdx)))) 452 if (params.hasIQWakeUp) { 453 XSPerfAccumulate(s"enqEntry_all_ldCancel_src${srcIdx}_cnt", PopCount(perfLdCancelVec.get.take(params.numEnq).map(_(srcIdx)))) 454 XSPerfAccumulate(s"enqEntry_all_og0Cancel_src${srcIdx}_cnt", PopCount(perfOg0CancelVec.get.take(params.numEnq).map(_(srcIdx)))) 455 for (iqIdx <- 0 until params.numWakeupFromIQ) { 456 XSPerfAccumulate(s"enqEntry_all_wakeup_iq_from_exu${params.wakeUpSourceExuIdx(iqIdx)}_src${srcIdx}_cnt", PopCount(perfWakeupByIQVec.get.take(params.numEnq).map(_(srcIdx)(iqIdx)))) 457 } 458 } 459 } 460 461 XSPerfAccumulate(s"othersEntry_all_in_cnt", PopCount(entryInValidVec.drop(params.numEnq))) 462 XSPerfAccumulate(s"othersEntry_all_out_deq_cnt", PopCount(entryOutDeqValidVec.drop(params.numEnq))) 463 XSPerfAccumulate(s"othersEntry_all_out_trans_cnt", PopCount(entryOutTransValidVec.drop(params.numEnq))) 464 for (srcIdx <- 0 until params.numRegSrc) { 465 XSPerfAccumulate(s"othersEntry_all_wakeup_wb_src${srcIdx}_cnt", PopCount(perfWakeupByWBVec.drop(params.numEnq).map(_(srcIdx)))) 466 if (params.hasIQWakeUp) { 467 XSPerfAccumulate(s"othersEntry_all_ldCancel_src${srcIdx}_cnt", PopCount(perfLdCancelVec.get.drop(params.numEnq).map(_(srcIdx)))) 468 XSPerfAccumulate(s"othersEntry_all_og0Cancel_src${srcIdx}_cnt", PopCount(perfOg0CancelVec.get.drop(params.numEnq).map(_(srcIdx)))) 469 for (iqIdx <- 0 until params.numWakeupFromIQ) { 470 XSPerfAccumulate(s"othersEntry_all_wakeup_iq_from_exu${params.wakeUpSourceExuIdx(iqIdx)}_src${srcIdx}_cnt", PopCount(perfWakeupByIQVec.get.drop(params.numEnq).map(_(srcIdx)(iqIdx)))) 471 } 472 } 473 } 474 475 for (t <- FuType.functionNameMap.keys) { 476 val fuName = FuType.functionNameMap(t) 477 if (params.getFuCfgs.map(_.fuType == t).reduce(_ | _) && params.getFuCfgs.size > 1) { 478 for (srcIdx <- 0 until params.numRegSrc) { 479 XSPerfAccumulate(s"allEntry_futype_${fuName}_wakeup_wb_src${srcIdx}_cnt", PopCount(perfWakeupByWBVec.zip(fuTypeVec).map{ case(x, fu) => x(srcIdx) && fu(t.id) })) 480 if (params.hasIQWakeUp) { 481 XSPerfAccumulate(s"allEntry_futype_${fuName}_ldCancel_src${srcIdx}_cnt", PopCount(perfLdCancelVec.get.zip(fuTypeVec).map{ case(x, fu) => x(srcIdx) && fu(t.id) })) 482 XSPerfAccumulate(s"allEntry_futype_${fuName}_og0Cancel_src${srcIdx}_cnt", PopCount(perfOg0CancelVec.get.zip(fuTypeVec).map{ case(x, fu) => x(srcIdx) && fu(t.id) })) 483 for (iqIdx <- 0 until params.numWakeupFromIQ) { 484 XSPerfAccumulate(s"allEntry_futype_${fuName}_wakeup_iq_from_exu${params.wakeUpSourceExuIdx(iqIdx)}_src${srcIdx}_cnt", PopCount(perfWakeupByIQVec.get.zip(fuTypeVec).map{ case(x, fu) => x(srcIdx)(iqIdx) && fu(t.id) })) 485 } 486 } 487 } 488 } 489 } 490} 491 492class EntriesIO(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { 493 val flush = Flipped(ValidIO(new Redirect)) 494 //enq 495 val enq = Vec(params.numEnq, Flipped(ValidIO(new EntryBundle))) 496 val og0Resp = Vec(params.numDeq, Flipped(ValidIO(new EntryDeqRespBundle))) 497 val og1Resp = Vec(params.numDeq, Flipped(ValidIO(new EntryDeqRespBundle))) 498 val og2Resp = OptionWrapper(params.inVfSchd, Vec(params.numDeq, Flipped(ValidIO(new EntryDeqRespBundle)))) 499 //deq sel 500 val deqReady = Vec(params.numDeq, Input(Bool())) 501 val deqSelOH = Vec(params.numDeq, Flipped(ValidIO(UInt(params.numEntries.W)))) 502 val enqEntryOldestSel = Vec(params.numDeq, Flipped(ValidIO(UInt(params.numEnq.W)))) 503 val simpEntryOldestSel = OptionWrapper(params.hasCompAndSimp, Vec(params.numDeq, Flipped(ValidIO(UInt(params.numSimp.W))))) 504 val compEntryOldestSel = OptionWrapper(params.hasCompAndSimp, Vec(params.numDeq, Flipped(ValidIO(UInt(params.numComp.W))))) 505 val othersEntryOldestSel= OptionWrapper(params.isAllComp || params.isAllSimp, Vec(params.numDeq, Flipped(ValidIO(UInt((params.numEntries - params.numEnq).W))))) 506 val subDeqRequest = OptionWrapper(params.deqFuSame, Vec(params.numDeq, Input(UInt(params.numEntries.W)))) 507 val subDeqSelOH = OptionWrapper(params.deqFuSame, Vec(params.numDeq, Input(UInt(params.numEntries.W)))) 508 // wakeup 509 val wakeUpFromWB: MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = Flipped(params.genWBWakeUpSinkValidBundle) 510 val wakeUpFromIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(params.genIQWakeUpSinkValidBundle) 511 val og0Cancel = Input(ExuOH(backendParams.numExu)) 512 val og1Cancel = Input(ExuOH(backendParams.numExu)) 513 val ldCancel = Vec(backendParams.LdExuCnt, Flipped(new LoadCancelIO)) 514 //entries status 515 val valid = Output(UInt(params.numEntries.W)) 516 val canIssue = Output(UInt(params.numEntries.W)) 517 val fuType = Vec(params.numEntries, Output(FuType())) 518 val dataSources = Vec(params.numEntries, Vec(params.numRegSrc, Output(DataSource()))) 519 val loadDependency = Vec(params.numEntries, Vec(LoadPipelineWidth, UInt(3.W))) 520 val srcWakeUpL1ExuOH = OptionWrapper(params.hasIQWakeUp, Vec(params.numEntries, Vec(params.numRegSrc, Output(ExuOH())))) 521 //deq status 522 val isFirstIssue = Vec(params.numDeq, Output(Bool())) 523 val deqEntry = Vec(params.numDeq, ValidIO(new EntryBundle)) 524 val cancelDeqVec = Vec(params.numDeq, Output(Bool())) 525 526 // load/hybird only 527 val fromLoad = OptionWrapper(params.isLdAddrIQ || params.isHyAddrIQ, new Bundle { 528 val finalIssueResp = Vec(params.numDeq, Flipped(ValidIO(new EntryDeqRespBundle))) 529 val memAddrIssueResp = Vec(params.numDeq, Flipped(ValidIO(new EntryDeqRespBundle))) 530 }) 531 // mem only 532 val fromMem = OptionWrapper(params.isMemAddrIQ, new Bundle { 533 val slowResp = Vec(params.numDeq, Flipped(ValidIO(new EntryDeqRespBundle))) 534 val fastResp = Vec(params.numDeq, Flipped(ValidIO(new EntryDeqRespBundle))) 535 }) 536 // vec mem only 537 val vecMemIn = OptionWrapper(params.isVecMemIQ, new Bundle { 538 val sqDeqPtr = Input(new SqPtr) 539 val lqDeqPtr = Input(new LqPtr) 540 }) 541 val robIdx = OptionWrapper(params.isVecMemIQ, Output(Vec(params.numEntries, new RobPtr))) 542 val uopIdx = OptionWrapper(params.isVecMemIQ, Output(Vec(params.numEntries, UopIdx()))) 543 544 // trans 545 val simpEntryDeqSelVec = OptionWrapper(params.hasCompAndSimp, Vec(params.numEnq, Input(UInt(params.numSimp.W)))) 546 val simpEntryEnqSelVec = OptionWrapper(params.hasCompAndSimp, Vec(params.numEnq, Output(UInt(params.numSimp.W)))) 547 val compEntryEnqSelVec = OptionWrapper(params.hasCompAndSimp, Vec(params.numEnq, Output(UInt(params.numComp.W)))) 548 val othersEntryEnqSelVec = OptionWrapper(params.isAllComp || params.isAllSimp, Vec(params.numEnq, Output(UInt((params.numEntries - params.numEnq).W)))) 549 550 def wakeup = wakeUpFromWB ++ wakeUpFromIQ 551} 552