xref: /XiangShan/src/main/scala/xiangshan/backend/issue/EnqEntry.scala (revision ac4d321d18df4775b9ddda83e77cf526a0b1ca67) 
1package xiangshan.backend.issue
2
3import org.chipsalliance.cde.config.Parameters
4import chisel3._
5import chisel3.util._
6import utility.{HasCircularQueuePtrHelper, GatedValidRegNext}
7import utils.{MathUtils, OptionWrapper}
8import xiangshan._
9import xiangshan.backend.Bundles._
10import xiangshan.backend.fu.FuType
11import xiangshan.backend.datapath.DataSource
12import xiangshan.backend.rob.RobPtr
13import xiangshan.backend.issue.EntryBundles._
14import xiangshan.mem.{MemWaitUpdateReq, SqPtr, LqPtr}
15
16
17class EnqEntryIO(implicit p: Parameters, params: IssueBlockParams) extends XSBundle {
18  //input
19  val commonIn            = new CommonInBundle
20  val enqDelayWakeUpFromWB: MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = Flipped(params.genWBWakeUpSinkValidBundle)
21  val enqDelayWakeUpFromIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(params.genIQWakeUpSinkValidBundle)
22  val enqDelayOg0Cancel   = Input(ExuOH(backendParams.numExu))
23  val enqDelayLdCancel    = Vec(backendParams.LdExuCnt, Flipped(new LoadCancelIO))
24
25  //output
26  val commonOut           = new CommonOutBundle
27
28  def wakeup              = commonIn.wakeUpFromWB ++ commonIn.wakeUpFromIQ
29}
30
31class EnqEntry(isComp: Boolean)(implicit p: Parameters, params: IssueBlockParams) extends XSModule {
32  val io = IO(new EnqEntryIO)
33
34  val common              = Wire(new CommonWireBundle)
35  val entryUpdate         = Wire(new EntryBundle)
36  val entryRegNext        = Wire(new EntryBundle)
37  val enqDelayValidRegNext= Wire(Bool())
38  val hasWakeupIQ         = OptionWrapper(params.hasIQWakeUp, Wire(new CommonIQWakeupBundle))
39
40  val currentStatus               = Wire(new Status())
41  val enqDelaySrcState            = Wire(Vec(params.numRegSrc, SrcState()))
42  val enqDelayDataSources         = Wire(Vec(params.numRegSrc, DataSource()))
43  val enqDelaySrcWakeUpL1ExuOH    = OptionWrapper(params.hasIQWakeUp, Wire(Vec(params.numRegSrc, ExuOH())))
44  val enqDelaySrcTimer            = OptionWrapper(params.hasIQWakeUp, Wire(Vec(params.numRegSrc, UInt(3.W))))
45  val enqDelaySrcLoadDependency   = Wire(Vec(params.numRegSrc, Vec(LoadPipelineWidth, UInt(3.W))))
46
47  val enqDelaySrcWakeUpByWB: Vec[UInt]                            = Wire(Vec(params.numRegSrc, SrcState()))
48  val enqDelaySrcWakeUpByIQ: Vec[UInt]                            = Wire(Vec(params.numRegSrc, SrcState()))
49  val enqDelaySrcWakeUpByIQVec: Vec[Vec[Bool]]                    = Wire(Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool())))
50  val enqDelayShiftedWakeupLoadDependencyByIQVec: Vec[Vec[UInt]]  = Wire(Vec(params.numWakeupFromIQ, Vec(LoadPipelineWidth, UInt(3.W))))
51
52  //Reg
53  val validReg = GatedValidRegNext(common.validRegNext, false.B)
54  val entryReg = RegEnable(entryRegNext, validReg || common.validRegNext)
55  val enqDelayValidReg = GatedValidRegNext(enqDelayValidRegNext, false.B)
56
57  //Wire
58  CommonWireConnect(common, hasWakeupIQ, validReg, currentStatus, io.commonIn, true)
59
60  when(io.commonIn.enq.valid) {
61    assert(common.enqReady, "Entry is not ready when enq is valid\n")
62  }
63
64  when(io.commonIn.enq.valid && common.enqReady) {
65    entryRegNext := io.commonIn.enq.bits
66  }.otherwise {
67    entryRegNext := entryUpdate
68  }
69
70  when(io.commonIn.enq.valid && common.enqReady) {
71    enqDelayValidRegNext := true.B
72  }.otherwise {
73    enqDelayValidRegNext := false.B
74  }
75
76  if (params.hasIQWakeUp) {
77    ShiftLoadDependency(hasWakeupIQ.get)
78    CommonIQWakeupConnect(common, hasWakeupIQ.get, validReg, currentStatus, io.commonIn, true)
79  }
80
81  // enq delay wakeup
82  enqDelaySrcWakeUpByWB.zipWithIndex.foreach { case (wakeup, i) =>
83    wakeup := io.enqDelayWakeUpFromWB.map(x => x.bits.wakeUp(Seq((entryReg.status.srcStatus(i).psrc, entryReg.status.srcStatus(i).srcType)), x.valid).head
84    ).reduce(_ || _)
85  }
86
87  if (params.hasIQWakeUp) {
88    val wakeupVec: IndexedSeq[IndexedSeq[Bool]] = io.enqDelayWakeUpFromIQ.map( x =>
89      x.bits.wakeUpFromIQ(entryReg.status.srcStatus.map(_.psrc) zip entryReg.status.srcStatus.map(_.srcType))
90    ).toIndexedSeq.transpose
91    val cancelSel = params.wakeUpSourceExuIdx.zip(io.enqDelayWakeUpFromIQ).map{ case (x, y) => io.enqDelayOg0Cancel(x) && y.bits.is0Lat}
92    enqDelaySrcWakeUpByIQVec := wakeupVec.map(x => VecInit(x.zip(cancelSel).map { case (wakeup, cancel) => wakeup && !cancel }))
93  } else {
94    enqDelaySrcWakeUpByIQVec := 0.U.asTypeOf(enqDelaySrcWakeUpByIQVec)
95  }
96
97  if (params.hasIQWakeUp) {
98    enqDelaySrcWakeUpByIQ.zipWithIndex.foreach { case (wakeup, i) =>
99      val ldTransCancel = Mux1H(enqDelaySrcWakeUpByIQVec(i), io.enqDelayWakeUpFromIQ.map(_.bits.loadDependency).map(dp => LoadShouldCancel(Some(dp), io.enqDelayLdCancel)).toSeq)
100      wakeup := enqDelaySrcWakeUpByIQVec(i).asUInt.orR && !ldTransCancel
101    }
102  } else {
103    enqDelaySrcWakeUpByIQ := 0.U.asTypeOf(enqDelaySrcWakeUpByIQ)
104  }
105
106  enqDelayShiftedWakeupLoadDependencyByIQVec.zip(io.enqDelayWakeUpFromIQ.map(_.bits.loadDependency))
107    .zip(params.wakeUpInExuSources.map(_.name)).foreach { case ((dps, ldps), name) =>
108    dps.zip(ldps).zipWithIndex.foreach { case ((dp, ldp), deqPortIdx) =>
109      if (params.backendParam.getLdExuIdx(params.backendParam.allExuParams.find(_.name == name).get) == deqPortIdx)
110        dp := (ldp << 2).asUInt | 2.U
111      else
112        dp := ldp << 1
113    }
114  }
115
116  for (i <- 0 until params.numRegSrc) {
117    enqDelaySrcState(i)                     := entryReg.status.srcStatus(i).srcState | enqDelaySrcWakeUpByWB(i) | enqDelaySrcWakeUpByIQ(i)
118    enqDelayDataSources(i).value            := Mux(enqDelaySrcWakeUpByIQ(i).asBool, DataSource.bypass, entryReg.status.srcStatus(i).dataSources.value)
119    if (params.hasIQWakeUp) {
120      val wakeUpValid = enqDelaySrcWakeUpByIQVec(i).asUInt.orR
121      val wakeUpOH = enqDelaySrcWakeUpByIQVec(i)
122      enqDelaySrcWakeUpL1ExuOH.get(i)       := Mux1H(wakeUpOH, params.wakeUpSourceExuIdx.map(x => MathUtils.IntToOH(x).U(backendParams.numExu.W)).toSeq)
123      enqDelaySrcTimer.get(i)               := Mux(wakeUpValid, 2.U, 3.U)
124      enqDelaySrcLoadDependency(i)          := Mux(enqDelaySrcWakeUpByIQVec(i).asUInt.orR, Mux1H(enqDelaySrcWakeUpByIQVec(i), enqDelayShiftedWakeupLoadDependencyByIQVec), entryReg.status.srcStatus(i).srcLoadDependency)
125    } else {
126      enqDelaySrcLoadDependency(i)          := entryReg.status.srcStatus(i).srcLoadDependency
127    }
128  }
129  currentStatus                             := entryReg.status
130  when (enqDelayValidReg) {
131    currentStatus.srcStatus.zipWithIndex.foreach { case (srcStatus, srcIdx) =>
132      srcStatus.srcState                    := enqDelaySrcState(srcIdx)
133      srcStatus.dataSources                 := enqDelayDataSources(srcIdx)
134      srcStatus.srcTimer.foreach(_          := enqDelaySrcTimer.get(srcIdx))
135      srcStatus.srcLoadDependency           := enqDelaySrcLoadDependency(srcIdx)
136    }
137  }
138
139  if (params.hasIQWakeUp) {
140    currentStatus.srcStatus.map(_.srcWakeUpL1ExuOH.get).zip(entryReg.status.srcStatus.map(_.srcWakeUpL1ExuOH.get)).zip(enqDelaySrcWakeUpL1ExuOH.get).foreach {
141      case ((currExuOH, regExuOH), enqDelayExuOH) =>
142        currExuOH := 0.U.asTypeOf(currExuOH)
143        params.wakeUpSourceExuIdx.foreach(x => currExuOH(x) := Mux(enqDelayValidReg, enqDelayExuOH(x), regExuOH(x)))
144    }
145  }
146
147  EntryRegCommonConnect(common, hasWakeupIQ, validReg, entryUpdate, entryReg, currentStatus, io.commonIn, true)
148
149  //output
150  CommonOutConnect(io.commonOut, common, hasWakeupIQ, validReg, entryUpdate, entryReg, currentStatus, io.commonIn, true, isComp)
151}
152
153class EnqEntryVecMem(isComp: Boolean)(implicit p: Parameters, params: IssueBlockParams) extends EnqEntry(isComp)
154  with HasCircularQueuePtrHelper {
155
156  require(params.isVecMemIQ, "EnqEntryVecMem can only be instance of VecMem IQ")
157
158  EntryVecMemConnect(io.commonIn, common, validReg, entryReg, entryRegNext, entryUpdate)
159}
160
161object EnqEntry {
162  def apply(isComp: Boolean)(implicit p: Parameters, iqParams: IssueBlockParams): EnqEntry = {
163    iqParams.schdType match {
164      case IntScheduler() => new EnqEntry(isComp)
165      case MemScheduler() =>
166        if (iqParams.isVecMemIQ) new EnqEntryVecMem(isComp)
167        else new EnqEntry(isComp)
168      case VfScheduler() => new EnqEntry(isComp)
169      case _ => null
170    }
171  }
172}