xref: /XiangShan/src/main/scala/xiangshan/backend/issue/EnqEntry.scala (revision 9477429f7dc92dfd72de3908b8e953de2886a01d) 
1package xiangshan.backend.issue
2
3import org.chipsalliance.cde.config.Parameters
4import chisel3._
5import chisel3.util._
6import utility.HasCircularQueuePtrHelper
7import utils.{MathUtils, OptionWrapper}
8import xiangshan._
9import xiangshan.backend.Bundles._
10import xiangshan.backend.fu.FuType
11import xiangshan.backend.datapath.DataSource
12import xiangshan.backend.rob.RobPtr
13import xiangshan.backend.issue.EntryBundles._
14import xiangshan.mem.{MemWaitUpdateReq, SqPtr, LqPtr}
15
16
17class EnqEntryIO(implicit p: Parameters, params: IssueBlockParams) extends XSBundle {
18  //input
19  val commonIn            = new CommonInBundle
20  val enqDelayWakeUpFromWB: MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = Flipped(params.genWBWakeUpSinkValidBundle)
21  val enqDelayWakeUpFromIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(params.genIQWakeUpSinkValidBundle)
22  val enqDelayOg0Cancel   = Input(ExuOH(backendParams.numExu))
23  val enqDelayLdCancel    = Vec(backendParams.LdExuCnt, Flipped(new LoadCancelIO))
24
25  //output
26  val commonOut           = new CommonOutBundle
27
28  def wakeup              = commonIn.wakeUpFromWB ++ commonIn.wakeUpFromIQ
29}
30
31class EnqEntry(isComp: Boolean)(implicit p: Parameters, params: IssueBlockParams) extends XSModule {
32  val io = IO(new EnqEntryIO)
33
34  val validReg            = RegInit(false.B)
35  val enqDelayValidReg    = RegInit(false.B)
36
37  val common              = Wire(new CommonWireBundle)
38  val entryUpdate         = Wire(new EntryBundle)
39  val entryRegNext        = Wire(new EntryBundle)
40  val enqDelayValidRegNext= Wire(Bool())
41  val hasWakeupIQ         = OptionWrapper(params.hasIQWakeUp, Wire(new CommonIQWakeupBundle))
42
43  val currentStatus               = Wire(new Status())
44  val enqDelaySrcState            = Wire(Vec(params.numRegSrc, SrcState()))
45  val enqDelayDataSources         = Wire(Vec(params.numRegSrc, DataSource()))
46  val enqDelaySrcWakeUpL1ExuOH    = OptionWrapper(params.hasIQWakeUp, Wire(Vec(params.numRegSrc, ExuOH())))
47  val enqDelaySrcTimer            = OptionWrapper(params.hasIQWakeUp, Wire(Vec(params.numRegSrc, UInt(3.W))))
48  val enqDelaySrcLoadDependency   = Wire(Vec(params.numRegSrc, Vec(LoadPipelineWidth, UInt(3.W))))
49
50  val enqDelaySrcWakeUpByWB: Vec[UInt]                            = Wire(Vec(params.numRegSrc, SrcState()))
51  val enqDelaySrcWakeUpByIQ: Vec[UInt]                            = Wire(Vec(params.numRegSrc, SrcState()))
52  val enqDelaySrcWakeUpByIQVec: Vec[Vec[Bool]]                    = Wire(Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool())))
53  val enqDelayShiftedWakeupLoadDependencyByIQVec: Vec[Vec[UInt]]  = Wire(Vec(params.numWakeupFromIQ, Vec(LoadPipelineWidth, UInt(3.W))))
54
55  //Reg
56  val entryReg = RegEnable(entryRegNext, validReg || common.validRegNext)
57  validReg                        := common.validRegNext
58  enqDelayValidReg                := enqDelayValidRegNext
59
60  //Wire
61  CommonWireConnect(common, hasWakeupIQ, validReg, currentStatus, io.commonIn, true)
62
63  when(io.commonIn.enq.valid) {
64    assert(common.enqReady, "Entry is not ready when enq is valid\n")
65  }
66
67  when(io.commonIn.enq.valid && common.enqReady) {
68    entryRegNext := io.commonIn.enq.bits
69  }.otherwise {
70    entryRegNext := entryUpdate
71  }
72
73  when(io.commonIn.enq.valid && common.enqReady) {
74    enqDelayValidRegNext := true.B
75  }.otherwise {
76    enqDelayValidRegNext := false.B
77  }
78
79  if (params.hasIQWakeUp) {
80    ShiftLoadDependency(hasWakeupIQ.get)
81    CommonIQWakeupConnect(common, hasWakeupIQ.get, validReg, currentStatus, io.commonIn, true)
82  }
83
84  // enq delay wakeup
85  enqDelaySrcWakeUpByWB.zipWithIndex.foreach { case (wakeup, i) =>
86    wakeup := io.enqDelayWakeUpFromWB.map(x => x.bits.wakeUp(Seq((entryReg.status.srcStatus(i).psrc, entryReg.status.srcStatus(i).srcType)), x.valid).head
87    ).reduce(_ || _)
88  }
89
90  if (params.hasIQWakeUp) {
91    val wakeupVec: IndexedSeq[IndexedSeq[Bool]] = io.enqDelayWakeUpFromIQ.map( x =>
92      x.bits.wakeUpFromIQ(entryReg.status.srcStatus.map(_.psrc) zip entryReg.status.srcStatus.map(_.srcType))
93    ).toIndexedSeq.transpose
94    val cancelSel = params.wakeUpSourceExuIdx.zip(io.enqDelayWakeUpFromIQ).map{ case (x, y) => io.enqDelayOg0Cancel(x) && y.bits.is0Lat}
95    enqDelaySrcWakeUpByIQVec := wakeupVec.map(x => VecInit(x.zip(cancelSel).map { case (wakeup, cancel) => wakeup && !cancel }))
96  } else {
97    enqDelaySrcWakeUpByIQVec := 0.U.asTypeOf(enqDelaySrcWakeUpByIQVec)
98  }
99
100  if (params.hasIQWakeUp) {
101    enqDelaySrcWakeUpByIQ.zipWithIndex.foreach { case (wakeup, i) =>
102      val ldTransCancel = Mux1H(enqDelaySrcWakeUpByIQVec(i), io.enqDelayWakeUpFromIQ.map(_.bits.loadDependency).map(dp => LoadShouldCancel(Some(dp), io.enqDelayLdCancel)).toSeq)
103      wakeup := enqDelaySrcWakeUpByIQVec(i).asUInt.orR && !ldTransCancel
104    }
105  } else {
106    enqDelaySrcWakeUpByIQ := 0.U.asTypeOf(enqDelaySrcWakeUpByIQ)
107  }
108
109  enqDelayShiftedWakeupLoadDependencyByIQVec.zip(io.enqDelayWakeUpFromIQ.map(_.bits.loadDependency))
110    .zip(params.wakeUpInExuSources.map(_.name)).foreach { case ((dps, ldps), name) =>
111    dps.zip(ldps).zipWithIndex.foreach { case ((dp, ldp), deqPortIdx) =>
112      if (params.backendParam.getLdExuIdx(params.backendParam.allExuParams.find(_.name == name).get) == deqPortIdx)
113        dp := (ldp << 2).asUInt | 2.U
114      else
115        dp := ldp << 1
116    }
117  }
118
119  for (i <- 0 until params.numRegSrc) {
120    enqDelaySrcState(i)                     := entryReg.status.srcStatus(i).srcState | enqDelaySrcWakeUpByWB(i) | enqDelaySrcWakeUpByIQ(i)
121    enqDelayDataSources(i).value            := Mux(enqDelaySrcWakeUpByIQ(i).asBool, DataSource.bypass, entryReg.status.srcStatus(i).dataSources.value)
122    if (params.hasIQWakeUp) {
123      val wakeUpValid = enqDelaySrcWakeUpByIQVec(i).asUInt.orR
124      val wakeUpOH = enqDelaySrcWakeUpByIQVec(i)
125      enqDelaySrcWakeUpL1ExuOH.get(i)       := Mux1H(wakeUpOH, params.wakeUpSourceExuIdx.map(x => MathUtils.IntToOH(x).U(backendParams.numExu.W)).toSeq)
126      enqDelaySrcTimer.get(i)               := Mux(wakeUpValid, 2.U, 3.U)
127      enqDelaySrcLoadDependency(i)          := Mux(enqDelaySrcWakeUpByIQVec(i).asUInt.orR, Mux1H(enqDelaySrcWakeUpByIQVec(i), enqDelayShiftedWakeupLoadDependencyByIQVec), entryReg.status.srcStatus(i).srcLoadDependency)
128    } else {
129      enqDelaySrcLoadDependency(i)          := entryReg.status.srcStatus(i).srcLoadDependency
130    }
131  }
132  currentStatus                             := entryReg.status
133  when (enqDelayValidReg) {
134    currentStatus.srcStatus.zipWithIndex.foreach { case (srcStatus, srcIdx) =>
135      srcStatus.srcState                    := enqDelaySrcState(srcIdx)
136      srcStatus.dataSources                 := enqDelayDataSources(srcIdx)
137      srcStatus.srcTimer.foreach(_          := enqDelaySrcTimer.get(srcIdx))
138      srcStatus.srcLoadDependency           := enqDelaySrcLoadDependency(srcIdx)
139    }
140  }
141
142  if (params.hasIQWakeUp) {
143    currentStatus.srcStatus.map(_.srcWakeUpL1ExuOH.get).zip(entryReg.status.srcStatus.map(_.srcWakeUpL1ExuOH.get)).zip(enqDelaySrcWakeUpL1ExuOH.get).foreach {
144      case ((currExuOH, regExuOH), enqDelayExuOH) =>
145        currExuOH := 0.U.asTypeOf(currExuOH)
146        params.wakeUpSourceExuIdx.foreach(x => currExuOH(x) := Mux(enqDelayValidReg, enqDelayExuOH(x), regExuOH(x)))
147    }
148  }
149
150  EntryRegCommonConnect(common, hasWakeupIQ, validReg, entryUpdate, entryReg, currentStatus, io.commonIn, true)
151
152  //output
153  CommonOutConnect(io.commonOut, common, hasWakeupIQ, validReg, entryUpdate, entryReg, currentStatus, io.commonIn, true, isComp)
154}
155
156class EnqEntryVecMem(isComp: Boolean)(implicit p: Parameters, params: IssueBlockParams) extends EnqEntry(isComp)
157  with HasCircularQueuePtrHelper {
158
159  require(params.isVecMemIQ, "EnqEntryVecMem can only be instance of VecMem IQ")
160
161  EntryVecMemConnect(io.commonIn, common, validReg, entryReg, entryRegNext, entryUpdate)
162}
163
164object EnqEntry {
165  def apply(isComp: Boolean)(implicit p: Parameters, iqParams: IssueBlockParams): EnqEntry = {
166    iqParams.schdType match {
167      case IntScheduler() => new EnqEntry(isComp)
168      case MemScheduler() =>
169        if (iqParams.isVecMemIQ) new EnqEntryVecMem(isComp)
170        else new EnqEntry(isComp)
171      case VfScheduler() => new EnqEntry(isComp)
172      case _ => null
173    }
174  }
175}