xref: /XiangShan/src/main/scala/xiangshan/backend/issue/EnqEntry.scala (revision 6b102a39d3be6d1d5673cad2c054db245a52f5ff) 
1package xiangshan.backend.issue
2
3import org.chipsalliance.cde.config.Parameters
4import chisel3._
5import chisel3.util._
6import utility.HasCircularQueuePtrHelper
7import utils.{MathUtils, OptionWrapper}
8import xiangshan._
9import xiangshan.backend.Bundles._
10import xiangshan.backend.fu.FuType
11import xiangshan.backend.datapath.DataSource
12import xiangshan.backend.rob.RobPtr
13import xiangshan.mem.{MemWaitUpdateReq, SqPtr, LqPtr}
14
15
16class EnqEntryIO(implicit p: Parameters, params: IssueBlockParams) extends XSBundle {
17  //input
18  val enq = Flipped(ValidIO(new EntryBundle))
19  val flush = Flipped(ValidIO(new Redirect))
20  val wakeUpFromWB: MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = Flipped(params.genWBWakeUpSinkValidBundle)
21  val wakeUpFromIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(params.genIQWakeUpSinkValidBundle)
22  val og0Cancel = Input(ExuOH(backendParams.numExu))
23  val og1Cancel = Input(ExuOH(backendParams.numExu))
24  val ldCancel = Vec(backendParams.LduCnt + backendParams.HyuCnt, Flipped(new LoadCancelIO))
25  val enqDelayWakeUpFromWB: MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = Flipped(params.genWBWakeUpSinkValidBundle)
26  val enqDelayWakeUpFromIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(params.genIQWakeUpSinkValidBundle)
27  val enqDelayOg0Cancel = Input(ExuOH(backendParams.numExu))
28  val enqDelayLdCancel = Vec(backendParams.LdExuCnt, Flipped(new LoadCancelIO))
29  val deqSel = Input(Bool())
30  val deqPortIdxWrite = Input(UInt(1.W))
31  val transSel = Input(Bool())
32  val issueResp = Flipped(ValidIO(new EntryDeqRespBundle))
33  //output
34  val valid = Output(Bool())
35  val canIssue = Output(Bool())
36  val clear = Output(Bool())
37  val fuType = Output(FuType())
38  val dataSource = Output(Vec(params.numRegSrc, DataSource()))
39  val srcWakeUpL1ExuOH = OptionWrapper(params.hasIQWakeUp, Output(Vec(params.numRegSrc, ExuOH())))
40  val srcTimer = OptionWrapper(params.hasIQWakeUp, Output(Vec(params.numRegSrc, UInt(3.W))))
41  val transEntry =  ValidIO(new EntryBundle)
42  val isFirstIssue = Output(Bool())
43  val entry = ValidIO(new EntryBundle)
44  val robIdx = Output(new RobPtr)
45  val uopIdx = OptionWrapper(params.isVecMemIQ, Output(UopIdx()))
46  val deqPortIdxRead = Output(UInt(1.W))
47  val issueTimerRead = Output(UInt(2.W))
48  // mem only
49  val fromMem = if(params.isMemAddrIQ) Some(new Bundle {
50    val stIssuePtr = Input(new SqPtr)
51    val memWaitUpdateReq = Flipped(new MemWaitUpdateReq)
52  }) else None
53  // vector mem only
54  val fromLsq = OptionWrapper(params.isVecMemIQ, new Bundle {
55    val sqDeqPtr = Input(new SqPtr)
56    val lqDeqPtr = Input(new LqPtr)
57  })
58  // debug
59  val cancel = OptionWrapper(params.hasIQWakeUp, Output(Bool()))
60
61  def wakeup = wakeUpFromWB ++ wakeUpFromIQ
62}
63
64class EnqEntry(implicit p: Parameters, params: IssueBlockParams) extends XSModule {
65  val io = IO(new EnqEntryIO)
66
67  val validReg = RegInit(false.B)
68  val entryReg = Reg(new EntryBundle)
69  val enqDelayValidReg = RegInit(false.B)
70
71  val validRegNext = Wire(Bool())
72  val entryRegNext = Wire(new EntryBundle)
73  val entryUpdate = Wire(new EntryBundle)
74  val enqDelayValidRegNext = Wire(Bool())
75  val enqReady = Wire(Bool())
76  val clear = Wire(Bool())
77  val flushed = Wire(Bool())
78  val deqSuccess = Wire(Bool())
79  val srcWakeUp = Wire(Vec(params.numRegSrc, Bool()))
80  val srcWakeUpByWB = Wire(Vec(params.numRegSrc, Bool()))
81  val srcCancelVec = OptionWrapper(params.hasIQWakeUp, Wire(Vec(params.numRegSrc, Bool())))
82  val srcLoadCancelVec = OptionWrapper(params.hasIQWakeUp, Wire(Vec(params.numRegSrc, Bool())))
83  val srcWakeUpByIQVec = Wire(Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool())))
84  val srcWakeUpByIQWithoutCancel = Wire(Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool())))
85  val srcWakeUpButCancel = Wire(Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool())))
86  val srcWakeUpL1ExuOHOut = OptionWrapper(params.hasIQWakeUp, Wire(Vec(params.numRegSrc, ExuOH())))
87  val srcLoadDependencyOut = OptionWrapper(params.hasIQWakeUp, Wire(Vec(params.numRegSrc, Vec(LoadPipelineWidth, UInt(3.W)))))
88  val wakeupLoadDependencyByIQVec = Wire(Vec(params.numWakeupFromIQ, Vec(LoadPipelineWidth, UInt(3.W))))
89  val shiftedWakeupLoadDependencyByIQVec = Wire(Vec(params.numWakeupFromIQ, Vec(LoadPipelineWidth, UInt(3.W))))
90  val shiftedWakeupLoadDependencyByIQBypassVec = Wire(Vec(params.numWakeupFromIQ, Vec(LoadPipelineWidth, UInt(3.W))))
91  val cancelVec = OptionWrapper(params.hasIQWakeUp, Wire(Vec(params.numRegSrc, Bool())))
92
93  val currentStatus = Wire(new Status())
94  val enqDelaySrcState = Wire(Vec(params.numRegSrc, SrcState()))
95  val enqDelayDataSources = Wire(Vec(params.numRegSrc, DataSource()))
96  val enqDelaySrcWakeUpL1ExuOH = OptionWrapper(params.hasIQWakeUp, Wire(Vec(params.numRegSrc, ExuOH())))
97  val enqDelaySrcTimer = OptionWrapper(params.hasIQWakeUp, Wire(Vec(params.numRegSrc, UInt(3.W))))
98  val enqDelaySrcLoadDependency = OptionWrapper(params.hasIQWakeUp, Wire(Vec(params.numRegSrc, Vec(LoadPipelineWidth, UInt(3.W)))))
99
100  val enqDelaySrcWakeUpByWB: Vec[UInt] = Wire(Vec(params.numRegSrc, SrcState()))
101  val enqDelaySrcWakeUpByIQ: Vec[UInt] = Wire(Vec(params.numRegSrc, SrcState()))
102  val enqDelaySrcWakeUpByIQVec: Vec[Vec[Bool]] = Wire(Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool())))
103  val enqDelayShiftedWakeupLoadDependencyByIQVec: Vec[Vec[UInt]] = Wire(Vec(params.numWakeupFromIQ, Vec(LoadPipelineWidth, UInt(3.W))))
104
105  //Reg
106  validReg := validRegNext
107  entryReg := entryRegNext
108  enqDelayValidReg := enqDelayValidRegNext
109
110  //Wire
111  when(io.enq.valid && enqReady) {
112    validRegNext := true.B
113  }.elsewhen(clear) {
114    validRegNext := false.B
115  }.otherwise {
116    validRegNext := validReg
117  }
118
119  when(io.enq.valid && enqReady) {
120    entryRegNext := io.enq.bits
121  }.otherwise {
122    entryRegNext := entryUpdate
123  }
124
125  when(io.enq.valid && enqReady) {
126    enqDelayValidRegNext := true.B
127  }.otherwise {
128    enqDelayValidRegNext := false.B
129  }
130
131  enqReady := !validReg || clear
132  clear := flushed || io.transSel || deqSuccess
133  flushed := entryReg.status.robIdx.needFlush(io.flush)
134  deqSuccess := io.issueResp.valid && io.issueResp.bits.respType === RSFeedbackType.fuIdle && !srcLoadCancelVec.map(_.reduce(_ || _)).getOrElse(false.B)
135
136  // current wakeup
137  srcWakeUpByWB := io.wakeUpFromWB.map(bundle => bundle.bits.wakeUp(entryReg.status.psrc zip entryReg.status.srcType, bundle.valid)).transpose.map(x => VecInit(x.toSeq).asUInt.orR).toSeq
138  srcWakeUp := srcWakeUpByWB.zip(srcWakeUpByIQVec).map { case (x, y) => x || y.asUInt.orR }
139
140  shiftedWakeupLoadDependencyByIQVec
141    .zip(wakeupLoadDependencyByIQVec)
142    .zip(params.wakeUpInExuSources.map(_.name)).foreach {
143    case ((deps, originalDeps), name) => deps.zip(originalDeps).zipWithIndex.foreach {
144      case ((dep, originalDep), deqPortIdx) =>
145        if (params.backendParam.getLdExuIdx(params.backendParam.allExuParams.find(_.name == name).get) == deqPortIdx)
146          dep := (originalDep << 2).asUInt | 2.U
147        else
148          dep := originalDep << 1
149    }
150  }
151  shiftedWakeupLoadDependencyByIQBypassVec
152    .zip(wakeupLoadDependencyByIQVec)
153    .zip(params.wakeUpInExuSources.map(_.name)).foreach {
154    case ((deps, originalDeps), name) => deps.zip(originalDeps).zipWithIndex.foreach {
155      case ((dep, originalDep), deqPortIdx) =>
156        if (params.backendParam.getLdExuIdx(params.backendParam.allExuParams.find(_.name == name).get) == deqPortIdx)
157          dep := (originalDep << 1).asUInt | 1.U
158        else
159          dep := originalDep
160    }
161  }
162
163  if (params.hasIQWakeUp) {
164    srcCancelVec.get.zip(srcLoadCancelVec.get).zip(srcWakeUpByIQWithoutCancel).zipWithIndex.foreach { case (((srcCancel, srcLoadCancel), wakeUpByIQVec), srcIdx) =>
165      val ldTransCancel = Mux1H(wakeUpByIQVec, wakeupLoadDependencyByIQVec.map(dep => LoadShouldCancel(Some(dep), io.ldCancel)))
166      srcLoadCancel := LoadShouldCancel(currentStatus.srcLoadDependency.map(_(srcIdx)), io.ldCancel)
167      srcCancel := srcLoadCancel || ldTransCancel
168    }
169  }
170
171  if (io.wakeUpFromIQ.isEmpty) {
172    srcWakeUpByIQVec := 0.U.asTypeOf(srcWakeUpByIQVec)
173    wakeupLoadDependencyByIQVec := 0.U.asTypeOf(wakeupLoadDependencyByIQVec)
174  } else {
175    val wakeupVec: IndexedSeq[IndexedSeq[Bool]] = io.wakeUpFromIQ.map((bundle: ValidIO[IssueQueueIQWakeUpBundle]) =>
176      bundle.bits.wakeUp(entryReg.status.psrc zip entryReg.status.srcType, bundle.valid)
177    ).toIndexedSeq.transpose
178    val cancelSel = io.wakeUpFromIQ.map(x => x.bits.exuIdx).map(x => io.og0Cancel(x))
179    srcWakeUpByIQVec := wakeupVec.map(x => VecInit(x.zip(cancelSel).map { case (wakeup, cancel) => wakeup && !cancel }))
180    srcWakeUpButCancel := wakeupVec.map(x => VecInit(x.zip(cancelSel).map { case (wakeup, cancel) => wakeup && cancel }))
181    srcWakeUpByIQWithoutCancel := wakeupVec.map(x => VecInit(x))
182    wakeupLoadDependencyByIQVec := io.wakeUpFromIQ.map(_.bits.loadDependency).toSeq
183  }
184
185  // enq delay wakeup
186  enqDelaySrcWakeUpByWB.zipWithIndex.foreach { case (wakeup, i) =>
187    wakeup := io.enqDelayWakeUpFromWB.map(x => x.bits.wakeUp(Seq((entryReg.status.psrc(i), entryReg.status.srcType(i))), x.valid).head
188    ).reduce(_ || _)
189  }
190
191  if (params.hasIQWakeUp) {
192    val wakeupVec: IndexedSeq[IndexedSeq[Bool]] = io.enqDelayWakeUpFromIQ.map( x =>
193      x.bits.wakeUp(entryReg.status.psrc.zip(entryReg.status.srcType), x.valid)
194    ).toIndexedSeq.transpose
195    val cancelSel = io.enqDelayWakeUpFromIQ.map(x => x.bits.exuIdx).map(io.enqDelayOg0Cancel(_))
196    enqDelaySrcWakeUpByIQVec := wakeupVec.map(x => VecInit(x.zip(cancelSel).map { case (wakeup, cancel) => wakeup && !cancel }))
197  } else {
198    enqDelaySrcWakeUpByIQVec := 0.U.asTypeOf(enqDelaySrcWakeUpByIQVec)
199  }
200
201  if (params.hasIQWakeUp) {
202    enqDelaySrcWakeUpByIQ.zipWithIndex.foreach { case (wakeup, i) =>
203      val ldTransCancel = Mux1H(enqDelaySrcWakeUpByIQVec(i), io.enqDelayWakeUpFromIQ.map(_.bits.loadDependency).map(dp => LoadShouldCancel(Some(dp), io.enqDelayLdCancel)).toSeq)
204      wakeup := enqDelaySrcWakeUpByIQVec(i).asUInt.orR && !ldTransCancel
205    }
206  } else {
207    enqDelaySrcWakeUpByIQ := 0.U.asTypeOf(enqDelaySrcWakeUpByIQ)
208  }
209
210  enqDelayShiftedWakeupLoadDependencyByIQVec.zip(io.enqDelayWakeUpFromIQ.map(_.bits.loadDependency))
211    .zip(params.wakeUpInExuSources.map(_.name)).foreach { case ((dps, ldps), name) =>
212    dps.zip(ldps).zipWithIndex.foreach { case ((dp, ldp), deqPortIdx) =>
213      if (params.backendParam.getLdExuIdx(params.backendParam.allExuParams.find(_.name == name).get) == deqPortIdx)
214        dp := (ldp << 2).asUInt | 2.U
215      else
216        dp := ldp << 1
217    }
218  }
219
220  for(i <- 0 until params.numRegSrc) {
221    enqDelaySrcState(i) := entryReg.status.srcState(i) | enqDelaySrcWakeUpByWB(i) | enqDelaySrcWakeUpByIQ(i)
222    enqDelayDataSources(i).value := Mux(enqDelaySrcWakeUpByIQ(i).asBool, DataSource.bypass, DataSource.reg)
223    if (params.hasIQWakeUp) {
224      val wakeUpValid = enqDelaySrcWakeUpByIQVec(i).asUInt.orR
225      val wakeUpOH = enqDelaySrcWakeUpByIQVec(i)
226      enqDelaySrcWakeUpL1ExuOH.get(i) := Mux1H(wakeUpOH, io.enqDelayWakeUpFromIQ.map(x => MathUtils.IntToOH(x.bits.exuIdx).U(backendParams.numExu.W)).toSeq)
227      enqDelaySrcTimer.get(i) := Mux(wakeUpValid, 2.U, 3.U)
228      enqDelaySrcLoadDependency.get(i) := Mux(wakeUpValid, Mux1H(wakeUpOH, enqDelayShiftedWakeupLoadDependencyByIQVec), entryReg.status.srcLoadDependency.get(i))
229    }
230  }
231  currentStatus := entryReg.status
232  when (enqDelayValidReg) {
233    currentStatus.srcState := enqDelaySrcState
234    currentStatus.dataSources := enqDelayDataSources
235    currentStatus.srcWakeUpL1ExuOH.foreach(_ := enqDelaySrcWakeUpL1ExuOH.get)
236    currentStatus.srcTimer.foreach(_ := enqDelaySrcTimer.get)
237    currentStatus.srcLoadDependency.foreach(_ := enqDelaySrcLoadDependency.get)
238  }
239
240  //entryUpdate
241  entryUpdate.status.srcState.zip(currentStatus.srcState).zip(srcWakeUp).zipWithIndex.foreach { case (((stateNext, state), wakeup), srcIdx) =>
242    val cancel = srcCancelVec.map(_ (srcIdx)).getOrElse(false.B)
243    stateNext := Mux(cancel, false.B, wakeup | state)
244    if (params.hasIQWakeUp) {
245      cancelVec.get(srcIdx) := cancel
246    }
247  }
248  entryUpdate.status.dataSources.zip(srcWakeUpByIQVec).foreach {
249    case (dataSourceNext: DataSource, wakeUpByIQOH: Vec[Bool]) =>
250      when(wakeUpByIQOH.asUInt.orR) {
251        dataSourceNext.value := DataSource.bypass
252      }.otherwise {
253        dataSourceNext.value := DataSource.reg
254      }
255  }
256  if (params.hasIQWakeUp) {
257    entryUpdate.status.srcWakeUpL1ExuOH.get.zip(srcWakeUpByIQVec).zip(srcWakeUp).zipWithIndex.foreach {
258      case (((exuOH: UInt, wakeUpByIQOH: Vec[Bool]), wakeUp: Bool), srcIdx) =>
259        when(wakeUpByIQOH.asUInt.orR) {
260          exuOH := Mux1H(wakeUpByIQOH, io.wakeUpFromIQ.toSeq.map(x => MathUtils.IntToOH(x.bits.exuIdx).U(backendParams.numExu.W)))
261        }.elsewhen(wakeUp) {
262          exuOH := 0.U.asTypeOf(exuOH)
263        }.otherwise {
264          exuOH := currentStatus.srcWakeUpL1ExuOH.get(srcIdx)
265        }
266    }
267    srcWakeUpL1ExuOHOut.get.zip(srcWakeUpByIQWithoutCancel).zip(srcWakeUp).zipWithIndex.foreach {
268      case (((exuOH: UInt, wakeUpByIQOH: Vec[Bool]), wakeUp: Bool), srcIdx) =>
269        when(wakeUpByIQOH.asUInt.orR) {
270          exuOH := Mux1H(wakeUpByIQOH, io.wakeUpFromIQ.map(x => MathUtils.IntToOH(x.bits.exuIdx).U(backendParams.numExu.W)).toSeq)
271        }.otherwise {
272          exuOH := currentStatus.srcWakeUpL1ExuOH.get(srcIdx)
273        }
274    }
275    entryUpdate.status.srcTimer.get.zip(currentStatus.srcTimer.get).zip(srcWakeUpByIQVec).zipWithIndex.foreach {
276      case (((srcIssuedTimerNext, srcIssuedTimer), wakeUpByIQOH: Vec[Bool]), srcIdx) =>
277        srcIssuedTimerNext := MuxCase(3.U, Seq(
278          // T0: waked up by IQ, T1: reset timer as 1
279          wakeUpByIQOH.asUInt.orR -> 2.U,
280          // do not overflow
281          srcIssuedTimer.andR -> srcIssuedTimer,
282          // T2+: increase if the entry is valid, the src is ready, and the src is woken up by iq
283          (validReg && SrcState.isReady(currentStatus.srcState(srcIdx)) && currentStatus.srcWakeUpL1ExuOH.get.asUInt.orR) -> (srcIssuedTimer + 1.U)
284        ))
285    }
286    entryUpdate.status.srcLoadDependency.get.zip(currentStatus.srcLoadDependency.get).zip(srcWakeUpByIQVec).zip(srcWakeUp).foreach {
287      case (((loadDependencyNext, loadDependency), wakeUpByIQVec), wakeup) =>
288        loadDependencyNext :=
289          Mux(wakeup,
290            Mux1H(wakeUpByIQVec, shiftedWakeupLoadDependencyByIQVec),
291            Mux(validReg && loadDependency.asUInt.orR, VecInit(loadDependency.map(i => i(i.getWidth - 2, 0) << 1)), loadDependency)
292          )
293    }
294    srcLoadDependencyOut.get.zip(currentStatus.srcLoadDependency.get).zip(srcWakeUpByIQVec).zip(srcWakeUp).foreach {
295      case (((loadDependencyOut, loadDependency), wakeUpByIQVec), wakeup) =>
296        loadDependencyOut := Mux1H(wakeUpByIQVec, shiftedWakeupLoadDependencyByIQBypassVec)
297    }
298  }
299
300  when(io.deqSel) {
301    entryUpdate.status.issueTimer := 0.U
302    entryUpdate.status.deqPortIdx := io.deqPortIdxWrite
303  }.elsewhen(entryReg.status.issued){
304    entryUpdate.status.issueTimer := entryReg.status.issueTimer + 1.U
305    entryUpdate.status.deqPortIdx := entryReg.status.deqPortIdx
306  }.otherwise {
307    entryUpdate.status.issueTimer := "b10".U
308    entryUpdate.status.deqPortIdx := 0.U
309  }
310  entryUpdate.status.psrc := entryReg.status.psrc
311  entryUpdate.status.srcType := entryReg.status.srcType
312  entryUpdate.status.fuType := entryReg.status.fuType
313  entryUpdate.status.robIdx := entryReg.status.robIdx
314  when(srcLoadCancelVec.map(_.reduce(_ || _)).getOrElse(false.B) || srcWakeUpButCancel.map(_.fold(false.B)(_ || _)).fold(false.B)(_ || _)) {
315    entryUpdate.status.issued := false.B
316  }.elsewhen(io.deqSel) {
317    entryUpdate.status.issued := true.B
318  }.elsewhen(io.issueResp.valid && RSFeedbackType.isBlocked(io.issueResp.bits.respType)) {
319    entryUpdate.status.issued := false.B
320  }.elsewhen(!currentStatus.srcReady) {
321    entryUpdate.status.issued := false.B
322  }.otherwise {
323    entryUpdate.status.issued := entryReg.status.issued
324  }
325  entryUpdate.status.firstIssue := io.deqSel || entryReg.status.firstIssue
326  entryUpdate.status.blocked := false.B //todo
327  //remain imm and payload
328  entryUpdate.imm.foreach(_ := entryReg.imm.get)
329  entryUpdate.payload := entryReg.payload
330
331  //output
332  val canIssue = currentStatus.canIssue && validReg && !srcCancelVec.getOrElse(false.B).asUInt.orR
333  val canIssueBypass = validReg && !entryReg.status.issued && !entryReg.status.blocked &&
334    VecInit(currentStatus.srcState.zip(srcWakeUpByIQWithoutCancel).zipWithIndex.map { case ((state, wakeupVec), srcIdx) =>
335      val cancel = srcCancelVec.map(_ (srcIdx)).getOrElse(false.B)
336      Mux(cancel, false.B, wakeupVec.asUInt.orR | state)
337    }).asUInt.andR
338  io.dataSource.zip(currentStatus.dataSources).zip(srcWakeUpByIQVec).zip(srcWakeUp).foreach {
339    case (((dataSourceOut: DataSource, dataSource: DataSource), wakeUpByIQOH: Vec[Bool]), wakeUpAll) =>
340      when(wakeUpByIQOH.asUInt.orR) {
341        dataSourceOut.value := DataSource.forward
342      }.otherwise {
343        dataSourceOut.value := dataSource.value
344      }
345  }
346  if (params.hasIQWakeUp) {
347    io.srcTimer.get.zip(currentStatus.srcTimer.get).zip(srcWakeUpByIQWithoutCancel).zip(srcWakeUp).foreach {
348      case (((srcTimerOut, srcTimer), wakeUpByIQOH: Vec[Bool]), wakeUpAll) =>
349        when(wakeUpByIQOH.asUInt.orR) {
350          srcTimerOut := 1.U
351        }.otherwise {
352          srcTimerOut := srcTimer
353        }
354    }
355    io.srcWakeUpL1ExuOH.get := Mux(canIssueBypass && !canIssue, srcWakeUpL1ExuOHOut.get, currentStatus.srcWakeUpL1ExuOH.get)
356  }
357  io.transEntry.valid := validReg && !flushed && !deqSuccess
358  io.transEntry.bits := entryUpdate
359  io.canIssue := (canIssue || canIssueBypass) && !flushed
360  io.clear := clear
361  io.fuType := entryReg.status.fuType
362  io.valid := validReg
363  io.isFirstIssue := !entryReg.status.firstIssue
364  io.entry.valid := validReg
365  io.entry.bits := entryReg
366  io.entry.bits.status := currentStatus
367  io.entry.bits.status.srcLoadDependency.foreach(_ := Mux(canIssueBypass && !canIssue, srcLoadDependencyOut.get, currentStatus.srcLoadDependency.get))
368  io.robIdx := entryReg.status.robIdx
369  io.uopIdx.foreach(_ := entryReg.status.uopIdx.get)
370  io.issueTimerRead := entryReg.status.issueTimer
371  io.deqPortIdxRead := entryReg.status.deqPortIdx
372  io.cancel.foreach(_ := cancelVec.get.asUInt.orR)
373}
374
375class EnqEntryMem()(implicit p: Parameters, params: IssueBlockParams) extends EnqEntry
376  with HasCircularQueuePtrHelper {
377  val fromMem = io.fromMem.get
378
379  val memStatus = entryReg.status.mem.get
380  println("memStatus" + memStatus)
381  val memStatusNext = entryRegNext.status.mem.get
382  val memStatusUpdate = entryUpdate.status.mem.get
383
384  // load cannot be issued before older store, unless meet some condition
385  val blockedByOlderStore = isAfter(memStatusNext.sqIdx, fromMem.stIssuePtr)
386
387  val deqFailedForStdInvalid = io.issueResp.valid && io.issueResp.bits.respType === RSFeedbackType.dataInvalid
388
389  val staWaitedReleased = Cat(
390    fromMem.memWaitUpdateReq.robIdx.map(x => x.valid && x.bits.value === memStatusNext.waitForRobIdx.value)
391  ).orR
392  val stdWaitedReleased = Cat(
393    fromMem.memWaitUpdateReq.sqIdx.map(x => x.valid && x.bits.value === memStatusNext.waitForSqIdx.value)
394  ).orR
395  val olderStaNotViolate = staWaitedReleased && !memStatusNext.strictWait
396  val olderStdReady = stdWaitedReleased && memStatusNext.waitForStd
397  val waitStd = !olderStdReady
398  val waitSta = !olderStaNotViolate
399
400  when (io.enq.valid && enqReady) {
401    memStatusNext.waitForSqIdx := io.enq.bits.status.mem.get.waitForSqIdx
402    // update by lfst at dispatch stage
403    memStatusNext.waitForRobIdx := io.enq.bits.status.mem.get.waitForRobIdx
404    // new load inst don't known if it is blocked by store data ahead of it
405    memStatusNext.waitForStd := false.B
406    // update by ssit at rename stage
407    memStatusNext.strictWait := io.enq.bits.status.mem.get.strictWait
408    memStatusNext.sqIdx := io.enq.bits.status.mem.get.sqIdx
409  }.otherwise {
410    memStatusNext := memStatusUpdate
411  }
412
413  when(deqFailedForStdInvalid) {
414    memStatusUpdate.waitForSqIdx := io.issueResp.bits.dataInvalidSqIdx
415    memStatusUpdate.waitForRobIdx := memStatus.waitForRobIdx
416    memStatusUpdate.waitForStd := true.B
417    memStatusUpdate.strictWait := memStatus.strictWait
418    memStatusUpdate.sqIdx := memStatus.sqIdx
419  }.otherwise {
420    memStatusUpdate := memStatus
421  }
422
423  val shouldBlock = Mux(io.enq.valid && enqReady, io.enq.bits.status.blocked, entryReg.status.blocked)
424  val blockNotReleased = waitStd || waitSta
425  val respBlock = deqFailedForStdInvalid
426  entryRegNext.status.blocked := shouldBlock && blockNotReleased && blockedByOlderStore || respBlock
427  entryUpdate.status.blocked := shouldBlock && blockNotReleased && blockedByOlderStore || respBlock
428
429}
430
431class EnqEntryVecMemAddr()(implicit p: Parameters, params: IssueBlockParams) extends EnqEntryMem {
432
433  require(params.isVecMemAddrIQ, "EnqEntryVecMemAddr can only be instance of VecMemAddr IQ")
434
435  val vecMemStatus = entryReg.status.vecMem.get
436  val vecMemStatusNext = entryRegNext.status.vecMem.get
437  val vecMemStatusUpdate = entryUpdate.status.vecMem.get
438  val fromLsq = io.fromLsq.get
439
440  when (io.enq.valid && enqReady) {
441    vecMemStatusNext.sqIdx := io.enq.bits.status.vecMem.get.sqIdx
442    vecMemStatusNext.lqIdx := io.enq.bits.status.vecMem.get.lqIdx
443  }.otherwise {
444    vecMemStatusNext := vecMemStatusUpdate
445  }
446  vecMemStatusUpdate := vecMemStatus
447
448  val isLsqHead = {
449    // if (params.isVecLdAddrIQ)
450      entryRegNext.status.vecMem.get.lqIdx <= fromLsq.lqDeqPtr &&
451    // else
452      entryRegNext.status.vecMem.get.sqIdx <= fromLsq.sqDeqPtr
453  }
454
455  entryRegNext.status.blocked := shouldBlock && blockNotReleased && blockedByOlderStore || respBlock || !isLsqHead
456  entryUpdate.status.blocked := shouldBlock && blockNotReleased && blockedByOlderStore || respBlock || !isLsqHead
457  entryUpdate.status.uopIdx.get := entryReg.status.uopIdx.get
458}
459
460class EnqEntryVecMemData()(implicit p: Parameters, params: IssueBlockParams) extends EnqEntry
461  with HasCircularQueuePtrHelper {
462
463  require(params.isVecStDataIQ, "EnqEntryVecMemData can only be instance of VecMemData IQ")
464
465  val vecMemStatus = entryReg.status.vecMem.get
466  val vecMemStatusNext = entryRegNext.status.vecMem.get
467  val vecMemStatusUpdate = entryUpdate.status.vecMem.get
468  val fromLsq = io.fromLsq.get
469
470  when (io.enq.valid && enqReady) {
471    vecMemStatusNext.sqIdx := io.enq.bits.status.vecMem.get.sqIdx
472    vecMemStatusNext.lqIdx := io.enq.bits.status.vecMem.get.lqIdx
473  }.otherwise {
474    vecMemStatusNext := vecMemStatusUpdate
475  }
476  vecMemStatusUpdate := vecMemStatus
477
478  val isLsqHead = entryRegNext.status.vecMem.get.sqIdx.value === fromLsq.sqDeqPtr.value
479
480  entryRegNext.status.blocked := !isLsqHead
481  entryUpdate.status.blocked := !isLsqHead
482  entryUpdate.status.uopIdx.get := entryReg.status.uopIdx.get
483}
484
485object EnqEntry {
486  def apply(implicit p: Parameters, iqParams: IssueBlockParams): EnqEntry = {
487    iqParams.schdType match {
488      case IntScheduler() => new EnqEntry()
489      case MemScheduler() =>
490        if (iqParams.isLdAddrIQ || iqParams.isStAddrIQ || iqParams.isHyAddrIQ) new EnqEntryMem()
491        else if (iqParams.isVecMemAddrIQ) new EnqEntryVecMemAddr()
492        else if (iqParams.isVecStDataIQ) new EnqEntryVecMemData()
493        else new EnqEntry()
494      case VfScheduler() => new EnqEntry()
495      case _ => null
496    }
497  }
498}