xref: /XiangShan/src/main/scala/xiangshan/backend/issue/EnqEntry.scala (revision 397c0f330295d110f9451000814959f075ccb37a) 
1package xiangshan.backend.issue
2
3import org.chipsalliance.cde.config.Parameters
4import chisel3._
5import chisel3.util._
6import utility.HasCircularQueuePtrHelper
7import utils.{MathUtils, OptionWrapper}
8import xiangshan._
9import xiangshan.backend.Bundles._
10import xiangshan.backend.fu.FuType
11import xiangshan.backend.datapath.DataSource
12import xiangshan.backend.rob.RobPtr
13import xiangshan.backend.issue.EntryBundles._
14import xiangshan.mem.{MemWaitUpdateReq, SqPtr, LqPtr}
15
16
17class EnqEntryIO(implicit p: Parameters, params: IssueBlockParams) extends XSBundle {
18  //input
19  val commonIn            = new CommonInBundle
20  val enqDelayWakeUpFromWB: MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = Flipped(params.genWBWakeUpSinkValidBundle)
21  val enqDelayWakeUpFromIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(params.genIQWakeUpSinkValidBundle)
22  val enqDelayOg0Cancel   = Input(ExuOH(backendParams.numExu))
23  val enqDelayLdCancel    = Vec(backendParams.LdExuCnt, Flipped(new LoadCancelIO))
24
25  //output
26  val commonOut           = new CommonOutBundle
27
28  def wakeup              = commonIn.wakeUpFromWB ++ commonIn.wakeUpFromIQ
29}
30
31class EnqEntry(implicit p: Parameters, params: IssueBlockParams) extends XSModule {
32  val io = IO(new EnqEntryIO)
33
34  val validReg            = RegInit(false.B)
35  val enqDelayValidReg    = RegInit(false.B)
36  val entryReg            = Reg(new EntryBundle)
37
38  val common              = Wire(new CommonWireBundle)
39  val entryUpdate         = Wire(new EntryBundle)
40  val entryRegNext        = Wire(new EntryBundle)
41  val enqDelayValidRegNext= Wire(Bool())
42  val hasWakeupIQ         = OptionWrapper(params.hasIQWakeUp, Wire(new CommonIQWakeupBundle))
43
44  val currentStatus               = Wire(new Status())
45  val enqDelaySrcState            = Wire(Vec(params.numRegSrc, SrcState()))
46  val enqDelayDataSources         = Wire(Vec(params.numRegSrc, DataSource()))
47  val enqDelaySrcWakeUpL1ExuOH    = OptionWrapper(params.hasIQWakeUp, Wire(Vec(params.numRegSrc, ExuOH())))
48  val enqDelaySrcTimer            = OptionWrapper(params.hasIQWakeUp, Wire(Vec(params.numRegSrc, UInt(3.W))))
49  val enqDelaySrcLoadDependency   = OptionWrapper(params.hasIQWakeUp, Wire(Vec(params.numRegSrc, Vec(LoadPipelineWidth, UInt(3.W)))))
50
51  val enqDelaySrcWakeUpByWB: Vec[UInt]                            = Wire(Vec(params.numRegSrc, SrcState()))
52  val enqDelaySrcWakeUpByIQ: Vec[UInt]                            = Wire(Vec(params.numRegSrc, SrcState()))
53  val enqDelaySrcWakeUpByIQVec: Vec[Vec[Bool]]                    = Wire(Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool())))
54  val enqDelayShiftedWakeupLoadDependencyByIQVec: Vec[Vec[UInt]]  = Wire(Vec(params.numWakeupFromIQ, Vec(LoadPipelineWidth, UInt(3.W))))
55
56  //Reg
57  validReg                        := common.validRegNext
58  entryReg                        := entryRegNext
59  enqDelayValidReg                := enqDelayValidRegNext
60
61  //Wire
62  CommonWireConnect(common, hasWakeupIQ, validReg, currentStatus, io.commonIn, true)
63
64  when(io.commonIn.enq.valid && common.enqReady) {
65    entryRegNext := io.commonIn.enq.bits
66  }.otherwise {
67    entryRegNext := entryUpdate
68  }
69
70  when(io.commonIn.enq.valid && common.enqReady) {
71    enqDelayValidRegNext := true.B
72  }.otherwise {
73    enqDelayValidRegNext := false.B
74  }
75
76  if (params.hasIQWakeUp) {
77    ShiftLoadDependency(hasWakeupIQ.get)
78    CommonIQWakeupConnect(common, hasWakeupIQ.get, validReg, currentStatus, io.commonIn, true)
79  }
80
81  // enq delay wakeup
82  enqDelaySrcWakeUpByWB.zipWithIndex.foreach { case (wakeup, i) =>
83    wakeup := io.enqDelayWakeUpFromWB.map(x => x.bits.wakeUp(Seq((entryReg.status.srcStatus(i).psrc, entryReg.status.srcStatus(i).srcType)), x.valid).head
84    ).reduce(_ || _)
85  }
86
87  if (params.hasIQWakeUp) {
88    val wakeupVec: IndexedSeq[IndexedSeq[Bool]] = io.enqDelayWakeUpFromIQ.map( x =>
89      x.bits.wakeUpFromIQ(entryReg.status.srcStatus.map(_.psrc) zip entryReg.status.srcStatus.map(_.srcType))
90    ).toIndexedSeq.transpose
91    val cancelSel = params.wakeUpSourceExuIdx.zip(io.enqDelayWakeUpFromIQ).map{ case (x, y) => io.enqDelayOg0Cancel(x) && y.bits.is0Lat}
92    enqDelaySrcWakeUpByIQVec := wakeupVec.map(x => VecInit(x.zip(cancelSel).map { case (wakeup, cancel) => wakeup && !cancel }))
93  } else {
94    enqDelaySrcWakeUpByIQVec := 0.U.asTypeOf(enqDelaySrcWakeUpByIQVec)
95  }
96
97  if (params.hasIQWakeUp) {
98    enqDelaySrcWakeUpByIQ.zipWithIndex.foreach { case (wakeup, i) =>
99      val ldTransCancel = Mux1H(enqDelaySrcWakeUpByIQVec(i), io.enqDelayWakeUpFromIQ.map(_.bits.loadDependency).map(dp => LoadShouldCancel(Some(dp), io.enqDelayLdCancel)).toSeq)
100      wakeup := enqDelaySrcWakeUpByIQVec(i).asUInt.orR && !ldTransCancel
101    }
102  } else {
103    enqDelaySrcWakeUpByIQ := 0.U.asTypeOf(enqDelaySrcWakeUpByIQ)
104  }
105
106  enqDelayShiftedWakeupLoadDependencyByIQVec.zip(io.enqDelayWakeUpFromIQ.map(_.bits.loadDependency))
107    .zip(params.wakeUpInExuSources.map(_.name)).foreach { case ((dps, ldps), name) =>
108    dps.zip(ldps).zipWithIndex.foreach { case ((dp, ldp), deqPortIdx) =>
109      if (params.backendParam.getLdExuIdx(params.backendParam.allExuParams.find(_.name == name).get) == deqPortIdx)
110        dp := (ldp << 2).asUInt | 2.U
111      else
112        dp := ldp << 1
113    }
114  }
115
116  for (i <- 0 until params.numRegSrc) {
117    enqDelaySrcState(i)                     := entryReg.status.srcStatus(i).srcState | enqDelaySrcWakeUpByWB(i) | enqDelaySrcWakeUpByIQ(i)
118    enqDelayDataSources(i).value            := Mux(enqDelaySrcWakeUpByIQ(i).asBool, DataSource.bypass, DataSource.reg)
119    if (params.hasIQWakeUp) {
120      val wakeUpValid = enqDelaySrcWakeUpByIQVec(i).asUInt.orR
121      val wakeUpOH = enqDelaySrcWakeUpByIQVec(i)
122      enqDelaySrcWakeUpL1ExuOH.get(i)       := Mux1H(wakeUpOH, params.wakeUpSourceExuIdx.map(x => MathUtils.IntToOH(x).U(backendParams.numExu.W)).toSeq)
123      enqDelaySrcTimer.get(i)               := Mux(wakeUpValid, 2.U, 3.U)
124      enqDelaySrcLoadDependency.get(i)      := Mux(wakeUpValid, Mux1H(wakeUpOH, enqDelayShiftedWakeupLoadDependencyByIQVec), entryReg.status.srcStatus(i).srcLoadDependency.get)
125    }
126  }
127  currentStatus                             := entryReg.status
128  when (enqDelayValidReg) {
129    currentStatus.srcStatus.zipWithIndex.foreach { case (srcStatus, srcIdx) =>
130      srcStatus.srcState                    := enqDelaySrcState(srcIdx)
131      srcStatus.dataSources                 := enqDelayDataSources(srcIdx)
132      srcStatus.srcTimer.foreach(_          := enqDelaySrcTimer.get(srcIdx))
133      srcStatus.srcLoadDependency.foreach(_ := enqDelaySrcLoadDependency.get(srcIdx))
134    }
135  }
136
137  if (params.hasIQWakeUp) {
138    currentStatus.srcStatus.map(_.srcWakeUpL1ExuOH.get).zip(entryReg.status.srcStatus.map(_.srcWakeUpL1ExuOH.get)).zip(enqDelaySrcWakeUpL1ExuOH.get).foreach {
139      case ((currExuOH, regExuOH), enqDelayExuOH) =>
140        currExuOH := 0.U.asTypeOf(currExuOH)
141        params.wakeUpSourceExuIdx.foreach(x => currExuOH(x) := Mux(enqDelayValidReg, enqDelayExuOH(x), regExuOH(x)))
142    }
143  }
144
145  EntryRegCommonConnect(common, hasWakeupIQ, validReg, entryUpdate, entryReg, currentStatus, io.commonIn, true)
146
147  //output
148  CommonOutConnect(io.commonOut, common, hasWakeupIQ, validReg, entryUpdate, entryReg, currentStatus, io.commonIn, true)
149}
150
151class EnqEntryMem()(implicit p: Parameters, params: IssueBlockParams) extends EnqEntry
152  with HasCircularQueuePtrHelper {
153  EntryMemConnect(io.commonIn, common, validReg, entryReg, entryRegNext, entryUpdate, true)
154}
155
156class EnqEntryVecMemAddr()(implicit p: Parameters, params: IssueBlockParams) extends EnqEntryMem {
157
158  require(params.isVecMemAddrIQ, "EnqEntryVecMemAddr can only be instance of VecMemAddr IQ")
159
160  val vecMemStatus = entryReg.status.vecMem.get
161  val vecMemStatusNext = entryRegNext.status.vecMem.get
162  val vecMemStatusUpdate = entryUpdate.status.vecMem.get
163  val fromLsq = io.commonIn.fromLsq.get
164
165  when (io.commonIn.enq.valid && common.enqReady) {
166    vecMemStatusNext.sqIdx := io.commonIn.enq.bits.status.vecMem.get.sqIdx
167    vecMemStatusNext.lqIdx := io.commonIn.enq.bits.status.vecMem.get.lqIdx
168  }.otherwise {
169    vecMemStatusNext := vecMemStatusUpdate
170  }
171  vecMemStatusUpdate := vecMemStatus
172
173  val isLsqHead = {
174    // if (params.isVecLdAddrIQ)
175      entryRegNext.status.vecMem.get.lqIdx <= fromLsq.lqDeqPtr &&
176    // else
177      entryRegNext.status.vecMem.get.sqIdx <= fromLsq.sqDeqPtr
178  }
179
180  entryUpdate.status.vecMem.get.uopIdx := entryReg.status.vecMem.get.uopIdx
181}
182
183class EnqEntryVecMemData()(implicit p: Parameters, params: IssueBlockParams) extends EnqEntry
184  with HasCircularQueuePtrHelper {
185
186  require(params.isVecStDataIQ, "EnqEntryVecMemData can only be instance of VecMemData IQ")
187
188  val vecMemStatus = entryReg.status.vecMem.get
189  val vecMemStatusNext = entryRegNext.status.vecMem.get
190  val vecMemStatusUpdate = entryUpdate.status.vecMem.get
191  val fromLsq = io.commonIn.fromLsq.get
192
193  when (io.commonIn.enq.valid && common.enqReady) {
194    vecMemStatusNext.sqIdx := io.commonIn.enq.bits.status.vecMem.get.sqIdx
195    vecMemStatusNext.lqIdx := io.commonIn.enq.bits.status.vecMem.get.lqIdx
196  }.otherwise {
197    vecMemStatusNext := vecMemStatusUpdate
198  }
199  vecMemStatusUpdate := vecMemStatus
200
201  val isLsqHead = entryRegNext.status.vecMem.get.sqIdx.value === fromLsq.sqDeqPtr.value
202
203  entryRegNext.status.blocked := !isLsqHead
204  entryUpdate.status.blocked := !isLsqHead
205  entryUpdate.status.vecMem.get.uopIdx := entryReg.status.vecMem.get.uopIdx
206}
207
208object EnqEntry {
209  def apply(implicit p: Parameters, iqParams: IssueBlockParams): EnqEntry = {
210    iqParams.schdType match {
211      case IntScheduler() => new EnqEntry()
212      case MemScheduler() =>
213        if (iqParams.isLdAddrIQ || iqParams.isStAddrIQ || iqParams.isHyAddrIQ) new EnqEntryMem()
214        else if (iqParams.isVecMemAddrIQ) new EnqEntryVecMemAddr()
215        else if (iqParams.isVecStDataIQ) new EnqEntryVecMemData()
216        else new EnqEntry()
217      case VfScheduler() => new EnqEntry()
218      case _ => null
219    }
220  }
221}