xref: /XiangShan/src/main/scala/xiangshan/backend/issue/BypassNetwork.scala (revision eb163ef08fc5ac1da1f32d948699bd6de053e444) 
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package xiangshan.backend.issue
18
19import chipsalliance.rocketchip.config.Parameters
20import chisel3._
21import chisel3.util._
22import xiangshan._
23import utils._
24
25
26class BypassInfo(numWays: Int, dataBits: Int) extends Bundle {
27  val valid = Vec(numWays, Bool())
28  val data = UInt(dataBits.W)
29}
30
31class BypassNetworkIO(numWays: Int, numBypass: Int, dataBits: Int) extends Bundle {
32  val hold = Input(Bool())
33  val source = Vec(numWays, Input(UInt(dataBits.W)))
34  val target = Vec(numWays, Output(UInt(dataBits.W)))
35  val bypass = Vec(numBypass, Input(new BypassInfo(numWays, dataBits)))
36}
37
38class BypassNetwork(numWays: Int, numBypass: Int, dataBits: Int)(implicit p: Parameters)
39  extends XSModule {
40
41  val io = IO(new BypassNetworkIO(numWays, numBypass, dataBits))
42
43  def doBypass(bypassValid: Seq[Bool], bypassData: Seq[UInt], baseData: UInt, debugIndex: Int = 0): UInt = {
44    val bypassVec = VecInit(bypassValid)
45    val target = Mux(bypassVec.asUInt.orR, ParallelMux(bypassValid, bypassData), baseData)
46
47    XSError(PopCount(bypassVec) > 1.U, p"bypass mask ${Binary(bypassVec.asUInt)} is not one-hot\n")
48    bypassVec.zipWithIndex.map { case (m, i) =>
49      XSDebug(bypassVec(i), p"target($debugIndex) bypassed from $i:0x${Hexadecimal(bypassData(i))}\n")
50    }
51
52    target
53  }
54
55}
56
57// Bypass at the right: RegNext(data) and compute the bypassed data at the next clock cycle
58class BypassNetworkRight(numWays: Int, numBypass: Int, dataBits: Int)(implicit p: Parameters)
59  extends BypassNetwork(numWays, numBypass, dataBits) {
60
61  val last_cycle_hold = RegInit(false.B)
62  last_cycle_hold := io.hold
63
64  val target_reg = Reg(Vec(numWays, UInt(dataBits.W)))
65  val bypass_reg = Reg(Vec(numBypass, new BypassInfo(numWays, dataBits)))
66
67  // When last cycle holds the data, no need to update it.
68  when (io.hold && !last_cycle_hold) {
69    bypass_reg.map(_.valid.map(_ := false.B))
70    target_reg := io.target
71  }.elsewhen(!io.hold) {
72    target_reg := io.source
73    for ((by_reg, by_io) <- bypass_reg.zip(io.bypass)) {
74      by_reg.data := by_io.data
75      by_reg.valid := by_io.valid
76    }
77  }
78
79  // bypass data to target
80  for (i <- 0 until numWays) {
81    io.target(i) := doBypass(bypass_reg.map(_.valid(i)), bypass_reg.map(_.data), target_reg(i))
82  }
83
84}
85
86// Bypass at the left: compute the bypassed data and RegNext(bypassed_data)
87class BypassNetworkLeft(numWays: Int, numBypass: Int, dataBits: Int)(implicit p: Parameters)
88  extends BypassNetwork(numWays, numBypass, dataBits) {
89
90  val bypassedData = Reg(io.target.cloneType)
91
92  when (!io.hold) {
93    for ((by, i) <- bypassedData.zipWithIndex) {
94      by := doBypass(io.bypass.map(_.valid(i)), io.bypass.map(_.data), io.source(i))
95    }
96  }
97
98  io.target := bypassedData
99
100}
101
102object BypassNetwork {
103  def apply(
104    numWays: Int,
105    numBypass: Int,
106    dataBits: Int,
107    optFirstStage: Boolean
108  )(implicit p: Parameters): BypassNetwork = {
109    if (optFirstStage) {
110      Module(new BypassNetworkLeft(numWays, numBypass, dataBits))
111    }
112    else {
113      Module(new BypassNetworkRight(numWays, numBypass, dataBits))
114    }
115  }
116}
117