1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend.issue 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import xiangshan._ 23import utils._ 24 25 26class BypassInfo(numWays: Int, dataBits: Int) extends Bundle { 27 val valid = Vec(numWays, Bool()) 28 val data = UInt(dataBits.W) 29 30 override def cloneType: BypassInfo.this.type = 31 new BypassInfo(numWays, dataBits).asInstanceOf[this.type] 32} 33 34class BypassNetworkIO(numWays: Int, numBypass: Int, dataBits: Int) extends Bundle { 35 val hold = Input(Bool()) 36 val source = Vec(numWays, Input(UInt(dataBits.W))) 37 val target = Vec(numWays, Output(UInt(dataBits.W))) 38 val bypass = Vec(numBypass, Input(new BypassInfo(numWays, dataBits))) 39 40 override def cloneType: BypassNetworkIO.this.type = 41 new BypassNetworkIO(numWays, numBypass, dataBits).asInstanceOf[this.type] 42} 43 44class BypassNetwork(numWays: Int, numBypass: Int, dataBits: Int)(implicit p: Parameters) 45 extends XSModule { 46 47 val io = IO(new BypassNetworkIO(numWays, numBypass, dataBits)) 48 49 def doBypass(bypassValid: Seq[Bool], bypassData: Seq[UInt], baseData: UInt, debugIndex: Int = 0): UInt = { 50 val bypassVec = VecInit(bypassValid) 51 val target = Mux(bypassVec.asUInt.orR, Mux1H(bypassValid, bypassData), baseData) 52 53 XSError(PopCount(bypassVec) > 1.U, p"bypass mask ${Binary(bypassVec.asUInt)} is not one-hot\n") 54 bypassVec.zipWithIndex.map { case (m, i) => 55 XSDebug(bypassVec(i), p"target($debugIndex) bypassed from $i:0x${Hexadecimal(bypassData(i))}\n") 56 } 57 58 target 59 } 60 61} 62 63// Bypass at the right: RegNext(data) and compute the bypassed data at the next clock cycle 64class BypassNetworkRight(numWays: Int, numBypass: Int, dataBits: Int)(implicit p: Parameters) 65 extends BypassNetwork(numWays, numBypass, dataBits) { 66 67 val target_reg = Reg(Vec(numWays, UInt(dataBits.W))) 68 val bypass_reg = Reg(Vec(numBypass, new BypassInfo(numWays, dataBits))) 69 70 when (io.hold) { 71 target_reg := io.target 72 bypass_reg.map(_.valid.map(_ := false.B)) 73 }.otherwise { 74 target_reg := io.source 75 for ((by_reg, by_io) <- bypass_reg.zip(io.bypass)) { 76 by_reg.data := by_io.data 77 by_reg.valid := by_io.valid 78 } 79 } 80 81 // bypass data to target 82 for (i <- 0 until numWays) { 83 io.target(i) := doBypass(bypass_reg.map(_.valid(i)), bypass_reg.map(_.data), target_reg(i)) 84 } 85 86} 87 88// Bypass at the left: compute the bypassed data and RegNext(bypassed_data) 89class BypassNetworkLeft(numWays: Int, numBypass: Int, dataBits: Int)(implicit p: Parameters) 90 extends BypassNetwork(numWays, numBypass, dataBits) { 91 92 val bypassedData = Reg(io.target.cloneType) 93 94 when (!io.hold) { 95 for ((by, i) <- bypassedData.zipWithIndex) { 96 by := doBypass(io.bypass.map(_.valid(i)), io.bypass.map(_.data), io.source(i)) 97 } 98 } 99 100 io.target := bypassedData 101 102} 103 104object BypassNetwork { 105 def apply(numWays: Int, numBypass: Int, dataBits: Int, optFirstStage: Boolean)(implicit p: Parameters) = { 106 Module(new BypassNetworkLeft(numWays, numBypass, dataBits)) 107 } 108} 109