1package xiangshan.backend.fu.wrapper 2 3import chipsalliance.rocketchip.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import utils.XSError 7import xiangshan.backend.fu.FuConfig 8import xiangshan.backend.fu.vector.Bundles.VSew 9import xiangshan.backend.fu.vector.utils.VecDataSplitModule 10import xiangshan.backend.fu.vector.{Mgu, Utils, VecPipedFuncUnit, VecSrcTypeModule} 11import yunsuan.VialuFixType 12import yunsuan.encoding.Opcode.VimacOpcode 13import yunsuan.encoding.{VdType, Vs1IntType, Vs2IntType} 14import yunsuan.{OpType, VimacType} 15import yunsuan.vector.mac.VIMac64b 16 17class VIMacSrcTypeModule extends VecSrcTypeModule { 18 19 private val opcode = VimacType.getOpcode(fuOpType) 20 private val vs2Sign = VimacType.vs2Sign(fuOpType) 21 private val vs1Sign = VimacType.vs1Sign(fuOpType) 22 private val vdSign = VimacType.vdSign(fuOpType) 23 private val format = VimacType.getFormat(fuOpType) 24 private val widen = format === VimacType.FMT.VVW 25 26 private val vs2IntType = Cat(0.U(1.W), vs2Sign) 27 private val vs1IntType = Cat(0.U(1.W), vs1Sign) 28 private val vdIntType = Cat(0.U(1.W), vdSign) 29 30 private val vsewX2 = vsew + 1.U 31 32 private val vs2Type = Cat(vs2IntType, vsew) 33 private val vs1Type = Cat(vs1IntType, vsew) 34 private val vdType = Cat( vdIntType, Mux(widen, vsewX2, vsew)) 35 36 private val widenIllegal = widen && vsewX2 === VSew.e8 37 38 io.out.illegal := widenIllegal 39 io.out.vs2Type := vs2Type 40 io.out.vs1Type := vs1Type 41 io.out.vdType := vdType 42} 43 44class VIMacU(cfg: FuConfig)(implicit p: Parameters) extends VecPipedFuncUnit(cfg) { 45 XSError(io.in.valid && io.in.bits.ctrl.fuOpType === VimacType.dummy, "VialuF OpType not supported") 46 47 // params alias 48 private val dataWidth = cfg.dataBits 49 private val dataWidthOfDataModule = 64 50 private val numVecModule = dataWidth / dataWidthOfDataModule 51 52 // io alias 53 private val opcode = VimacType.getOpcode(fuOpType) 54 private val format = VimacType.getFormat(fuOpType) 55 private val widen = format === VimacType.FMT.VVW 56 57 // modules 58 private val typeMod = Module(new VIMacSrcTypeModule) 59 private val vs2Split = Module(new VecDataSplitModule(dataWidth, dataWidthOfDataModule)) 60 private val vs1Split = Module(new VecDataSplitModule(dataWidth, dataWidthOfDataModule)) 61 private val oldVdSplit = Module(new VecDataSplitModule(dataWidth, dataWidthOfDataModule)) 62 private val vimacs = Seq.fill(numVecModule)(Module(new VIMac64b)) 63 private val mgu = Module(new Mgu(dataWidth)) 64 65 /** 66 * [[typeMod]]'s in connection 67 */ 68 typeMod.io.in.fuOpType := fuOpType 69 typeMod.io.in.vsew := vsew 70 typeMod.io.in.isReverse := isReverse 71 typeMod.io.in.isExt := isExt 72 typeMod.io.in.isDstMask := vecCtrl.isDstMask 73 typeMod.io.in.isMove := isMove 74 75 /** 76 * In connection of [[vs2Split]], [[vs1Split]] and [[oldVdSplit]] 77 */ 78 vs2Split.io.inVecData := vs2 79 vs1Split.io.inVecData := vs1 80 oldVdSplit.io.inVecData := oldVd 81 82 /** 83 * [[vimacs]]'s in connection 84 */ 85 private val vs2VecUsed: Vec[UInt] = Mux(widen, VecInit(vs2Split.io.outVec32b.take(numVecModule)), vs2Split.io.outVec64b) 86 private val vs1VecUsed: Vec[UInt] = Mux(widen, VecInit(vs1Split.io.outVec32b.take(numVecModule)), vs1Split.io.outVec64b) 87 private val oldVdVecUsed: Vec[UInt] = WireInit(oldVdSplit.io.outVec64b) 88 89 vimacs.zipWithIndex.foreach { 90 case (mod, i) => 91 mod.io.info.vm := vm 92 mod.io.info.ma := vma 93 mod.io.info.ta := vta 94 mod.io.info.vlmul := vlmul 95 mod.io.info.vl := srcVConfig.vl 96 mod.io.info.vstart := vstart 97 mod.io.info.uopIdx := vuopIdx 98 mod.io.info.vxrm := vxrm 99 mod.io.srcType(0) := typeMod.io.out.vs2Type 100 mod.io.srcType(1) := typeMod.io.out.vs1Type 101 mod.io.vdType := typeMod.io.out.vdType 102 mod.io.vs1 := vs1VecUsed(i) 103 mod.io.vs2 := vs2VecUsed(i) 104 mod.io.oldVd := oldVdVecUsed(i) 105 mod.io.highHalf := VimacOpcode.highHalf(opcode) 106 mod.io.isMacc := VimacOpcode.isMacc(opcode) 107 mod.io.isSub := VimacOpcode.isSub(opcode) 108 mod.io.widen := widen 109 mod.io.isFixP := VimacOpcode.isFixP(opcode) 110 } 111 112 /** 113 * [[mgu]]'s in connection 114 */ 115 private val vd = Cat(vimacs.reverse.map(_.io.vd)) 116 mgu.io.in.vd := vd 117 mgu.io.in.oldVd := oldVd 118 mgu.io.in.mask := srcMask 119 mgu.io.in.info.ta := vta 120 mgu.io.in.info.ma := vma 121 mgu.io.in.info.vl := vl 122 mgu.io.in.info.vstart := vstart 123 mgu.io.in.info.eew := vsew 124 mgu.io.in.info.vdIdx := vuopIdx 125 126 io.out.bits.res.data := mgu.io.out.vd 127 io.out.bits.res.vxsat.get := vimacs.map(_.io.vxsat).reduce(_ | _).orR 128} 129