1package xiangshan.backend.fu.wrapper 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import utility.XSError 7import xiangshan.backend.fu.FuConfig 8import xiangshan.backend.fu.vector.Bundles.VSew 9import xiangshan.backend.fu.vector.{Mgu, VecNonPipedFuncUnit} 10import xiangshan.backend.rob.RobPtr 11import xiangshan.ExceptionNO 12import yunsuan.VidivType 13import yunsuan.vector.VectorIdiv 14 15class VIDiv(cfg: FuConfig)(implicit p: Parameters) extends VecNonPipedFuncUnit(cfg) { 16 XSError(io.in.valid && io.in.bits.ctrl.fuOpType === VidivType.dummy, "Vfdiv OpType not supported") 17 18 // params alias 19 private val dataWidth = cfg.destDataBits 20 21 // modules 22 private val vidiv = Module(new VectorIdiv) 23 private val mgu = Module(new Mgu(dataWidth)) 24 25 private val thisRobIdx = Wire(new RobPtr) 26 when(io.in.ready){ 27 thisRobIdx := io.in.bits.ctrl.robIdx 28 }.otherwise{ 29 thisRobIdx := outCtrl.robIdx 30 } 31 32 /** 33 * [[vidiv]]'s in connection 34 */ 35 vidiv.io match { 36 case subIO => 37 subIO.div_in_valid := io.in.valid 38 subIO.div_out_ready := io.out.ready & io.out.valid 39 subIO.sew := vsew 40 subIO.sign := VidivType.isSigned(fuOpType) 41 subIO.dividend_v := vs2 42 subIO.divisor_v := vs1 43 subIO.flush := thisRobIdx.needFlush(io.flush) 44 } 45 46 io.in.ready := vidiv.io.div_in_ready 47 io.out.valid := vidiv.io.div_out_valid 48 49 private val outFuOpType = outCtrl.fuOpType 50 private val outIsDiv = VidivType.isDiv(outFuOpType) 51 private val resultData = Mux(outIsDiv, vidiv.io.div_out_q_v, vidiv.io.div_out_rem_v) 52 private val notModifyVd = outVl === 0.U 53 54 mgu.io.in.vd := resultData 55 mgu.io.in.oldVd := outOldVd 56 mgu.io.in.mask := outSrcMask 57 mgu.io.in.info.ta := outVecCtrl.vta 58 mgu.io.in.info.ma := outVecCtrl.vma 59 mgu.io.in.info.vl := outVl 60 mgu.io.in.info.vlmul := outVecCtrl.vlmul 61 mgu.io.in.info.valid := io.out.valid 62 mgu.io.in.info.vstart := outVecCtrl.vstart 63 mgu.io.in.info.eew := outVecCtrl.vsew 64 mgu.io.in.info.vsew := outVecCtrl.vsew 65 mgu.io.in.info.vdIdx := outVecCtrl.vuopIdx 66 mgu.io.in.info.narrow := outVecCtrl.isNarrow 67 mgu.io.in.info.dstMask := outVecCtrl.isDstMask 68 mgu.io.in.isIndexedVls := false.B 69 io.out.bits.res.data := Mux(notModifyVd, outOldVd, mgu.io.out.vd) 70 io.out.bits.ctrl.exceptionVec.get(ExceptionNO.illegalInstr) := mgu.io.out.illegal 71} 72