1package xiangshan.backend.fu.wrapper 2 3import chipsalliance.rocketchip.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import utils.XSError 7import xiangshan.backend.fu.FuConfig 8import xiangshan.backend.fu.vector.Bundles.VSew 9import xiangshan.backend.fu.vector.utils.VecDataSplitModule 10import xiangshan.backend.fu.vector.{Mgu, Utils, VecPipedFuncUnit, VecSrcTypeModule} 11import yunsuan.VfpuType 12import yunsuan.encoding.Opcode.VimacOpcode 13import yunsuan.encoding.{VdType, Vs1IntType, Vs2IntType} 14import yunsuan.{OpType, VimacType} 15import yunsuan.vector.VectorFloatFMA 16import yunsuan.vector.mac.VIMac64b 17 18class VFMA(cfg: FuConfig)(implicit p: Parameters) extends VecPipedFuncUnit(cfg) { 19 XSError(io.in.valid && io.in.bits.ctrl.fuOpType === VfpuType.dummy, "Vfalu OpType not supported") 20 21 // params alias 22 private val dataWidth = cfg.dataBits 23 private val dataWidthOfDataModule = 64 24 private val numVecModule = dataWidth / dataWidthOfDataModule 25 26 // io alias 27 private val opcode = fuOpType(3,0) 28 private val resWiden = fuOpType(4) 29 30 // modules 31 private val vfmas = Seq.fill(numVecModule)(Module(new VectorFloatFMA)) 32 private val vs2Split = Module(new VecDataSplitModule(dataWidth, dataWidthOfDataModule)) 33 private val vs1Split = Module(new VecDataSplitModule(dataWidth, dataWidthOfDataModule)) 34 private val oldVdSplit = Module(new VecDataSplitModule(dataWidth, dataWidthOfDataModule)) 35 private val mgu = Module(new Mgu(dataWidth)) 36 37 /** 38 * In connection of [[vs2Split]], [[vs1Split]] and [[oldVdSplit]] 39 */ 40 vs2Split.io.inVecData := vs2 41 vs1Split.io.inVecData := vs1 42 oldVdSplit.io.inVecData := oldVd 43 44 /** 45 * [[vfmas]]'s in connection 46 */ 47 // Vec(vs2(31,0), vs2(63,32), vs2(95,64), vs2(127,96)) ==> 48 // Vec( 49 // Cat(vs2(95,64), vs2(31,0)), 50 // Cat(vs2(127,96), vs2(63,32)), 51 // ) 52 private val vs2GroupedVec: Vec[UInt] = VecInit(vs2Split.io.outVec32b.zipWithIndex.groupBy(_._2 % 2).map(x => x._1 -> x._2.map(_._1)).values.map(x => Cat(x.reverse)).toSeq) 53 private val vs1GroupedVec: Vec[UInt] = VecInit(vs1Split.io.outVec32b.zipWithIndex.groupBy(_._2 % 2).map(x => x._1 -> x._2.map(_._1)).values.map(x => Cat(x.reverse)).toSeq) 54 private val resultData = Wire(Vec(numVecModule, UInt(dataWidthOfDataModule.W))) 55 private val fflagsData = Wire(Vec(numVecModule, UInt(20.W))) 56 57 vfmas.zipWithIndex.foreach { 58 case (mod, i) => 59 mod.io.fp_a := vs2Split.io.outVec64b(i) 60 mod.io.fp_b := vs1Split.io.outVec64b(i) 61 mod.io.fp_c := oldVdSplit.io.outVec64b(i) 62 mod.io.widen_a := Cat(vs2Split.io.outVec32b(i+numVecModule), vs2Split.io.outVec32b(i)) 63 mod.io.widen_b := Cat(vs1Split.io.outVec32b(i+numVecModule), vs1Split.io.outVec32b(i)) 64 mod.io.frs1 := 0.U // already vf -> vv 65 mod.io.is_frs1 := false.B // already vf -> vv 66 mod.io.uop_idx := vuopIdx(0) 67 mod.io.is_vec := true.B // Todo 68 mod.io.round_mode := frm 69 mod.io.fp_format := Mux(resWiden, vsew + 1.U, vsew) 70 mod.io.res_widening := resWiden 71 mod.io.op_code := opcode 72 resultData(i) := mod.io.fp_result 73 fflagsData(i) := mod.io.fflags 74 } 75 76 val resultDataUInt = resultData.asUInt 77 private val outEew = Mux(RegNext(resWiden), outVecCtrl.vsew + 1.U, outVecCtrl.vsew) 78 mgu.io.in.vd := resultDataUInt 79 mgu.io.in.oldVd := outOldVd 80 mgu.io.in.mask := outSrcMask 81 mgu.io.in.info.ta := outVecCtrl.vta 82 mgu.io.in.info.ma := outVecCtrl.vma 83 mgu.io.in.info.vl := outVl 84 mgu.io.in.info.vstart := outVecCtrl.vstart 85 mgu.io.in.info.eew := outEew 86 mgu.io.in.info.vdIdx := outVecCtrl.vuopIdx 87 mgu.io.in.info.narrow := outVecCtrl.isNarrow 88 mgu.io.in.info.dstMask := outVecCtrl.isDstMask 89 io.out.bits.res.data := mgu.io.out.vd 90 91 val allFFlagsEn = Wire(Vec(4 * numVecModule, Bool())) 92 val outSrcMaskRShift = Wire(UInt((4 * numVecModule).W)) 93 outSrcMaskRShift := (outSrcMask >> (outVecCtrl.vuopIdx * (16.U >> outVecCtrl.vsew)))(4 * numVecModule - 1, 0) 94 val f16FFlagsEn = outSrcMaskRShift 95 val f32FFlagsEn = Wire(Vec(numVecModule, UInt(4.W))) 96 for (i <- 0 until numVecModule) { 97 f32FFlagsEn(i) := Cat(Fill(2, 1.U), outSrcMaskRShift(2 * i + 1, 2 * i)) 98 } 99 val f64FFlagsEn = Wire(Vec(numVecModule, UInt(4.W))) 100 for (i <- 0 until numVecModule) { 101 f64FFlagsEn(i) := Cat(Fill(3, 1.U), outSrcMaskRShift(i)) 102 } 103 val fflagsEn = Mux1H( 104 Seq( 105 (outVecCtrl.vsew === 1.U) -> f16FFlagsEn.asUInt, 106 (outVecCtrl.vsew === 2.U) -> f32FFlagsEn.asUInt, 107 (outVecCtrl.vsew === 3.U) -> f64FFlagsEn.asUInt 108 ) 109 ) 110 allFFlagsEn := fflagsEn.asTypeOf(allFFlagsEn) 111 112 val allFFlags = fflagsData.asTypeOf(Vec(4 * numVecModule, UInt(5.W))) 113 val outFFlags = allFFlagsEn.zip(allFFlags).map { 114 case (en, fflags) => Mux(en, fflags, 0.U(5.W)) 115 }.reduce(_ | _) 116 io.out.bits.res.fflags.get := outFFlags 117} 118