1package xiangshan.backend.fu.wrapper 2 3import chipsalliance.rocketchip.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import utils.XSError 7import xiangshan.backend.fu.FuConfig 8import xiangshan.backend.fu.vector.Bundles.VSew 9import xiangshan.backend.fu.vector.utils.VecDataSplitModule 10import xiangshan.backend.fu.vector.{Mgu, Utils, VecPipedFuncUnit, VecSrcTypeModule} 11import yunsuan.VfpuType 12import yunsuan.encoding.Opcode.VimacOpcode 13import yunsuan.encoding.{VdType, Vs1IntType, Vs2IntType} 14import yunsuan.{OpType, VimacType} 15import yunsuan.vector.VectorFloatDivider 16import yunsuan.vector.mac.VIMac64b 17 18class VFDivSqrt(cfg: FuConfig)(implicit p: Parameters) extends VecPipedFuncUnit(cfg) { //here extends VecPipedFuncUnit has error 19 XSError(io.in.valid && io.in.bits.ctrl.fuOpType === VfpuType.dummy, "Vfdiv OpType not supported") 20 21 // params alias 22 private val dataWidth = cfg.dataBits 23 private val dataWidthOfDataModule = 64 24 private val numVecModule = dataWidth / dataWidthOfDataModule 25 26 // io alias 27 private val opcode = fuOpType(0) 28 29 // modules 30 private val vfdivs = Seq.fill(numVecModule)(Module(new VectorFloatDivider)) 31 private val vs2Split = Module(new VecDataSplitModule(dataWidth, dataWidthOfDataModule)) 32 private val vs1Split = Module(new VecDataSplitModule(dataWidth, dataWidthOfDataModule)) 33 private val oldVdSplit = Module(new VecDataSplitModule(dataWidth, dataWidthOfDataModule)) 34// private val mgu = Module(new Mgu(dataWidth)) 35 36 /** 37 * In connection of [[vs2Split]], [[vs1Split]] and [[oldVdSplit]] 38 */ 39 vs2Split.io.inVecData := vs2 40 vs1Split.io.inVecData := vs1 41 oldVdSplit.io.inVecData := oldVd 42 43 /** 44 * [[vfdivs]]'s in connection 45 */ 46 // Vec(vs2(31,0), vs2(63,32), vs2(95,64), vs2(127,96)) ==> 47 // Vec( 48 // Cat(vs2(95,64), vs2(31,0)), 49 // Cat(vs2(127,96), vs2(63,32)), 50 // ) 51 private val vs2GroupedVec: Vec[UInt] = VecInit(vs2Split.io.outVec32b.zipWithIndex.groupBy(_._2 % 2).map(x => x._1 -> x._2.map(_._1)).values.map(x => Cat(x.reverse)).toSeq) 52 private val vs1GroupedVec: Vec[UInt] = VecInit(vs1Split.io.outVec32b.zipWithIndex.groupBy(_._2 % 2).map(x => x._1 -> x._2.map(_._1)).values.map(x => Cat(x.reverse)).toSeq) 53 54 vfdivs.zipWithIndex.foreach { 55 case (mod, i) => 56 mod.io.start_valid_i := io.in.valid 57 mod.io.finish_ready_i := io.out.ready 58 mod.io.flush_i := 0.U 59 mod.io.fp_format_i := vsew 60 mod.io.opa_i := vs2Split.io.outVec64b(i) 61 mod.io.opb_i := vs1Split.io.outVec64b(i) 62 mod.io.frs2_i := 0.U // already vf -> vv 63 mod.io.frs1_i := 0.U // already vf -> vv 64 mod.io.is_frs2_i := false.B // already vf -> vv 65 mod.io.is_frs1_i := false.B // already vf -> vv 66 mod.io.is_sqrt_i := opcode 67 mod.io.rm_i := frm 68 mod.io.is_vec_i := true.B // Todo 69 70 io.in.ready := mod.io.start_ready_o 71 io.out.valid := mod.io.finish_valid_o 72 } 73 74 io.out.bits.res.data := vfdivs.map(_.io.fpdiv_res_o).reduceRight(Cat(_,_)) 75 val allFFlagsEn = Wire(Vec(4*numVecModule,Bool())) 76 allFFlagsEn.foreach(en => en := true.B) // Todo 77 val allFFlags = vfdivs.map(_.io.fflags_o).reduceRight(Cat(_,_)).asTypeOf(Vec(4*numVecModule,UInt(5.W))) 78 val outFFlags = allFFlagsEn.zip(allFFlags).map{ 79 case(en,fflags) => Mux(en, fflags, 0.U(5.W)) 80 }.reduce(_ | _) 81 io.out.bits.res.fflags.get := outFFlags 82} 83