1package xiangshan.backend.fu.wrapper 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import utility.XSError 7import xiangshan.backend.fu.FuConfig 8import xiangshan.backend.fu.vector.Bundles.VSew 9import xiangshan.backend.fu.vector.utils.VecDataSplitModule 10import xiangshan.backend.fu.vector.{Mgu, VecNonPipedFuncUnit} 11import xiangshan.backend.rob.RobPtr 12import xiangshan.ExceptionNO 13import yunsuan.VfpuType 14import yunsuan.vector.VectorFloatDivider 15 16class VFDivSqrt(cfg: FuConfig)(implicit p: Parameters) extends VecNonPipedFuncUnit(cfg) { 17 XSError(io.in.valid && io.in.bits.ctrl.fuOpType === VfpuType.dummy, "Vfdiv OpType not supported") 18 19 // params alias 20 private val dataWidth = cfg.destDataBits 21 private val dataWidthOfDataModule = 64 22 private val numVecModule = dataWidth / dataWidthOfDataModule 23 24 // io alias 25 private val opcode = fuOpType(0) 26 27 // modules 28 private val vfdivs = Seq.fill(numVecModule)(Module(new VectorFloatDivider)) 29 private val vs2Split = Module(new VecDataSplitModule(dataWidth, dataWidthOfDataModule)) 30 private val vs1Split = Module(new VecDataSplitModule(dataWidth, dataWidthOfDataModule)) 31 private val oldVdSplit = Module(new VecDataSplitModule(dataWidth, dataWidthOfDataModule)) 32 private val mgu = Module(new Mgu(dataWidth)) 33 34 /** 35 * In connection of [[vs2Split]], [[vs1Split]] and [[oldVdSplit]] 36 */ 37 vs2Split.io.inVecData := vs2 38 vs1Split.io.inVecData := vs1 39 oldVdSplit.io.inVecData := oldVd 40 41 /** 42 * [[vfdivs]]'s in connection 43 */ 44 private val vs2GroupedVec: Vec[UInt] = VecInit(vs2Split.io.outVec32b.zipWithIndex.groupBy(_._2 % 2).map(x => x._1 -> x._2.map(_._1)).values.map(x => Cat(x.reverse)).toSeq) 45 private val vs1GroupedVec: Vec[UInt] = VecInit(vs1Split.io.outVec32b.zipWithIndex.groupBy(_._2 % 2).map(x => x._1 -> x._2.map(_._1)).values.map(x => Cat(x.reverse)).toSeq) 46 private val resultData = Wire(Vec(numVecModule, UInt(dataWidthOfDataModule.W))) 47 private val fflagsData = Wire(Vec(numVecModule, UInt(20.W))) 48 val fp_aIsFpCanonicalNAN = Wire(Vec(numVecModule, Bool())) 49 val fp_bIsFpCanonicalNAN = Wire(Vec(numVecModule, Bool())) 50 51 val thisRobIdx = Wire(new RobPtr) 52 when(io.in.ready){ 53 thisRobIdx := io.in.bits.ctrl.robIdx 54 }.otherwise{ 55 thisRobIdx := outCtrl.robIdx 56 } 57 vfdivs.zipWithIndex.foreach { 58 case (mod, i) => 59 mod.io.start_valid_i := io.in.valid 60 mod.io.finish_ready_i := io.out.ready & io.out.valid 61 mod.io.flush_i := thisRobIdx.needFlush(io.flush) 62 mod.io.fp_format_i := vsew 63 mod.io.opa_i := vs2Split.io.outVec64b(i) 64 mod.io.opb_i := vs1Split.io.outVec64b(i) 65 mod.io.frs2_i := 0.U // already vf -> vv 66 mod.io.frs1_i := 0.U // already vf -> vv 67 mod.io.is_frs2_i := false.B // already vf -> vv 68 mod.io.is_frs1_i := false.B // already vf -> vv 69 mod.io.is_sqrt_i := opcode 70 mod.io.rm_i := rm 71 mod.io.is_vec_i := true.B // Todo 72 resultData(i) := mod.io.fpdiv_res_o 73 fflagsData(i) := mod.io.fflags_o 74 fp_aIsFpCanonicalNAN(i) := vecCtrl.fpu.isFpToVecInst & ( 75 ((vsew === VSew.e32) & (!vs2Split.io.outVec64b(i).head(32).andR)) | 76 ((vsew === VSew.e16) & (!vs2Split.io.outVec64b(i).head(48).andR)) 77 ) 78 fp_bIsFpCanonicalNAN(i) := vecCtrl.fpu.isFpToVecInst & ( 79 ((vsew === VSew.e32) & (!vs1Split.io.outVec64b(i).head(32).andR)) | 80 ((vsew === VSew.e16) & (!vs1Split.io.outVec64b(i).head(48).andR)) 81 ) 82 mod.io.fp_aIsFpCanonicalNAN := fp_aIsFpCanonicalNAN(i) 83 mod.io.fp_bIsFpCanonicalNAN := fp_bIsFpCanonicalNAN(i) 84 } 85 86 io.in.ready := vfdivs.map(_.io.start_ready_o).reduce(_&_) 87 io.out.valid := vfdivs.map(_.io.finish_valid_o).reduce(_&_) 88 val outEew = outVecCtrl.vsew 89 val outVuopidx = outVecCtrl.vuopIdx(2, 0) 90 val vlMax = ((VLEN / 8).U >> outEew).asUInt 91 val lmulAbs = Mux(outVecCtrl.vlmul(2), (~outVecCtrl.vlmul(1, 0)).asUInt + 1.U, outVecCtrl.vlmul(1, 0)) 92 val outVlFix = Mux(outVecCtrl.fpu.isFpToVecInst, 1.U, outVl) 93 val vlMaxAllUop = Wire(outVl.cloneType) 94 vlMaxAllUop := Mux(outVecCtrl.vlmul(2), vlMax >> lmulAbs, vlMax << lmulAbs).asUInt 95 val vlMaxThisUop = Mux(outVecCtrl.vlmul(2), vlMax >> lmulAbs, vlMax).asUInt 96 val vlSetThisUop = Mux(outVlFix > outVuopidx * vlMaxThisUop, outVlFix - outVuopidx * vlMaxThisUop, 0.U) 97 val vlThisUop = Wire(UInt(3.W)) 98 vlThisUop := Mux(vlSetThisUop < vlMaxThisUop, vlSetThisUop, vlMaxThisUop) 99 val vlMaskRShift = Wire(UInt((4 * numVecModule).W)) 100 vlMaskRShift := Fill(4 * numVecModule, 1.U(1.W)) >> ((4 * numVecModule).U - vlThisUop) 101 102 private val needNoMask = outVecCtrl.fpu.isFpToVecInst 103 val maskToMgu = Mux(needNoMask, allMaskTrue, outSrcMask) 104 val allFFlagsEn = Wire(Vec(4 * numVecModule, Bool())) 105 val outSrcMaskRShift = Wire(UInt((4 * numVecModule).W)) 106 outSrcMaskRShift := (maskToMgu >> (outVecCtrl.vuopIdx(2, 0) * vlMax))(4 * numVecModule - 1, 0) 107 val f16FFlagsEn = outSrcMaskRShift 108 val f32FFlagsEn = Wire(Vec(numVecModule, UInt(4.W))) 109 val f64FFlagsEn = Wire(Vec(numVecModule, UInt(4.W))) 110 val f16VlMaskEn = vlMaskRShift 111 val f32VlMaskEn = Wire(Vec(numVecModule, UInt(4.W))) 112 val f64VlMaskEn = Wire(Vec(numVecModule, UInt(4.W))) 113 for (i <- 0 until numVecModule) { 114 f32FFlagsEn(i) := Cat(Fill(2, 0.U), outSrcMaskRShift(2 * i + 1, 2 * i)) 115 f64FFlagsEn(i) := Cat(Fill(3, 0.U), outSrcMaskRShift(i)) 116 f32VlMaskEn(i) := Cat(Fill(2, 0.U), vlMaskRShift(2 * i + 1, 2 * i)) 117 f64VlMaskEn(i) := Cat(Fill(3, 0.U), vlMaskRShift(i)) 118 } 119 val fflagsEn = Mux1H( 120 Seq( 121 (outEew === 1.U) -> f16FFlagsEn.asUInt, 122 (outEew === 2.U) -> f32FFlagsEn.asUInt, 123 (outEew === 3.U) -> f64FFlagsEn.asUInt 124 ) 125 ) 126 val vlMaskEn = Mux1H( 127 Seq( 128 (outEew === 1.U) -> f16VlMaskEn.asUInt, 129 (outEew === 2.U) -> f32VlMaskEn.asUInt, 130 (outEew === 3.U) -> f64VlMaskEn.asUInt 131 ) 132 ) 133 allFFlagsEn := (fflagsEn & vlMaskEn).asTypeOf(allFFlagsEn) 134 135 val allFFlags = fflagsData.asTypeOf(Vec(4 * numVecModule, UInt(5.W))) 136 val outFFlags = allFFlagsEn.zip(allFFlags).map { 137 case (en, fflags) => Mux(en, fflags, 0.U(5.W)) 138 }.reduce(_ | _) 139 io.out.bits.res.fflags.get := outFFlags 140 141 val resultDataUInt = resultData.asUInt 142 mgu.io.in.vd := resultDataUInt 143 mgu.io.in.oldVd := outOldVd 144 mgu.io.in.mask := maskToMgu 145 mgu.io.in.info.ta := outVecCtrl.vta 146 mgu.io.in.info.ma := outVecCtrl.vma 147 mgu.io.in.info.vl := Mux(outVecCtrl.fpu.isFpToVecInst, 1.U, outVl) 148 mgu.io.in.info.vlmul := outVecCtrl.vlmul 149 mgu.io.in.info.valid := io.out.valid 150 mgu.io.in.info.vstart := Mux(outVecCtrl.fpu.isFpToVecInst, 0.U, outVecCtrl.vstart) 151 mgu.io.in.info.eew := outVecCtrl.vsew 152 mgu.io.in.info.vsew := outVecCtrl.vsew 153 mgu.io.in.info.vdIdx := outVecCtrl.vuopIdx 154 mgu.io.in.info.narrow := outVecCtrl.isNarrow 155 mgu.io.in.info.dstMask := outVecCtrl.isDstMask 156 mgu.io.in.isIndexedVls := false.B 157 io.out.bits.res.data := mgu.io.out.vd 158 io.out.bits.ctrl.exceptionVec.get(ExceptionNO.illegalInstr) := mgu.io.out.illegal 159} 160