1package xiangshan.backend.fu.wrapper 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import utils.XSError 7import xiangshan.backend.fu.FuConfig 8import xiangshan.backend.fu.vector.Bundles.VSew 9import xiangshan.backend.fu.vector.utils.VecDataSplitModule 10import xiangshan.backend.fu.vector.{Mgu, VecNonPipedFuncUnit} 11import xiangshan.backend.rob.RobPtr 12import yunsuan.VfpuType 13import yunsuan.vector.VectorFloatDivider 14 15class VFDivSqrt(cfg: FuConfig)(implicit p: Parameters) extends VecNonPipedFuncUnit(cfg) { 16 XSError(io.in.valid && io.in.bits.ctrl.fuOpType === VfpuType.dummy, "Vfdiv OpType not supported") 17 18 // params alias 19 private val dataWidth = cfg.dataBits 20 private val dataWidthOfDataModule = 64 21 private val numVecModule = dataWidth / dataWidthOfDataModule 22 23 // io alias 24 private val opcode = fuOpType(0) 25 26 // modules 27 private val vfdivs = Seq.fill(numVecModule)(Module(new VectorFloatDivider)) 28 private val vs2Split = Module(new VecDataSplitModule(dataWidth, dataWidthOfDataModule)) 29 private val vs1Split = Module(new VecDataSplitModule(dataWidth, dataWidthOfDataModule)) 30 private val oldVdSplit = Module(new VecDataSplitModule(dataWidth, dataWidthOfDataModule)) 31 private val mgu = Module(new Mgu(dataWidth)) 32 33 /** 34 * In connection of [[vs2Split]], [[vs1Split]] and [[oldVdSplit]] 35 */ 36 vs2Split.io.inVecData := vs2 37 vs1Split.io.inVecData := vs1 38 oldVdSplit.io.inVecData := oldVd 39 40 /** 41 * [[vfdivs]]'s in connection 42 */ 43 private val vs2GroupedVec: Vec[UInt] = VecInit(vs2Split.io.outVec32b.zipWithIndex.groupBy(_._2 % 2).map(x => x._1 -> x._2.map(_._1)).values.map(x => Cat(x.reverse)).toSeq) 44 private val vs1GroupedVec: Vec[UInt] = VecInit(vs1Split.io.outVec32b.zipWithIndex.groupBy(_._2 % 2).map(x => x._1 -> x._2.map(_._1)).values.map(x => Cat(x.reverse)).toSeq) 45 private val resultData = Wire(Vec(numVecModule, UInt(dataWidthOfDataModule.W))) 46 private val fflagsData = Wire(Vec(numVecModule, UInt(20.W))) 47 val fp_aIsFpCanonicalNAN = Wire(Vec(numVecModule, Bool())) 48 val fp_bIsFpCanonicalNAN = Wire(Vec(numVecModule, Bool())) 49 50 val thisRobIdx = Wire(new RobPtr) 51 when(io.in.ready){ 52 thisRobIdx := io.in.bits.ctrl.robIdx 53 }.otherwise{ 54 thisRobIdx := outCtrl.robIdx 55 } 56 vfdivs.zipWithIndex.foreach { 57 case (mod, i) => 58 mod.io.start_valid_i := io.in.valid 59 mod.io.finish_ready_i := io.out.ready & io.out.valid 60 mod.io.flush_i := thisRobIdx.needFlush(io.flush) 61 mod.io.fp_format_i := vsew 62 mod.io.opa_i := vs2Split.io.outVec64b(i) 63 mod.io.opb_i := vs1Split.io.outVec64b(i) 64 mod.io.frs2_i := 0.U // already vf -> vv 65 mod.io.frs1_i := 0.U // already vf -> vv 66 mod.io.is_frs2_i := false.B // already vf -> vv 67 mod.io.is_frs1_i := false.B // already vf -> vv 68 mod.io.is_sqrt_i := opcode 69 mod.io.rm_i := frm 70 mod.io.is_vec_i := true.B // Todo 71 resultData(i) := mod.io.fpdiv_res_o 72 fflagsData(i) := mod.io.fflags_o 73 fp_aIsFpCanonicalNAN(i) := vecCtrl.fpu.isFpToVecInst & ( 74 ((vsew === VSew.e32) & (!vs2Split.io.outVec64b(i).head(32).andR)) | 75 ((vsew === VSew.e16) & (!vs2Split.io.outVec64b(i).head(48).andR)) 76 ) 77 fp_bIsFpCanonicalNAN(i) := vecCtrl.fpu.isFpToVecInst & ( 78 ((vsew === VSew.e32) & (!vs1Split.io.outVec64b(i).head(32).andR)) | 79 ((vsew === VSew.e16) & (!vs1Split.io.outVec64b(i).head(48).andR)) 80 ) 81 mod.io.fp_aIsFpCanonicalNAN := fp_aIsFpCanonicalNAN(i) 82 mod.io.fp_bIsFpCanonicalNAN := fp_bIsFpCanonicalNAN(i) 83 } 84 85 io.in.ready := vfdivs.map(_.io.start_ready_o).reduce(_&_) 86 io.out.valid := vfdivs.map(_.io.finish_valid_o).reduce(_&_) 87 val outEew = outVecCtrl.vsew 88 val outVuopidx = outVecCtrl.vuopIdx(2, 0) 89 val vlMax = ((VLEN / 8).U >> outEew).asUInt 90 val lmulAbs = Mux(outVecCtrl.vlmul(2), (~outVecCtrl.vlmul(1, 0)).asUInt + 1.U, outVecCtrl.vlmul(1, 0)) 91 val outVlFix = Mux(outVecCtrl.fpu.isFpToVecInst, 1.U, outVl) 92 val vlMaxAllUop = Wire(outVl.cloneType) 93 vlMaxAllUop := Mux(outVecCtrl.vlmul(2), vlMax >> lmulAbs, vlMax << lmulAbs).asUInt 94 val vlMaxThisUop = Mux(outVecCtrl.vlmul(2), vlMax >> lmulAbs, vlMax).asUInt 95 val vlSetThisUop = Mux(outVlFix > outVuopidx * vlMaxThisUop, outVlFix - outVuopidx * vlMaxThisUop, 0.U) 96 val vlThisUop = Wire(UInt(3.W)) 97 vlThisUop := Mux(vlSetThisUop < vlMaxThisUop, vlSetThisUop, vlMaxThisUop) 98 val vlMaskRShift = Wire(UInt((4 * numVecModule).W)) 99 vlMaskRShift := Fill(4 * numVecModule, 1.U(1.W)) >> ((4 * numVecModule).U - vlThisUop) 100 101 private val needNoMask = outVecCtrl.fpu.isFpToVecInst 102 val maskToMgu = Mux(needNoMask, allMaskTrue, outSrcMask) 103 val allFFlagsEn = Wire(Vec(4 * numVecModule, Bool())) 104 val outSrcMaskRShift = Wire(UInt((4 * numVecModule).W)) 105 outSrcMaskRShift := (maskToMgu >> (outVecCtrl.vuopIdx(2, 0) * vlMax))(4 * numVecModule - 1, 0) 106 val f16FFlagsEn = outSrcMaskRShift 107 val f32FFlagsEn = Wire(Vec(numVecModule, UInt(4.W))) 108 for (i <- 0 until numVecModule) { 109 f32FFlagsEn(i) := Cat(Fill(2, 1.U), outSrcMaskRShift(2 * i + 1, 2 * i)) 110 } 111 val f64FFlagsEn = Wire(Vec(numVecModule, UInt(4.W))) 112 for (i <- 0 until numVecModule) { 113 f64FFlagsEn(i) := Cat(Fill(3, 1.U), outSrcMaskRShift(i)) 114 } 115 val fflagsEn = Mux1H( 116 Seq( 117 (outEew === 1.U) -> f16FFlagsEn.asUInt, 118 (outEew === 2.U) -> f32FFlagsEn.asUInt, 119 (outEew === 3.U) -> f64FFlagsEn.asUInt 120 ) 121 ) 122 allFFlagsEn := (fflagsEn & vlMaskRShift).asTypeOf(allFFlagsEn) 123 124 val allFFlags = fflagsData.asTypeOf(Vec(4 * numVecModule, UInt(5.W))) 125 val outFFlags = allFFlagsEn.zip(allFFlags).map { 126 case (en, fflags) => Mux(en, fflags, 0.U(5.W)) 127 }.reduce(_ | _) 128 io.out.bits.res.fflags.get := outFFlags 129 130 val resultDataUInt = resultData.asUInt 131 mgu.io.in.vd := resultDataUInt 132 mgu.io.in.oldVd := outOldVd 133 mgu.io.in.mask := maskToMgu 134 mgu.io.in.info.ta := outVecCtrl.vta 135 mgu.io.in.info.ma := outVecCtrl.vma 136 mgu.io.in.info.vl := Mux(outVecCtrl.fpu.isFpToVecInst, 1.U, outVl) 137 mgu.io.in.info.vlmul := outVecCtrl.vlmul 138 mgu.io.in.info.valid := io.out.valid 139 mgu.io.in.info.vstart := Mux(outVecCtrl.fpu.isFpToVecInst, 0.U, outVecCtrl.vstart) 140 mgu.io.in.info.eew := outVecCtrl.vsew 141 mgu.io.in.info.vsew := outVecCtrl.vsew 142 mgu.io.in.info.vdIdx := outVecCtrl.vuopIdx 143 mgu.io.in.info.narrow := outVecCtrl.isNarrow 144 mgu.io.in.info.dstMask := outVecCtrl.isDstMask 145 io.out.bits.res.data := mgu.io.out.vd 146 147} 148