1package xiangshan.backend.fu.wrapper 2 3import chipsalliance.rocketchip.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import utils.XSError 7import xiangshan.backend.fu.FuConfig 8import xiangshan.backend.fu.vector.Bundles.VSew 9import xiangshan.backend.fu.vector.utils.VecDataSplitModule 10import xiangshan.backend.fu.vector.{Mgu, Utils, VecNonPipedFuncUnit, VecPipedFuncUnit, VecSrcTypeModule} 11import yunsuan.VfpuType 12import yunsuan.encoding.Opcode.VimacOpcode 13import yunsuan.encoding.{VdType, Vs1IntType, Vs2IntType} 14import yunsuan.{OpType, VimacType} 15import yunsuan.vector.VectorFloatDivider 16import yunsuan.vector.mac.VIMac64b 17 18class VFDivSqrt(cfg: FuConfig)(implicit p: Parameters) extends VecNonPipedFuncUnit(cfg) { 19 XSError(io.in.valid && io.in.bits.ctrl.fuOpType === VfpuType.dummy, "Vfdiv OpType not supported") 20 21 // params alias 22 private val dataWidth = cfg.dataBits 23 private val dataWidthOfDataModule = 64 24 private val numVecModule = dataWidth / dataWidthOfDataModule 25 26 // io alias 27 private val opcode = fuOpType(0) 28 29 // modules 30 private val vfdivs = Seq.fill(numVecModule)(Module(new VectorFloatDivider)) 31 private val vs2Split = Module(new VecDataSplitModule(dataWidth, dataWidthOfDataModule)) 32 private val vs1Split = Module(new VecDataSplitModule(dataWidth, dataWidthOfDataModule)) 33 private val oldVdSplit = Module(new VecDataSplitModule(dataWidth, dataWidthOfDataModule)) 34 private val mgu = Module(new Mgu(dataWidth)) 35 36 /** 37 * In connection of [[vs2Split]], [[vs1Split]] and [[oldVdSplit]] 38 */ 39 vs2Split.io.inVecData := vs2 40 vs1Split.io.inVecData := vs1 41 oldVdSplit.io.inVecData := oldVd 42 43 /** 44 * [[vfdivs]]'s in connection 45 */ 46 private val vs2GroupedVec: Vec[UInt] = VecInit(vs2Split.io.outVec32b.zipWithIndex.groupBy(_._2 % 2).map(x => x._1 -> x._2.map(_._1)).values.map(x => Cat(x.reverse)).toSeq) 47 private val vs1GroupedVec: Vec[UInt] = VecInit(vs1Split.io.outVec32b.zipWithIndex.groupBy(_._2 % 2).map(x => x._1 -> x._2.map(_._1)).values.map(x => Cat(x.reverse)).toSeq) 48 private val resultData = Wire(Vec(numVecModule, UInt(dataWidthOfDataModule.W))) 49 private val fflagsData = Wire(Vec(numVecModule, UInt(20.W))) 50 51 vfdivs.zipWithIndex.foreach { 52 case (mod, i) => 53 mod.io.start_valid_i := io.in.valid 54 mod.io.finish_ready_i := io.out.ready 55 mod.io.flush_i := 0.U 56 mod.io.fp_format_i := vsew 57 mod.io.opa_i := vs2Split.io.outVec64b(i) 58 mod.io.opb_i := vs1Split.io.outVec64b(i) 59 mod.io.frs2_i := 0.U // already vf -> vv 60 mod.io.frs1_i := 0.U // already vf -> vv 61 mod.io.is_frs2_i := false.B // already vf -> vv 62 mod.io.is_frs1_i := false.B // already vf -> vv 63 mod.io.is_sqrt_i := opcode 64 mod.io.rm_i := frm 65 mod.io.is_vec_i := true.B // Todo 66 resultData(i) := mod.io.fpdiv_res_o 67 fflagsData(i) := mod.io.fflags_o 68 69 io.in.ready := mod.io.start_ready_o 70 io.out.valid := mod.io.finish_valid_o 71 } 72 73 val resultDataUInt = resultData.asUInt 74 mgu.io.in.vd := resultDataUInt 75 mgu.io.in.oldVd := outOldVd 76 mgu.io.in.mask := outSrcMask 77 mgu.io.in.info.ta := outVecCtrl.vta 78 mgu.io.in.info.ma := outVecCtrl.vma 79 mgu.io.in.info.vl := outVl 80 mgu.io.in.info.vstart := outVecCtrl.vstart 81 mgu.io.in.info.eew := outVecCtrl.vsew 82 mgu.io.in.info.vdIdx := outVecCtrl.vuopIdx 83 mgu.io.in.info.narrow := outVecCtrl.isNarrow 84 mgu.io.in.info.dstMask := outVecCtrl.isDstMask 85 io.out.bits.res.data := mgu.io.out.vd 86 87 val allFFlagsEn = Wire(Vec(4 * numVecModule, Bool())) 88 val outSrcMaskRShift = Wire(UInt((4 * numVecModule).W)) 89 outSrcMaskRShift := (outSrcMask >> (outVecCtrl.vuopIdx * (16.U >> outVecCtrl.vsew)))(4 * numVecModule - 1, 0) 90 val f16FFlagsEn = outSrcMaskRShift 91 val f32FFlagsEn = Wire(Vec(numVecModule, UInt(4.W))) 92 for (i <- 0 until numVecModule) { 93 f32FFlagsEn(i) := Cat(Fill(2, 1.U), outSrcMaskRShift(2 * i + 1, 2 * i)) 94 } 95 val f64FFlagsEn = Wire(Vec(numVecModule, UInt(4.W))) 96 for (i <- 0 until numVecModule) { 97 f64FFlagsEn(i) := Cat(Fill(3, 1.U), outSrcMaskRShift(i)) 98 } 99 val fflagsEn = Mux1H( 100 Seq( 101 (outVecCtrl.vsew === 1.U) -> f16FFlagsEn.asUInt, 102 (outVecCtrl.vsew === 2.U) -> f32FFlagsEn.asUInt, 103 (outVecCtrl.vsew === 3.U) -> f64FFlagsEn.asUInt 104 ) 105 ) 106 allFFlagsEn := fflagsEn.asTypeOf(allFFlagsEn) 107 108 val allFFlags = fflagsData.asTypeOf(Vec(4 * numVecModule, UInt(5.W))) 109 val outFFlags = allFFlagsEn.zip(allFFlags).map { 110 case (en, fflags) => Mux(en, fflags, 0.U(5.W)) 111 }.reduce(_ | _) 112 io.out.bits.res.fflags.get := outFFlags 113} 114