1package xiangshan.backend.fu.wrapper 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import utils.XSError 7import xiangshan.backend.fu.FuConfig 8import xiangshan.backend.fu.vector.Bundles.{VLmul, VSew, ma} 9import xiangshan.backend.fu.vector.utils.VecDataSplitModule 10import xiangshan.backend.fu.vector.{Mgu, Mgtu, VecInfo, VecPipedFuncUnit} 11import xiangshan.ExceptionNO 12import yunsuan.{VfaluType, VfpuType} 13import yunsuan.vector.VectorFloatAdder 14 15class VFAlu(cfg: FuConfig)(implicit p: Parameters) extends VecPipedFuncUnit(cfg) { 16 XSError(io.in.valid && io.in.bits.ctrl.fuOpType === VfpuType.dummy, "Vfalu OpType not supported") 17 18 // params alias 19 private val dataWidth = cfg.dataBits 20 private val dataWidthOfDataModule = 64 21 private val numVecModule = dataWidth / dataWidthOfDataModule 22 23 // io alias 24 private val opcode = fuOpType(4,0) 25 private val resWiden = fuOpType(5) 26 private val opbWiden = fuOpType(6) 27 28 // modules 29 private val vfalus = Seq.fill(numVecModule)(Module(new VectorFloatAdder)) 30 private val vs2Split = Module(new VecDataSplitModule(dataWidth, dataWidthOfDataModule)) 31 private val vs1Split = Module(new VecDataSplitModule(dataWidth, dataWidthOfDataModule)) 32 private val oldVdSplit = Module(new VecDataSplitModule(dataWidth, dataWidthOfDataModule)) 33 private val mgu = Module(new Mgu(dataWidth)) 34 private val mgtu = Module(new Mgtu(dataWidth)) 35 36 /** 37 * In connection of [[vs2Split]], [[vs1Split]] and [[oldVdSplit]] 38 */ 39 vs2Split.io.inVecData := vs2 40 vs1Split.io.inVecData := vs1 41 oldVdSplit.io.inVecData := oldVd 42 43 /** 44 * [[vfalus]]'s in connection 45 */ 46 // Vec(vs2(31,0), vs2(63,32), vs2(95,64), vs2(127,96)) ==> 47 // Vec( 48 // Cat(vs2(95,64), vs2(31,0)), 49 // Cat(vs2(127,96), vs2(63,32)), 50 // ) 51 private val vs2GroupedVec: Vec[UInt] = VecInit(vs2Split.io.outVec32b.zipWithIndex.groupBy(_._2 % 2).map(x => x._1 -> x._2.map(_._1)).values.map(x => Cat(x.reverse)).toSeq) 52 private val vs1GroupedVec: Vec[UInt] = VecInit(vs1Split.io.outVec32b.zipWithIndex.groupBy(_._2 % 2).map(x => x._1 -> x._2.map(_._1)).values.map(x => Cat(x.reverse)).toSeq) 53 private val resultData = Wire(Vec(numVecModule,UInt(dataWidthOfDataModule.W))) 54 private val fflagsData = Wire(Vec(numVecModule,UInt(20.W))) 55 private val srcMaskRShiftForReduction = Wire(UInt((8 * numVecModule).W)) 56 // for reduction 57 val isFirstGroupUop = vuopIdx === 0.U || 58 (vuopIdx === 1.U && (vlmul === VLmul.m4 || vlmul === VLmul.m8)) || 59 ((vuopIdx === 2.U || vuopIdx === 3.U) && vlmul === VLmul.m8) 60 val maskRshiftWidthForReduction = Wire(UInt(6.W)) 61 maskRshiftWidthForReduction := Mux(fuOpType === VfaluType.vfredosum, 62 vuopIdx, 63 Mux1H(Seq( 64 (vsew === VSew.e16) -> (vuopIdx(1, 0) << 4), 65 (vsew === VSew.e32) -> (vuopIdx(1, 0) << 3), 66 (vsew === VSew.e64) -> (vuopIdx(1, 0) << 2), 67 )) 68 ) 69 val vlMaskForReduction = (~(Fill(VLEN, 1.U) << vl)).asUInt 70 srcMaskRShiftForReduction := ((srcMask & vlMaskForReduction) >> maskRshiftWidthForReduction)(8 * numVecModule - 1, 0) 71 72 def genMaskForReduction(inmask: UInt, sew: UInt, i: Int): UInt = { 73 val f64MaskNum = dataWidth / 64 * 2 74 val f32MaskNum = dataWidth / 32 * 2 75 val f16MaskNum = dataWidth / 16 * 2 76 val f64Mask = inmask(f64MaskNum - 1, 0) 77 val f32Mask = inmask(f32MaskNum - 1, 0) 78 val f16Mask = inmask(f16MaskNum - 1, 0) 79 // vs2 reordered, so mask use high bits 80 val f64FirstFoldMask = Mux1H( 81 Seq( 82 vecCtrl.fpu.isFoldTo1_2 -> Cat(0.U(3.W), f64Mask(0), 0.U(3.W), f64Mask(1)), 83 ) 84 ) 85 val f32FirstFoldMask = Mux1H( 86 Seq( 87 vecCtrl.fpu.isFoldTo1_2 -> Cat(0.U(2.W), f32Mask(1), f32Mask(0), 0.U(2.W), f32Mask(3), f32Mask(2)), 88 vecCtrl.fpu.isFoldTo1_4 -> Cat(0.U(3.W), f32Mask(0), 0.U(3.W), f32Mask(1)), 89 ) 90 ) 91 val f16FirstFoldMask = Mux1H( 92 Seq( 93 vecCtrl.fpu.isFoldTo1_2 -> Cat(f16Mask(7,4), f16Mask(3,0)), 94 vecCtrl.fpu.isFoldTo1_4 -> Cat(0.U(2.W), f16Mask(1), f16Mask(0), 0.U(2.W), f16Mask(3), f16Mask(2)), 95 vecCtrl.fpu.isFoldTo1_8 -> Cat(0.U(3.W), f16Mask(0), 0.U(3.W), f16Mask(1)), 96 ) 97 ) 98 val f64FoldMask = Mux1H( 99 Seq( 100 vecCtrl.fpu.isFoldTo1_2 -> "b00010001".U, 101 ) 102 ) 103 val f32FoldMask = Mux1H( 104 Seq( 105 vecCtrl.fpu.isFoldTo1_2 -> "b00110011".U, 106 vecCtrl.fpu.isFoldTo1_4 -> "b00010001".U, 107 ) 108 ) 109 val f16FoldMask = Mux1H( 110 Seq( 111 vecCtrl.fpu.isFoldTo1_2 -> "b11111111".U, 112 vecCtrl.fpu.isFoldTo1_4 -> "b00110011".U, 113 vecCtrl.fpu.isFoldTo1_8 -> "b00010001".U, 114 ) 115 ) 116 // low 4 bits for vs2(fp_a), high 4 bits for vs1(fp_b), 117 val isFold = vecCtrl.fpu.isFoldTo1_2 || vecCtrl.fpu.isFoldTo1_4 || vecCtrl.fpu.isFoldTo1_8 118 val f64FirstNotFoldMask = Cat(0.U(3.W), f64Mask(i + 2), 0.U(3.W), f64Mask(i)) 119 val f32FirstNotFoldMask = Cat(0.U(2.W), f32Mask(i * 2 + 5, i * 2 + 4), 0.U(2.W), Cat(f32Mask(i * 2 + 1, i * 2))) 120 val f16FirstNotFoldMask = Cat(f16Mask(i * 4 + 11, i * 4 + 8), f16Mask(i * 4 + 3, i * 4)) 121 val f64MaskI = Mux(isFirstGroupUop, Mux(isFold, f64FirstFoldMask, f64FirstNotFoldMask), Mux(isFold, f64FoldMask, Fill(8,1.U))) 122 val f32MaskI = Mux(isFirstGroupUop, Mux(isFold, f32FirstFoldMask, f32FirstNotFoldMask), Mux(isFold, f32FoldMask, Fill(8,1.U))) 123 val f16MaskI = Mux(isFirstGroupUop, Mux(isFold, f16FirstFoldMask, f16FirstNotFoldMask), Mux(isFold, f16FoldMask, Fill(8,1.U))) 124 val outMask = Mux1H( 125 Seq( 126 (sew === 3.U) -> f64MaskI, 127 (sew === 2.U) -> f32MaskI, 128 (sew === 1.U) -> f16MaskI, 129 ) 130 ) 131 Mux(fuOpType === VfaluType.vfredosum || fuOpType === VfaluType.vfwredosum, outMask(0),outMask) 132 } 133 def genMaskForMerge(inmask:UInt, sew:UInt, i:Int): UInt = { 134 val f64MaskNum = dataWidth / 64 135 val f32MaskNum = dataWidth / 32 136 val f16MaskNum = dataWidth / 16 137 val f64Mask = inmask(f64MaskNum-1,0) 138 val f32Mask = inmask(f32MaskNum-1,0) 139 val f16Mask = inmask(f16MaskNum-1,0) 140 val f64MaskI = Cat(0.U(3.W),f64Mask(i)) 141 val f32MaskI = Cat(0.U(2.W),f32Mask(2*i+1,2*i)) 142 val f16MaskI = f16Mask(4*i+3,4*i) 143 val outMask = Mux1H( 144 Seq( 145 (sew === 3.U) -> f64MaskI, 146 (sew === 2.U) -> f32MaskI, 147 (sew === 1.U) -> f16MaskI, 148 ) 149 ) 150 outMask 151 } 152 val isScalarMove = (fuOpType === VfaluType.vfmv_f_s) || (fuOpType === VfaluType.vfmv_s_f) 153 val srcMaskRShift = Wire(UInt((4 * numVecModule).W)) 154 val maskRshiftWidth = Wire(UInt(6.W)) 155 maskRshiftWidth := Mux1H( 156 Seq( 157 (vsew === VSew.e16) -> (vuopIdx(2,0) << 3), 158 (vsew === VSew.e32) -> (vuopIdx(2,0) << 2), 159 (vsew === VSew.e64) -> (vuopIdx(2,0) << 1), 160 ) 161 ) 162 srcMaskRShift := (srcMask >> maskRshiftWidth)(4 * numVecModule - 1, 0) 163 val fp_aIsFpCanonicalNAN = Wire(Vec(numVecModule,Bool())) 164 val fp_bIsFpCanonicalNAN = Wire(Vec(numVecModule,Bool())) 165 vfalus.zipWithIndex.foreach { 166 case (mod, i) => 167 mod.io.fp_a := Mux(opbWiden, vs1Split.io.outVec64b(i), vs2Split.io.outVec64b(i)) // very dirty TODO 168 mod.io.fp_b := Mux(opbWiden, vs2Split.io.outVec64b(i), vs1Split.io.outVec64b(i)) // very dirty TODO 169 mod.io.widen_a := Cat(vs2Split.io.outVec32b(i+numVecModule), vs2Split.io.outVec32b(i)) 170 mod.io.widen_b := Cat(vs1Split.io.outVec32b(i+numVecModule), vs1Split.io.outVec32b(i)) 171 mod.io.frs1 := 0.U // already vf -> vv 172 mod.io.is_frs1 := false.B // already vf -> vv 173 mod.io.mask := Mux(isScalarMove, !vuopIdx.orR, genMaskForMerge(inmask = srcMaskRShift, sew = vsew, i = i)) 174 mod.io.maskForReduction := genMaskForReduction(inmask = srcMaskRShiftForReduction, sew = vsew, i = i) 175 mod.io.uop_idx := Mux(fuOpType === VfaluType.vfwredosum, 0.U, vuopIdx(0)) 176 mod.io.is_vec := true.B // Todo 177 mod.io.round_mode := frm 178 mod.io.fp_format := Mux(resWiden, vsew + 1.U, vsew) 179 mod.io.opb_widening := opbWiden || (fuOpType === VfaluType.vfwredosum) 180 mod.io.res_widening := resWiden 181 mod.io.op_code := opcode 182 resultData(i) := mod.io.fp_result 183 fflagsData(i) := mod.io.fflags 184 fp_aIsFpCanonicalNAN(i) := vecCtrl.fpu.isFpToVecInst & ( 185 ((vsew === VSew.e32) & (!vs2Split.io.outVec64b(i).head(32).andR)) | 186 ((vsew === VSew.e16) & (!vs2Split.io.outVec64b(i).head(48).andR)) 187 ) 188 fp_bIsFpCanonicalNAN(i) := vecCtrl.fpu.isFpToVecInst & ( 189 ((vsew === VSew.e32) & (!vs1Split.io.outVec64b(i).head(32).andR)) | 190 ((vsew === VSew.e16) & (!vs1Split.io.outVec64b(i).head(48).andR)) 191 ) 192 mod.io.fp_aIsFpCanonicalNAN := fp_aIsFpCanonicalNAN(i) 193 mod.io.fp_bIsFpCanonicalNAN := fp_bIsFpCanonicalNAN(i) 194 } 195 val resultDataUInt = resultData.asUInt 196 val cmpResultWidth = dataWidth / 16 197 val cmpResult = Wire(Vec(cmpResultWidth, Bool())) 198 for (i <- 0 until cmpResultWidth) { 199 if(i == 0) { 200 cmpResult(i) := resultDataUInt(0) 201 } 202 else if(i < dataWidth / 64) { 203 cmpResult(i) := Mux1H( 204 Seq( 205 (outVecCtrl.vsew === 1.U) -> resultDataUInt(i*16), 206 (outVecCtrl.vsew === 2.U) -> resultDataUInt(i*32), 207 (outVecCtrl.vsew === 3.U) -> resultDataUInt(i*64) 208 ) 209 ) 210 } 211 else if(i < dataWidth / 32) { 212 cmpResult(i) := Mux1H( 213 Seq( 214 (outVecCtrl.vsew === 1.U) -> resultDataUInt(i * 16), 215 (outVecCtrl.vsew === 2.U) -> resultDataUInt(i * 32), 216 (outVecCtrl.vsew === 3.U) -> false.B 217 ) 218 ) 219 } 220 else if(i < dataWidth / 16) { 221 cmpResult(i) := Mux(outVecCtrl.vsew === 1.U, resultDataUInt(i*16), false.B) 222 } 223 } 224 225 val outEew = Mux(RegNext(resWiden), outVecCtrl.vsew + 1.U, outVecCtrl.vsew) 226 val outVuopidx = outVecCtrl.vuopIdx(2, 0) 227 val vlMax = ((VLEN/8).U >> outEew).asUInt 228 val lmulAbs = Mux(outVecCtrl.vlmul(2), (~outVecCtrl.vlmul(1,0)).asUInt + 1.U, outVecCtrl.vlmul(1,0)) 229 // vfmv_f_s need vl=1, reduction last uop need vl=1, other uop need vl=vlmax 230 val numOfUopVFRED = { 231 // addTime include add frs1 232 val addTime = MuxLookup(outVecCtrl.vlmul, 1.U(4.W), Array( 233 VLmul.m2 -> 2.U, 234 VLmul.m4 -> 4.U, 235 VLmul.m8 -> 8.U, 236 )) 237 val foldLastVlmul = MuxLookup(outVecCtrl.vsew, "b000".U, Array( 238 VSew.e16 -> VLmul.mf8, 239 VSew.e32 -> VLmul.mf4, 240 VSew.e64 -> VLmul.mf2, 241 )) 242 // lmul < 1, foldTime = vlmul - foldFastVlmul 243 // lmul >= 1, foldTime = 0.U - foldFastVlmul 244 val foldTime = Mux(outVecCtrl.vlmul(2), outVecCtrl.vlmul, 0.U) - foldLastVlmul 245 addTime + foldTime 246 } 247 val reductionVl = Mux((outVecCtrl.vuopIdx === numOfUopVFRED - 1.U) || (outCtrl.fuOpType === VfaluType.vfredosum || outCtrl.fuOpType === VfaluType.vfwredosum), 1.U, vlMax) 248 val outIsResuction = outCtrl.fuOpType === VfaluType.vfredusum || 249 outCtrl.fuOpType === VfaluType.vfredmax || 250 outCtrl.fuOpType === VfaluType.vfredmin || 251 outCtrl.fuOpType === VfaluType.vfredosum || 252 outCtrl.fuOpType === VfaluType.vfwredosum 253 val outVlFix = Mux( 254 outVecCtrl.fpu.isFpToVecInst || (outCtrl.fuOpType === VfaluType.vfmv_f_s), 255 1.U, 256 Mux( 257 outCtrl.fuOpType === VfaluType.vfmv_s_f, 258 outVl.orR, 259 Mux(outIsResuction, reductionVl, outVl) 260 ) 261 ) 262 val vlMaxAllUop = Wire(outVl.cloneType) 263 vlMaxAllUop := Mux(outVecCtrl.vlmul(2), vlMax >> lmulAbs, vlMax << lmulAbs).asUInt 264 val vlMaxThisUop = Mux(outVecCtrl.vlmul(2), vlMax >> lmulAbs, vlMax).asUInt 265 val vlSetThisUop = Mux(outVlFix > outVuopidx*vlMaxThisUop, outVlFix - outVuopidx*vlMaxThisUop, 0.U) 266 val vlThisUop = Wire(UInt(3.W)) 267 vlThisUop := Mux(vlSetThisUop < vlMaxThisUop, vlSetThisUop, vlMaxThisUop) 268 val vlMaskRShift = Wire(UInt((4 * numVecModule).W)) 269 vlMaskRShift := Fill(4 * numVecModule, 1.U(1.W)) >> ((4 * numVecModule).U - vlThisUop) 270 271 private val needNoMask = outCtrl.fuOpType === VfaluType.vfmerge || 272 outCtrl.fuOpType === VfaluType.vfmv_s_f || 273 outIsResuction || 274 outVecCtrl.fpu.isFpToVecInst 275 val maskToMgu = Mux(needNoMask, allMaskTrue, outSrcMask) 276 val allFFlagsEn = Wire(Vec(4*numVecModule,Bool())) 277 val outSrcMaskRShift = Wire(UInt((4*numVecModule).W)) 278 outSrcMaskRShift := (maskToMgu >> (outVecCtrl.vuopIdx(2,0) * vlMax))(4*numVecModule-1,0) 279 val f16FFlagsEn = outSrcMaskRShift 280 val f32FFlagsEn = Wire(Vec(numVecModule,UInt(4.W))) 281 for (i <- 0 until numVecModule){ 282 f32FFlagsEn(i) := Cat(Fill(2, 0.U),outSrcMaskRShift(2*i+1,2*i)) 283 } 284 val f64FFlagsEn = Wire(Vec(numVecModule, UInt(4.W))) 285 for (i <- 0 until numVecModule) { 286 f64FFlagsEn(i) := Cat(Fill(3, 0.U), outSrcMaskRShift(i)) 287 } 288 val fflagsEn= Mux1H( 289 Seq( 290 (outEew === 1.U) -> f16FFlagsEn.asUInt, 291 (outEew === 2.U) -> f32FFlagsEn.asUInt, 292 (outEew === 3.U) -> f64FFlagsEn.asUInt 293 ) 294 ) 295 allFFlagsEn := Mux(outIsResuction, Fill(4*numVecModule, 1.U), (fflagsEn & vlMaskRShift)).asTypeOf(allFFlagsEn) 296 297 val allFFlags = fflagsData.asTypeOf(Vec(4*numVecModule,UInt(5.W))) 298 val outFFlags = allFFlagsEn.zip(allFFlags).map{ 299 case(en,fflags) => Mux(en, fflags, 0.U(5.W)) 300 }.reduce(_ | _) 301 io.out.bits.res.fflags.get := outFFlags 302 303 304 val cmpResultOldVd = Wire(UInt(cmpResultWidth.W)) 305 val cmpResultOldVdRshiftWidth = Wire(UInt(6.W)) 306 cmpResultOldVdRshiftWidth := Mux1H( 307 Seq( 308 (outVecCtrl.vsew === VSew.e16) -> (outVecCtrl.vuopIdx(2, 0) << 3), 309 (outVecCtrl.vsew === VSew.e32) -> (outVecCtrl.vuopIdx(2, 0) << 2), 310 (outVecCtrl.vsew === VSew.e64) -> (outVecCtrl.vuopIdx(2, 0) << 1), 311 ) 312 ) 313 cmpResultOldVd := (outOldVd >> cmpResultOldVdRshiftWidth)(4*numVecModule-1,0) 314 val cmpResultForMgu = Wire(Vec(cmpResultWidth, Bool())) 315 private val maxVdIdx = 8 316 private val elementsInOneUop = Mux1H( 317 Seq( 318 (outEew === 1.U) -> (cmpResultWidth).U(4.W), 319 (outEew === 2.U) -> (cmpResultWidth / 2).U(4.W), 320 (outEew === 3.U) -> (cmpResultWidth / 4).U(4.W), 321 ) 322 ) 323 private val vdIdx = outVecCtrl.vuopIdx(2, 0) 324 private val elementsComputed = Mux1H(Seq.tabulate(maxVdIdx)(i => (vdIdx === i.U) -> (elementsInOneUop * i.U))) 325 for (i <- 0 until cmpResultWidth) { 326 val cmpResultWithVmask = Mux(outSrcMaskRShift(i), cmpResult(i), Mux(outVecCtrl.vma, true.B, cmpResultOldVd(i))) 327 cmpResultForMgu(i) := Mux(elementsComputed +& i.U >= outVl, true.B, cmpResultWithVmask) 328 } 329 val outIsFold = outVecCtrl.fpu.isFoldTo1_2 || outVecCtrl.fpu.isFoldTo1_4 || outVecCtrl.fpu.isFoldTo1_8 330 val outOldVdForREDO = Mux1H(Seq( 331 (outVecCtrl.vsew === VSew.e16) -> (outOldVd >> 16), 332 (outVecCtrl.vsew === VSew.e32) -> (outOldVd >> 32), 333 (outVecCtrl.vsew === VSew.e64) -> (outOldVd >> 64), 334 )) 335 val outOldVdForWREDO = Mux( 336 !outIsFold, 337 Mux(outVecCtrl.vsew === VSew.e16, Cat(outOldVd(VLEN-1-16,16), 0.U(32.W)), Cat(outOldVd(VLEN-1-32,32), 0.U(64.W))), 338 Mux(outVecCtrl.vsew === VSew.e16, 339 // Divide vuopIdx by 8 and the remainder is 1 340 Mux(outVecCtrl.vuopIdx(2,0) === 1.U, outOldVd, outOldVd >> 16), 341 // Divide vuopIdx by 4 and the remainder is 1 342 Mux(outVecCtrl.vuopIdx(1,0) === 1.U, outOldVd, outOldVd >> 32) 343 ), 344 ) 345 val outOldVdForRED = Mux(outCtrl.fuOpType === VfaluType.vfredosum, outOldVdForREDO, outOldVdForWREDO) 346 val numOfUopVFREDOSUM = { 347 val uvlMax = MuxLookup(outVecCtrl.vsew, 0.U, Array( 348 VSew.e16 -> 8.U, 349 VSew.e32 -> 4.U, 350 VSew.e64 -> 2.U, 351 )) 352 val vlMax = Mux(outVecCtrl.vlmul(2), uvlMax >> (-outVecCtrl.vlmul)(1, 0), uvlMax << outVecCtrl.vlmul(1, 0)).asUInt 353 vlMax 354 } 355 val isOutOldVdForREDO = (outCtrl.fuOpType === VfaluType.vfredosum && outIsFold) || outCtrl.fuOpType === VfaluType.vfwredosum 356 val taIsFalseForVFREDO = ((outCtrl.fuOpType === VfaluType.vfredosum) || (outCtrl.fuOpType === VfaluType.vfwredosum)) && (outVecCtrl.vuopIdx =/= numOfUopVFREDOSUM - 1.U) 357 // outVecCtrl.fpu.isFpToVecInst means the instruction is float instruction, not vector float instruction 358 val notUseVl = outVecCtrl.fpu.isFpToVecInst || (outCtrl.fuOpType === VfaluType.vfmv_f_s) 359 val notModifyVd = !notUseVl && (outVl === 0.U) 360 mgu.io.in.vd := Mux(outVecCtrl.isDstMask, Cat(0.U((dataWidth / 16 * 15).W), cmpResultForMgu.asUInt), resultDataUInt) 361 mgu.io.in.oldVd := Mux(isOutOldVdForREDO, outOldVdForRED, outOldVd) 362 mgu.io.in.mask := maskToMgu 363 mgu.io.in.info.ta := Mux(outCtrl.fuOpType === VfaluType.vfmv_f_s, true.B , Mux(taIsFalseForVFREDO, false.B, outVecCtrl.vta)) 364 mgu.io.in.info.ma := Mux(outCtrl.fuOpType === VfaluType.vfmv_s_f, true.B , outVecCtrl.vma) 365 mgu.io.in.info.vl := outVlFix 366 mgu.io.in.info.vstart := outVecCtrl.vstart 367 mgu.io.in.info.vlmul := outVecCtrl.vlmul 368 mgu.io.in.info.valid := Mux(notModifyVd, false.B, io.in.valid) 369 mgu.io.in.info.vstart := Mux(outVecCtrl.fpu.isFpToVecInst, 0.U, outVecCtrl.vstart) 370 mgu.io.in.info.eew := outEew 371 mgu.io.in.info.vsew := outVecCtrl.vsew 372 mgu.io.in.info.vdIdx := Mux(outIsResuction, 0.U, outVecCtrl.vuopIdx) 373 mgu.io.in.info.narrow := outVecCtrl.isNarrow 374 mgu.io.in.info.dstMask := outVecCtrl.isDstMask 375 mgu.io.in.isIndexedVls := false.B 376 mgtu.io.in.vd := Mux(outVecCtrl.isDstMask, mgu.io.out.vd, resultDataUInt) 377 mgtu.io.in.vl := outVl 378 val resultFpMask = Wire(UInt(VLEN.W)) 379 val isFclass = outVecCtrl.fpu.isFpToVecInst && (outCtrl.fuOpType === VfaluType.vfclass) 380 val fpCmpFuOpType = Seq(VfaluType.vfeq, VfaluType.vflt, VfaluType.vfle) 381 val isCmp = outVecCtrl.fpu.isFpToVecInst && (fpCmpFuOpType.map(_ === outCtrl.fuOpType).reduce(_|_)) 382 resultFpMask := Mux(isFclass || isCmp, Fill(16, 1.U(1.W)), Fill(VLEN, 1.U(1.W))) 383 // when dest is mask, the result need to be masked by mgtu 384 io.out.bits.res.data := Mux(notModifyVd, outOldVd, Mux(outVecCtrl.isDstMask, mgtu.io.out.vd, mgu.io.out.vd) & resultFpMask) 385 io.out.bits.ctrl.exceptionVec.get(ExceptionNO.illegalInstr) := mgu.io.out.illegal 386 387} 388 389class VFMgu(vlen:Int)(implicit p: Parameters) extends Module{ 390 val io = IO(new VFMguIO(vlen)) 391 392 val vd = io.in.vd 393 val oldvd = io.in.oldVd 394 val mask = io.in.mask 395 val vsew = io.in.info.eew 396 val num16bits = vlen / 16 397 398} 399 400class VFMguIO(vlen: Int)(implicit p: Parameters) extends Bundle { 401 val in = new Bundle { 402 val vd = Input(UInt(vlen.W)) 403 val oldVd = Input(UInt(vlen.W)) 404 val mask = Input(UInt(vlen.W)) 405 val info = Input(new VecInfo) 406 } 407 val out = new Bundle { 408 val vd = Output(UInt(vlen.W)) 409 } 410}