1package xiangshan.backend.fu.wrapper 2 3import chipsalliance.rocketchip.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import utils.XSError 7import xiangshan.backend.fu.FuConfig 8import xiangshan.backend.fu.vector.Bundles.{VSew, ma} 9import xiangshan.backend.fu.vector.utils.VecDataSplitModule 10import xiangshan.backend.fu.vector.{Mgu, VecInfo, VecPipedFuncUnit} 11import yunsuan.{VfaluType, VfpuType} 12import yunsuan.vector.VectorFloatAdder 13 14class VFAlu(cfg: FuConfig)(implicit p: Parameters) extends VecPipedFuncUnit(cfg) { 15 XSError(io.in.valid && io.in.bits.ctrl.fuOpType === VfpuType.dummy, "Vfalu OpType not supported") 16 17 // params alias 18 private val dataWidth = cfg.dataBits 19 private val dataWidthOfDataModule = 64 20 private val numVecModule = dataWidth / dataWidthOfDataModule 21 22 // io alias 23 private val opcode = fuOpType(4,0) 24 private val resWiden = fuOpType(5) 25 private val opbWiden = fuOpType(6) 26 27 // modules 28 private val vfalus = Seq.fill(numVecModule)(Module(new VectorFloatAdder)) 29 private val vs2Split = Module(new VecDataSplitModule(dataWidth, dataWidthOfDataModule)) 30 private val vs1Split = Module(new VecDataSplitModule(dataWidth, dataWidthOfDataModule)) 31 private val oldVdSplit = Module(new VecDataSplitModule(dataWidth, dataWidthOfDataModule)) 32 private val mgu = Module(new Mgu(dataWidth)) 33 34 /** 35 * In connection of [[vs2Split]], [[vs1Split]] and [[oldVdSplit]] 36 */ 37 vs2Split.io.inVecData := vs2 38 vs1Split.io.inVecData := vs1 39 oldVdSplit.io.inVecData := oldVd 40 41 /** 42 * [[vfalus]]'s in connection 43 */ 44 // Vec(vs2(31,0), vs2(63,32), vs2(95,64), vs2(127,96)) ==> 45 // Vec( 46 // Cat(vs2(95,64), vs2(31,0)), 47 // Cat(vs2(127,96), vs2(63,32)), 48 // ) 49 private val vs2GroupedVec: Vec[UInt] = VecInit(vs2Split.io.outVec32b.zipWithIndex.groupBy(_._2 % 2).map(x => x._1 -> x._2.map(_._1)).values.map(x => Cat(x.reverse)).toSeq) 50 private val vs1GroupedVec: Vec[UInt] = VecInit(vs1Split.io.outVec32b.zipWithIndex.groupBy(_._2 % 2).map(x => x._1 -> x._2.map(_._1)).values.map(x => Cat(x.reverse)).toSeq) 51 private val resultData = Wire(Vec(numVecModule,UInt(dataWidthOfDataModule.W))) 52 private val fflagsData = Wire(Vec(numVecModule,UInt(20.W))) 53 private val srcMaskRShift = Wire(UInt((4 * numVecModule).W)) 54 55 def genMaskForMerge(inmask:UInt, sew:UInt, i:Int): UInt = { 56 val f64MaskNum = dataWidth / 64 57 val f32MaskNum = dataWidth / 32 58 val f16MaskNum = dataWidth / 16 59 val f64Mask = inmask(f64MaskNum-1,0) 60 val f32Mask = inmask(f32MaskNum-1,0) 61 val f16Mask = inmask(f16MaskNum-1,0) 62 val f64MaskI = Cat(0.U(3.W),f64Mask(i)) 63 val f32MaskI = Cat(0.U(2.W),f32Mask(2*i+1,2*i)) 64 val f16MaskI = f16Mask(4*i+3,4*i) 65 val outMask = Mux1H( 66 Seq( 67 (sew === 3.U) -> f64MaskI, 68 (sew === 2.U) -> f32MaskI, 69 (sew === 1.U) -> f16MaskI, 70 ) 71 ) 72 outMask 73 } 74 val isScalarMove = (fuOpType === VfaluType.vfmv_f_s) || (fuOpType === VfaluType.vfmv_s_f) 75 srcMaskRShift := (srcMask >> (vecCtrl.vuopIdx * (16.U >> vecCtrl.vsew)))(4 * numVecModule - 1, 0) 76 val fp_aIsFpCanonicalNAN = Wire(Vec(numVecModule,Bool())) 77 val fp_bIsFpCanonicalNAN = Wire(Vec(numVecModule,Bool())) 78 vfalus.zipWithIndex.foreach { 79 case (mod, i) => 80 mod.io.fp_a := Mux(opbWiden, vs1Split.io.outVec64b(i), vs2Split.io.outVec64b(i)) // very dirty TODO 81 mod.io.fp_b := Mux(opbWiden, vs2Split.io.outVec64b(i), vs1Split.io.outVec64b(i)) // very dirty TODO 82 mod.io.widen_a := Cat(vs2Split.io.outVec32b(i+numVecModule), vs2Split.io.outVec32b(i)) 83 mod.io.widen_b := Cat(vs1Split.io.outVec32b(i+numVecModule), vs1Split.io.outVec32b(i)) 84 mod.io.frs1 := 0.U // already vf -> vv 85 mod.io.is_frs1 := false.B // already vf -> vv 86 mod.io.mask := Mux(isScalarMove, !vuopIdx.orR, genMaskForMerge(inmask = srcMaskRShift, sew = vsew, i = i)) 87 mod.io.uop_idx := vuopIdx(0) 88 mod.io.is_vec := true.B // Todo 89 mod.io.round_mode := frm 90 mod.io.fp_format := Mux(resWiden, vsew + 1.U, vsew) 91 mod.io.opb_widening := opbWiden 92 mod.io.res_widening := resWiden 93 mod.io.op_code := opcode 94 resultData(i) := mod.io.fp_result 95 fflagsData(i) := mod.io.fflags 96 fp_aIsFpCanonicalNAN(i) := vecCtrl.fpu.isFpToVecInst & ( 97 ((vsew === VSew.e32) & (!vs2Split.io.outVec64b(i).head(32).andR)) | 98 ((vsew === VSew.e16) & (!vs2Split.io.outVec64b(i).head(48).andR)) 99 ) 100 fp_bIsFpCanonicalNAN(i) := vecCtrl.fpu.isFpToVecInst & ( 101 ((vsew === VSew.e32) & (!vs1Split.io.outVec64b(i).head(32).andR)) | 102 ((vsew === VSew.e16) & (!vs1Split.io.outVec64b(i).head(48).andR)) 103 ) 104 mod.io.fp_aIsFpCanonicalNAN := fp_aIsFpCanonicalNAN(i) 105 mod.io.fp_bIsFpCanonicalNAN := fp_bIsFpCanonicalNAN(i) 106 } 107 val resultDataUInt = resultData.asUInt 108 val cmpResultWidth = dataWidth / 16 109 val cmpResult = Wire(Vec(cmpResultWidth, Bool())) 110 for (i <- 0 until cmpResultWidth) { 111 if(i == 0) { 112 cmpResult(i) := resultDataUInt(0) 113 } 114 else if(i < dataWidth / 64) { 115 cmpResult(i) := Mux1H( 116 Seq( 117 (outVecCtrl.vsew === 1.U) -> resultDataUInt(i*16), 118 (outVecCtrl.vsew === 2.U) -> resultDataUInt(i*32), 119 (outVecCtrl.vsew === 3.U) -> resultDataUInt(i*64) 120 ) 121 ) 122 } 123 else if(i < dataWidth / 32) { 124 cmpResult(i) := Mux1H( 125 Seq( 126 (outVecCtrl.vsew === 1.U) -> resultDataUInt(i * 16), 127 (outVecCtrl.vsew === 2.U) -> resultDataUInt(i * 32), 128 (outVecCtrl.vsew === 3.U) -> false.B 129 ) 130 ) 131 } 132 else if(i < dataWidth / 16) { 133 cmpResult(i) := Mux(outVecCtrl.vsew === 1.U, resultDataUInt(i*16), false.B) 134 } 135 } 136 137 val outEew = Mux(RegNext(resWiden), outVecCtrl.vsew + 1.U, outVecCtrl.vsew) 138 val outVuopidx = outVecCtrl.vuopIdx(2, 0) 139 val vlMax = ((VLEN/8).U >> outEew).asUInt 140 val lmulAbs = Mux(outVecCtrl.vlmul(2), (~outVecCtrl.vlmul(1,0)).asUInt + 1.U, outVecCtrl.vlmul(1,0)) 141 // vfmv_f_s need vl=1 142 val outVlFix = Mux( 143 outVecCtrl.fpu.isFpToVecInst || (fuOpType === VfaluType.vfmv_f_s), 144 1.U, 145 Mux(fuOpType === VfaluType.vfmv_s_f, outVl.orR, outVl) 146 ) 147 val vlMaxAllUop = Wire(outVl.cloneType) 148 vlMaxAllUop := Mux(outVecCtrl.vlmul(2), vlMax >> lmulAbs, vlMax << lmulAbs).asUInt 149 val vlMaxThisUop = Mux(outVecCtrl.vlmul(2), vlMax >> lmulAbs, vlMax).asUInt 150 val vlSetThisUop = Mux(outVlFix > outVuopidx*vlMaxThisUop, outVlFix - outVuopidx*vlMaxThisUop, 0.U) 151 val vlThisUop = Wire(UInt(3.W)) 152 vlThisUop := Mux(vlSetThisUop < vlMaxThisUop, vlSetThisUop, vlMaxThisUop) 153 val vlMaskRShift = Wire(UInt((4 * numVecModule).W)) 154 vlMaskRShift := Fill(4 * numVecModule, 1.U(1.W)) >> ((4 * numVecModule).U - vlThisUop) 155 156 private val needNoMask = (outCtrl.fuOpType === VfaluType.vfmerge) || (outCtrl.fuOpType === VfaluType.vfmv_s_f) || outVecCtrl.fpu.isFpToVecInst 157 val maskToMgu = Mux(needNoMask, allMaskTrue, outSrcMask) 158 val allFFlagsEn = Wire(Vec(4*numVecModule,Bool())) 159 val outSrcMaskRShift = Wire(UInt((4*numVecModule).W)) 160 outSrcMaskRShift := (maskToMgu >> (outVecCtrl.vuopIdx(2,0) * vlMax))(4*numVecModule-1,0) 161 val f16FFlagsEn = outSrcMaskRShift 162 val f32FFlagsEn = Wire(Vec(numVecModule,UInt(4.W))) 163 for (i <- 0 until numVecModule){ 164 f32FFlagsEn(i) := Cat(Fill(2, 1.U),outSrcMaskRShift(2*i+1,2*i)) 165 } 166 val f64FFlagsEn = Wire(Vec(numVecModule, UInt(4.W))) 167 for (i <- 0 until numVecModule) { 168 f64FFlagsEn(i) := Cat(Fill(3, 1.U), outSrcMaskRShift(i)) 169 } 170 val fflagsEn= Mux1H( 171 Seq( 172 (outEew === 1.U) -> f16FFlagsEn.asUInt, 173 (outEew === 2.U) -> f32FFlagsEn.asUInt, 174 (outEew === 3.U) -> f64FFlagsEn.asUInt 175 ) 176 ) 177 allFFlagsEn := (fflagsEn & vlMaskRShift).asTypeOf(allFFlagsEn) 178 179 val allFFlags = fflagsData.asTypeOf(Vec(4*numVecModule,UInt(5.W))) 180 val outFFlags = allFFlagsEn.zip(allFFlags).map{ 181 case(en,fflags) => Mux(en, fflags, 0.U(5.W)) 182 }.reduce(_ | _) 183 io.out.bits.res.fflags.get := outFFlags 184 185 186 val cmpResultOldVd = Wire(UInt(cmpResultWidth.W)) 187 cmpResultOldVd := (outOldVd >> (outVecCtrl.vuopIdx * (16.U >> outVecCtrl.vsew)))(4*numVecModule-1,0) 188 val cmpResultForMgu = Wire(Vec(cmpResultWidth, Bool())) 189 for (i <- 0 until cmpResultWidth) { 190 cmpResultForMgu(i) := Mux(outSrcMaskRShift(i), cmpResult(i), Mux(outVecCtrl.vma, true.B, cmpResultOldVd(i))) 191 } 192 193 mgu.io.in.vd := Mux(outVecCtrl.isDstMask, Cat(0.U((dataWidth / 16 * 15).W), cmpResultForMgu.asUInt), resultDataUInt) 194 mgu.io.in.oldVd := outOldVd 195 mgu.io.in.mask := maskToMgu 196 mgu.io.in.info.ta := Mux(outCtrl.fuOpType === VfaluType.vfmv_f_s, true.B , outVecCtrl.vta) 197 mgu.io.in.info.ma := Mux(outCtrl.fuOpType === VfaluType.vfmv_s_f, true.B , outVecCtrl.vma) 198 mgu.io.in.info.vl := outVlFix 199 mgu.io.in.info.vstart := outVecCtrl.vstart 200 mgu.io.in.info.eew := outEew 201 mgu.io.in.info.vdIdx := outVecCtrl.vuopIdx 202 mgu.io.in.info.narrow := outVecCtrl.isNarrow 203 mgu.io.in.info.dstMask := outVecCtrl.isDstMask 204 val resultFpMask = Wire(UInt(VLEN.W)) 205 val isFclass = outVecCtrl.fpu.isFpToVecInst && (outCtrl.fuOpType === VfaluType.vfclass) 206 val fpCmpFuOpType = Seq(VfaluType.vfeq, VfaluType.vflt, VfaluType.vfle) 207 val isCmp = outVecCtrl.fpu.isFpToVecInst && (fpCmpFuOpType.map(_ === outCtrl.fuOpType).reduce(_|_)) 208 resultFpMask := Mux(isFclass || isCmp, Fill(16, 1.U(1.W)), Fill(VLEN, 1.U(1.W))) 209 io.out.bits.res.data := mgu.io.out.vd & resultFpMask 210 211} 212 213class VFMgu(vlen:Int)(implicit p: Parameters) extends Module{ 214 val io = IO(new VFMguIO(vlen)) 215 216 val vd = io.in.vd 217 val oldvd = io.in.oldVd 218 val mask = io.in.mask 219 val vsew = io.in.info.eew 220 val num16bits = vlen / 16 221 222} 223 224class VFMguIO(vlen: Int)(implicit p: Parameters) extends Bundle { 225 val in = new Bundle { 226 val vd = Input(UInt(vlen.W)) 227 val oldVd = Input(UInt(vlen.W)) 228 val mask = Input(UInt(vlen.W)) 229 val info = Input(new VecInfo) 230 } 231 val out = new Bundle { 232 val vd = Output(UInt(vlen.W)) 233 } 234}