1package xiangshan.backend.fu.wrapper 2 3import chipsalliance.rocketchip.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import utils.XSError 7import xiangshan.backend.fu.FuConfig 8import xiangshan.backend.fu.vector.Bundles.VSew 9import xiangshan.backend.fu.vector.utils.VecDataSplitModule 10import xiangshan.backend.fu.vector.{Mgu, Utils, VecPipedFuncUnit, VecSrcTypeModule} 11import yunsuan.VfpuType 12import yunsuan.encoding.Opcode.VimacOpcode 13import yunsuan.encoding.{VdType, Vs1IntType, Vs2IntType} 14import yunsuan.{OpType, VimacType} 15import yunsuan.vector.VectorFloatAdder 16import yunsuan.vector.mac.VIMac64b 17 18class VFAlu(cfg: FuConfig)(implicit p: Parameters) extends VecPipedFuncUnit(cfg) { 19 XSError(io.in.valid && io.in.bits.ctrl.fuOpType === VfpuType.dummy, "Vfalu OpType not supported") 20 21 // params alias 22 private val dataWidth = cfg.dataBits 23 private val dataWidthOfDataModule = 64 24 private val numVecModule = dataWidth / dataWidthOfDataModule 25 26 // io alias 27 private val opcode = fuOpType(4,0) 28 private val resWiden = fuOpType(5) 29 private val opbWiden = fuOpType(6) 30 31 // modules 32 private val vfalus = Seq.fill(numVecModule)(Module(new VectorFloatAdder)) 33 private val vs2Split = Module(new VecDataSplitModule(dataWidth, dataWidthOfDataModule)) 34 private val vs1Split = Module(new VecDataSplitModule(dataWidth, dataWidthOfDataModule)) 35 private val oldVdSplit = Module(new VecDataSplitModule(dataWidth, dataWidthOfDataModule)) 36// private val mgu = Module(new Mgu(dataWidth)) 37 38 /** 39 * In connection of [[vs2Split]], [[vs1Split]] and [[oldVdSplit]] 40 */ 41 vs2Split.io.inVecData := vs2 42 vs1Split.io.inVecData := vs1 43 oldVdSplit.io.inVecData := oldVd 44 45 /** 46 * [[vfalus]]'s in connection 47 */ 48 // Vec(vs2(31,0), vs2(63,32), vs2(95,64), vs2(127,96)) ==> 49 // Vec( 50 // Cat(vs2(95,64), vs2(31,0)), 51 // Cat(vs2(127,96), vs2(63,32)), 52 // ) 53 private val vs2GroupedVec: Vec[UInt] = VecInit(vs2Split.io.outVec32b.zipWithIndex.groupBy(_._2 % 2).map(x => x._1 -> x._2.map(_._1)).values.map(x => Cat(x.reverse)).toSeq) 54 private val vs1GroupedVec: Vec[UInt] = VecInit(vs1Split.io.outVec32b.zipWithIndex.groupBy(_._2 % 2).map(x => x._1 -> x._2.map(_._1)).values.map(x => Cat(x.reverse)).toSeq) 55 56 vfalus.zipWithIndex.foreach { 57 case (mod, i) => 58 mod.io.fp_a := vs2Split.io.outVec64b(i) 59 mod.io.fp_b := vs1Split.io.outVec64b(i) 60 mod.io.widen_a := Cat(vs2Split.io.outVec32b(i+numVecModule), vs2Split.io.outVec32b(i)) 61 mod.io.widen_b := Cat(vs1Split.io.outVec32b(i+numVecModule), vs1Split.io.outVec32b(i)) 62 mod.io.frs1 := 0.U // already vf -> vv 63 mod.io.is_frs1 := false.B // already vf -> vv 64 mod.io.mask := 0.U // Todo 65 mod.io.uop_idx := vuopIdx(0) 66 mod.io.is_vec := true.B // Todo 67 mod.io.round_mode := frm 68 mod.io.fp_format := vsew 69 mod.io.opb_widening := opbWiden 70 mod.io.res_widening := resWiden 71 mod.io.op_code := opcode 72 } 73 io.out.bits.res.data := vfalus.map(_.io.fp_result).reduceRight(Cat(_,_)) 74 val allFFlagsEn = Wire(Vec(4*numVecModule,Bool())) 75 allFFlagsEn.foreach(en => en := true.B) // Todo 76 val allFFlags = vfalus.map(_.io.fflags).reduceRight(Cat(_,_)).asTypeOf(Vec(4*numVecModule,UInt(5.W))) 77 val outFFlags = allFFlagsEn.zip(allFFlags).map{ 78 case(en,fflags) => Mux(en, fflags, 0.U(5.W)) 79 }.reduce(_ | _) 80 io.out.bits.res.fflags.get := outFFlags//vfalus.map(_.io.fflags).reduceRight(_ | _).asTypeOf(Vec(4,UInt(5.W))).reduce(_ | _) 81} 82