1package xiangshan.backend.fu.wrapper 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import utils.XSError 7import xiangshan.backend.fu.FuConfig 8import xiangshan.backend.fu.vector.Bundles.{VLmul, VSew, ma} 9import xiangshan.backend.fu.vector.utils.VecDataSplitModule 10import xiangshan.backend.fu.vector.{Mgu, VecInfo, VecPipedFuncUnit} 11import xiangshan.ExceptionNO 12import yunsuan.{VfaluType, VfpuType} 13import yunsuan.vector.VectorFloatAdder 14 15class VFAlu(cfg: FuConfig)(implicit p: Parameters) extends VecPipedFuncUnit(cfg) { 16 XSError(io.in.valid && io.in.bits.ctrl.fuOpType === VfpuType.dummy, "Vfalu OpType not supported") 17 18 // params alias 19 private val dataWidth = cfg.dataBits 20 private val dataWidthOfDataModule = 64 21 private val numVecModule = dataWidth / dataWidthOfDataModule 22 23 // io alias 24 private val opcode = fuOpType(4,0) 25 private val resWiden = fuOpType(5) 26 private val opbWiden = fuOpType(6) 27 28 // modules 29 private val vfalus = Seq.fill(numVecModule)(Module(new VectorFloatAdder)) 30 private val vs2Split = Module(new VecDataSplitModule(dataWidth, dataWidthOfDataModule)) 31 private val vs1Split = Module(new VecDataSplitModule(dataWidth, dataWidthOfDataModule)) 32 private val oldVdSplit = Module(new VecDataSplitModule(dataWidth, dataWidthOfDataModule)) 33 private val mgu = Module(new Mgu(dataWidth)) 34 35 /** 36 * In connection of [[vs2Split]], [[vs1Split]] and [[oldVdSplit]] 37 */ 38 vs2Split.io.inVecData := vs2 39 vs1Split.io.inVecData := vs1 40 oldVdSplit.io.inVecData := oldVd 41 42 /** 43 * [[vfalus]]'s in connection 44 */ 45 // Vec(vs2(31,0), vs2(63,32), vs2(95,64), vs2(127,96)) ==> 46 // Vec( 47 // Cat(vs2(95,64), vs2(31,0)), 48 // Cat(vs2(127,96), vs2(63,32)), 49 // ) 50 private val vs2GroupedVec: Vec[UInt] = VecInit(vs2Split.io.outVec32b.zipWithIndex.groupBy(_._2 % 2).map(x => x._1 -> x._2.map(_._1)).values.map(x => Cat(x.reverse)).toSeq) 51 private val vs1GroupedVec: Vec[UInt] = VecInit(vs1Split.io.outVec32b.zipWithIndex.groupBy(_._2 % 2).map(x => x._1 -> x._2.map(_._1)).values.map(x => Cat(x.reverse)).toSeq) 52 private val resultData = Wire(Vec(numVecModule,UInt(dataWidthOfDataModule.W))) 53 private val fflagsData = Wire(Vec(numVecModule,UInt(20.W))) 54 private val srcMaskRShiftForReduction = Wire(UInt((8 * numVecModule).W)) 55 // for reduction 56 val isFirstGroupUop = vuopIdx === 0.U || 57 (vuopIdx === 1.U && (vlmul === VLmul.m4 || vlmul === VLmul.m8)) || 58 ((vuopIdx === 2.U || vuopIdx === 3.U) && vlmul === VLmul.m8) 59 val maskRshiftWidthForReduction = Wire(UInt(6.W)) 60 maskRshiftWidthForReduction := Mux(fuOpType === VfaluType.vfredosum, 61 vuopIdx, 62 Mux1H(Seq( 63 (vsew === VSew.e16) -> (vuopIdx(1, 0) << 4), 64 (vsew === VSew.e32) -> (vuopIdx(1, 0) << 3), 65 (vsew === VSew.e64) -> (vuopIdx(1, 0) << 2), 66 )) 67 ) 68 val vlMaskForReduction = (~(Fill(VLEN, 1.U) << vl)).asUInt 69 srcMaskRShiftForReduction := ((srcMask & vlMaskForReduction) >> maskRshiftWidthForReduction)(8 * numVecModule - 1, 0) 70 71 def genMaskForReduction(inmask: UInt, sew: UInt, i: Int): UInt = { 72 val f64MaskNum = dataWidth / 64 * 2 73 val f32MaskNum = dataWidth / 32 * 2 74 val f16MaskNum = dataWidth / 16 * 2 75 val f64Mask = inmask(f64MaskNum - 1, 0) 76 val f32Mask = inmask(f32MaskNum - 1, 0) 77 val f16Mask = inmask(f16MaskNum - 1, 0) 78 // vs2 reordered, so mask use high bits 79 val f64FirstFoldMask = Mux1H( 80 Seq( 81 vecCtrl.fpu.isFoldTo1_2 -> Cat(0.U(3.W), f64Mask(0), 0.U(3.W), f64Mask(1)), 82 ) 83 ) 84 val f32FirstFoldMask = Mux1H( 85 Seq( 86 vecCtrl.fpu.isFoldTo1_2 -> Cat(0.U(2.W), f32Mask(1), f32Mask(0), 0.U(2.W), f32Mask(3), f32Mask(2)), 87 vecCtrl.fpu.isFoldTo1_4 -> Cat(0.U(3.W), f32Mask(0), 0.U(3.W), f32Mask(1)), 88 ) 89 ) 90 val f16FirstFoldMask = Mux1H( 91 Seq( 92 vecCtrl.fpu.isFoldTo1_2 -> Cat(f16Mask(7,4), f16Mask(3,0)), 93 vecCtrl.fpu.isFoldTo1_4 -> Cat(0.U(2.W), f16Mask(1), f16Mask(0), 0.U(2.W), f16Mask(3), f16Mask(2)), 94 vecCtrl.fpu.isFoldTo1_8 -> Cat(0.U(3.W), f16Mask(0), 0.U(3.W), f16Mask(1)), 95 ) 96 ) 97 val f64FoldMask = Mux1H( 98 Seq( 99 vecCtrl.fpu.isFoldTo1_2 -> "b00010001".U, 100 ) 101 ) 102 val f32FoldMask = Mux1H( 103 Seq( 104 vecCtrl.fpu.isFoldTo1_2 -> "b00110011".U, 105 vecCtrl.fpu.isFoldTo1_4 -> "b00010001".U, 106 ) 107 ) 108 val f16FoldMask = Mux1H( 109 Seq( 110 vecCtrl.fpu.isFoldTo1_2 -> "b11111111".U, 111 vecCtrl.fpu.isFoldTo1_4 -> "b00110011".U, 112 vecCtrl.fpu.isFoldTo1_8 -> "b00010001".U, 113 ) 114 ) 115 // low 4 bits for vs2(fp_a), high 4 bits for vs1(fp_b), 116 val isFold = vecCtrl.fpu.isFoldTo1_2 || vecCtrl.fpu.isFoldTo1_4 || vecCtrl.fpu.isFoldTo1_8 117 val f64FirstNotFoldMask = Cat(0.U(3.W), f64Mask(i+2), 0.U(3.W), f64Mask(i)) 118 val f32FirstNotFoldMask = Cat(0.U(2.W), f32Mask(i + 5, i+4), 0.U(2.W), Cat(f32Mask(i + 1, i))) 119 val f16FirstNotFoldMask = Cat(f16Mask(i+11,i+8), f16Mask(i+3,0)) 120 val f64MaskI = Mux(isFirstGroupUop, Mux(isFold, f64FirstFoldMask, f64FirstNotFoldMask), Mux(isFold, f64FoldMask, Fill(8,1.U))) 121 val f32MaskI = Mux(isFirstGroupUop, Mux(isFold, f32FirstFoldMask, f32FirstNotFoldMask), Mux(isFold, f32FoldMask, Fill(8,1.U))) 122 val f16MaskI = Mux(isFirstGroupUop, Mux(isFold, f16FirstFoldMask, f16FirstNotFoldMask), Mux(isFold, f16FoldMask, Fill(8,1.U))) 123 val outMask = Mux1H( 124 Seq( 125 (sew === 3.U) -> f64MaskI, 126 (sew === 2.U) -> f32MaskI, 127 (sew === 1.U) -> f16MaskI, 128 ) 129 ) 130 Mux(fuOpType === VfaluType.vfredosum || fuOpType === VfaluType.vfwredosum, outMask(0),outMask) 131 } 132 def genMaskForMerge(inmask:UInt, sew:UInt, i:Int): UInt = { 133 val f64MaskNum = dataWidth / 64 134 val f32MaskNum = dataWidth / 32 135 val f16MaskNum = dataWidth / 16 136 val f64Mask = inmask(f64MaskNum-1,0) 137 val f32Mask = inmask(f32MaskNum-1,0) 138 val f16Mask = inmask(f16MaskNum-1,0) 139 val f64MaskI = Cat(0.U(3.W),f64Mask(i)) 140 val f32MaskI = Cat(0.U(2.W),f32Mask(2*i+1,2*i)) 141 val f16MaskI = f16Mask(4*i+3,4*i) 142 val outMask = Mux1H( 143 Seq( 144 (sew === 3.U) -> f64MaskI, 145 (sew === 2.U) -> f32MaskI, 146 (sew === 1.U) -> f16MaskI, 147 ) 148 ) 149 outMask 150 } 151 val isScalarMove = (fuOpType === VfaluType.vfmv_f_s) || (fuOpType === VfaluType.vfmv_s_f) 152 val srcMaskRShift = Wire(UInt((4 * numVecModule).W)) 153 val maskRshiftWidth = Wire(UInt(6.W)) 154 maskRshiftWidth := Mux1H( 155 Seq( 156 (vsew === VSew.e16) -> (vuopIdx(2,0) << 3), 157 (vsew === VSew.e32) -> (vuopIdx(2,0) << 2), 158 (vsew === VSew.e64) -> (vuopIdx(2,0) << 1), 159 ) 160 ) 161 srcMaskRShift := (srcMask >> maskRshiftWidth)(4 * numVecModule - 1, 0) 162 val fp_aIsFpCanonicalNAN = Wire(Vec(numVecModule,Bool())) 163 val fp_bIsFpCanonicalNAN = Wire(Vec(numVecModule,Bool())) 164 vfalus.zipWithIndex.foreach { 165 case (mod, i) => 166 mod.io.fp_a := Mux(opbWiden, vs1Split.io.outVec64b(i), vs2Split.io.outVec64b(i)) // very dirty TODO 167 mod.io.fp_b := Mux(opbWiden, vs2Split.io.outVec64b(i), vs1Split.io.outVec64b(i)) // very dirty TODO 168 mod.io.widen_a := Cat(vs2Split.io.outVec32b(i+numVecModule), vs2Split.io.outVec32b(i)) 169 mod.io.widen_b := Cat(vs1Split.io.outVec32b(i+numVecModule), vs1Split.io.outVec32b(i)) 170 mod.io.frs1 := 0.U // already vf -> vv 171 mod.io.is_frs1 := false.B // already vf -> vv 172 mod.io.mask := Mux(isScalarMove, !vuopIdx.orR, genMaskForMerge(inmask = srcMaskRShift, sew = vsew, i = i)) 173 mod.io.maskForReduction := genMaskForReduction(inmask = srcMaskRShiftForReduction, sew = vsew, i = i) 174 mod.io.uop_idx := Mux(fuOpType === VfaluType.vfwredosum, 0.U, vuopIdx(0)) 175 mod.io.is_vec := true.B // Todo 176 mod.io.round_mode := frm 177 mod.io.fp_format := Mux(resWiden, vsew + 1.U, vsew) 178 mod.io.opb_widening := opbWiden || (fuOpType === VfaluType.vfwredosum) 179 mod.io.res_widening := resWiden 180 mod.io.op_code := opcode 181 resultData(i) := mod.io.fp_result 182 fflagsData(i) := mod.io.fflags 183 fp_aIsFpCanonicalNAN(i) := vecCtrl.fpu.isFpToVecInst & ( 184 ((vsew === VSew.e32) & (!vs2Split.io.outVec64b(i).head(32).andR)) | 185 ((vsew === VSew.e16) & (!vs2Split.io.outVec64b(i).head(48).andR)) 186 ) 187 fp_bIsFpCanonicalNAN(i) := vecCtrl.fpu.isFpToVecInst & ( 188 ((vsew === VSew.e32) & (!vs1Split.io.outVec64b(i).head(32).andR)) | 189 ((vsew === VSew.e16) & (!vs1Split.io.outVec64b(i).head(48).andR)) 190 ) 191 mod.io.fp_aIsFpCanonicalNAN := fp_aIsFpCanonicalNAN(i) 192 mod.io.fp_bIsFpCanonicalNAN := fp_bIsFpCanonicalNAN(i) 193 } 194 val resultDataUInt = resultData.asUInt 195 val cmpResultWidth = dataWidth / 16 196 val cmpResult = Wire(Vec(cmpResultWidth, Bool())) 197 for (i <- 0 until cmpResultWidth) { 198 if(i == 0) { 199 cmpResult(i) := resultDataUInt(0) 200 } 201 else if(i < dataWidth / 64) { 202 cmpResult(i) := Mux1H( 203 Seq( 204 (outVecCtrl.vsew === 1.U) -> resultDataUInt(i*16), 205 (outVecCtrl.vsew === 2.U) -> resultDataUInt(i*32), 206 (outVecCtrl.vsew === 3.U) -> resultDataUInt(i*64) 207 ) 208 ) 209 } 210 else if(i < dataWidth / 32) { 211 cmpResult(i) := Mux1H( 212 Seq( 213 (outVecCtrl.vsew === 1.U) -> resultDataUInt(i * 16), 214 (outVecCtrl.vsew === 2.U) -> resultDataUInt(i * 32), 215 (outVecCtrl.vsew === 3.U) -> false.B 216 ) 217 ) 218 } 219 else if(i < dataWidth / 16) { 220 cmpResult(i) := Mux(outVecCtrl.vsew === 1.U, resultDataUInt(i*16), false.B) 221 } 222 } 223 224 val outEew = Mux(RegNext(resWiden), outVecCtrl.vsew + 1.U, outVecCtrl.vsew) 225 val outVuopidx = outVecCtrl.vuopIdx(2, 0) 226 val vlMax = ((VLEN/8).U >> outEew).asUInt 227 val lmulAbs = Mux(outVecCtrl.vlmul(2), (~outVecCtrl.vlmul(1,0)).asUInt + 1.U, outVecCtrl.vlmul(1,0)) 228 // vfmv_f_s need vl=1, reduction last uop need vl=1, other uop need vl=vlmax 229 val numOfUopVFRED = { 230 // addTime include add frs1 231 val addTime = MuxLookup(outVecCtrl.vlmul, 1.U(4.W), Array( 232 VLmul.m2 -> 2.U, 233 VLmul.m4 -> 4.U, 234 VLmul.m8 -> 8.U, 235 )) 236 val foldLastVlmul = MuxLookup(outVecCtrl.vsew, "b000".U, Array( 237 VSew.e16 -> VLmul.mf8, 238 VSew.e32 -> VLmul.mf4, 239 VSew.e64 -> VLmul.mf2, 240 )) 241 // lmul < 1, foldTime = vlmul - foldFastVlmul 242 // lmul >= 1, foldTime = 0.U - foldFastVlmul 243 val foldTime = Mux(outVecCtrl.vlmul(2), outVecCtrl.vlmul, 0.U) - foldLastVlmul 244 addTime + foldTime 245 } 246 val reductionVl = Mux((outVecCtrl.vuopIdx === numOfUopVFRED - 1.U) || (outCtrl.fuOpType === VfaluType.vfredosum || outCtrl.fuOpType === VfaluType.vfwredosum), 1.U, vlMax) 247 val outIsResuction = outCtrl.fuOpType === VfaluType.vfredusum || 248 outCtrl.fuOpType === VfaluType.vfredmax || 249 outCtrl.fuOpType === VfaluType.vfredmin || 250 outCtrl.fuOpType === VfaluType.vfredosum || 251 outCtrl.fuOpType === VfaluType.vfwredosum 252 val outVlFix = Mux( 253 outVecCtrl.fpu.isFpToVecInst || (outCtrl.fuOpType === VfaluType.vfmv_f_s), 254 1.U, 255 Mux( 256 outCtrl.fuOpType === VfaluType.vfmv_s_f, 257 outVl.orR, 258 Mux(outIsResuction, reductionVl, outVl) 259 ) 260 ) 261 val vlMaxAllUop = Wire(outVl.cloneType) 262 vlMaxAllUop := Mux(outVecCtrl.vlmul(2), vlMax >> lmulAbs, vlMax << lmulAbs).asUInt 263 val vlMaxThisUop = Mux(outVecCtrl.vlmul(2), vlMax >> lmulAbs, vlMax).asUInt 264 val vlSetThisUop = Mux(outVlFix > outVuopidx*vlMaxThisUop, outVlFix - outVuopidx*vlMaxThisUop, 0.U) 265 val vlThisUop = Wire(UInt(3.W)) 266 vlThisUop := Mux(vlSetThisUop < vlMaxThisUop, vlSetThisUop, vlMaxThisUop) 267 val vlMaskRShift = Wire(UInt((4 * numVecModule).W)) 268 vlMaskRShift := Fill(4 * numVecModule, 1.U(1.W)) >> ((4 * numVecModule).U - vlThisUop) 269 270 private val needNoMask = outCtrl.fuOpType === VfaluType.vfmerge || 271 outCtrl.fuOpType === VfaluType.vfmv_s_f || 272 outIsResuction || 273 outVecCtrl.fpu.isFpToVecInst 274 val maskToMgu = Mux(needNoMask, allMaskTrue, outSrcMask) 275 val allFFlagsEn = Wire(Vec(4*numVecModule,Bool())) 276 val outSrcMaskRShift = Wire(UInt((4*numVecModule).W)) 277 outSrcMaskRShift := (maskToMgu >> (outVecCtrl.vuopIdx(2,0) * vlMax))(4*numVecModule-1,0) 278 val f16FFlagsEn = outSrcMaskRShift 279 val f32FFlagsEn = Wire(Vec(numVecModule,UInt(4.W))) 280 for (i <- 0 until numVecModule){ 281 f32FFlagsEn(i) := Cat(Fill(2, 0.U),outSrcMaskRShift(2*i+1,2*i)) 282 } 283 val f64FFlagsEn = Wire(Vec(numVecModule, UInt(4.W))) 284 for (i <- 0 until numVecModule) { 285 f64FFlagsEn(i) := Cat(Fill(3, 0.U), outSrcMaskRShift(i)) 286 } 287 val fflagsEn= Mux1H( 288 Seq( 289 (outEew === 1.U) -> f16FFlagsEn.asUInt, 290 (outEew === 2.U) -> f32FFlagsEn.asUInt, 291 (outEew === 3.U) -> f64FFlagsEn.asUInt 292 ) 293 ) 294 allFFlagsEn := Mux(outIsResuction, Fill(4*numVecModule, 1.U), (fflagsEn & vlMaskRShift)).asTypeOf(allFFlagsEn) 295 296 val allFFlags = fflagsData.asTypeOf(Vec(4*numVecModule,UInt(5.W))) 297 val outFFlags = allFFlagsEn.zip(allFFlags).map{ 298 case(en,fflags) => Mux(en, fflags, 0.U(5.W)) 299 }.reduce(_ | _) 300 io.out.bits.res.fflags.get := outFFlags 301 302 303 val cmpResultOldVd = Wire(UInt(cmpResultWidth.W)) 304 val cmpResultOldVdRshiftWidth = Wire(UInt(6.W)) 305 cmpResultOldVdRshiftWidth := Mux1H( 306 Seq( 307 (outVecCtrl.vsew === VSew.e16) -> (outVecCtrl.vuopIdx(2, 0) << 3), 308 (outVecCtrl.vsew === VSew.e32) -> (outVecCtrl.vuopIdx(2, 0) << 2), 309 (outVecCtrl.vsew === VSew.e64) -> (outVecCtrl.vuopIdx(2, 0) << 1), 310 ) 311 ) 312 cmpResultOldVd := (outOldVd >> cmpResultOldVdRshiftWidth)(4*numVecModule-1,0) 313 val cmpResultForMgu = Wire(Vec(cmpResultWidth, Bool())) 314 for (i <- 0 until cmpResultWidth) { 315 cmpResultForMgu(i) := Mux(outSrcMaskRShift(i), cmpResult(i), Mux(outVecCtrl.vma, true.B, cmpResultOldVd(i))) 316 } 317 val outIsFold = outVecCtrl.fpu.isFoldTo1_2 || outVecCtrl.fpu.isFoldTo1_4 || outVecCtrl.fpu.isFoldTo1_8 318 val outOldVdForREDO = Mux1H(Seq( 319 (outVecCtrl.vsew === VSew.e16) -> (outOldVd >> 16), 320 (outVecCtrl.vsew === VSew.e32) -> (outOldVd >> 32), 321 (outVecCtrl.vsew === VSew.e64) -> (outOldVd >> 64), 322 )) 323 val outOldVdForWREDO = Mux( 324 !outIsFold, 325 Mux(outVecCtrl.vsew === VSew.e16, Cat(outOldVd(VLEN-1-16,16), 0.U(32.W)), Cat(outOldVd(VLEN-1-32,32), 0.U(64.W))), 326 Mux(outVecCtrl.vsew === VSew.e16, 327 // Divide vuopIdx by 8 and the remainder is 1 328 Mux(outVecCtrl.vuopIdx(2,0) === 1.U, outOldVd, outOldVd >> 16), 329 // Divide vuopIdx by 4 and the remainder is 1 330 Mux(outVecCtrl.vuopIdx(1,0) === 1.U, outOldVd, outOldVd >> 32) 331 ), 332 ) 333 val outOldVdForRED = Mux(outCtrl.fuOpType === VfaluType.vfredosum, outOldVdForREDO, outOldVdForWREDO) 334 val numOfUopVFREDOSUM = { 335 val uvlMax = MuxLookup(outVecCtrl.vsew, 0.U, Array( 336 VSew.e16 -> 8.U, 337 VSew.e32 -> 4.U, 338 VSew.e64 -> 2.U, 339 )) 340 val vlMax = Mux(outVecCtrl.vlmul(2), uvlMax >> (-outVecCtrl.vlmul)(1, 0), uvlMax << outVecCtrl.vlmul(1, 0)).asUInt 341 vlMax 342 } 343 val isOutOldVdForREDO = (outCtrl.fuOpType === VfaluType.vfredosum && outIsFold) || outCtrl.fuOpType === VfaluType.vfwredosum 344 val taIsFalseForVFREDO = ((outCtrl.fuOpType === VfaluType.vfredosum) || (outCtrl.fuOpType === VfaluType.vfwredosum)) && (outVecCtrl.vuopIdx =/= numOfUopVFREDOSUM - 1.U) 345 mgu.io.in.vd := Mux(outVecCtrl.isDstMask, Cat(0.U((dataWidth / 16 * 15).W), cmpResultForMgu.asUInt), resultDataUInt) 346 mgu.io.in.oldVd := Mux(isOutOldVdForREDO, outOldVdForRED, outOldVd) 347 mgu.io.in.mask := maskToMgu 348 mgu.io.in.info.ta := Mux(outCtrl.fuOpType === VfaluType.vfmv_f_s, true.B , Mux(taIsFalseForVFREDO, false.B, outVecCtrl.vta)) 349 mgu.io.in.info.ma := Mux(outCtrl.fuOpType === VfaluType.vfmv_s_f, true.B , outVecCtrl.vma) 350 mgu.io.in.info.vl := outVlFix 351 mgu.io.in.info.vstart := outVecCtrl.vstart 352 mgu.io.in.info.vlmul := outVecCtrl.vlmul 353 mgu.io.in.info.valid := io.out.valid 354 mgu.io.in.info.vstart := Mux(outVecCtrl.fpu.isFpToVecInst, 0.U, outVecCtrl.vstart) 355 mgu.io.in.info.eew := outEew 356 mgu.io.in.info.vsew := outVecCtrl.vsew 357 mgu.io.in.info.vdIdx := Mux(outIsResuction, 0.U, outVecCtrl.vuopIdx) 358 mgu.io.in.info.narrow := outVecCtrl.isNarrow 359 mgu.io.in.info.dstMask := outVecCtrl.isDstMask 360 mgu.io.in.isIndexedVls := false.B 361 val resultFpMask = Wire(UInt(VLEN.W)) 362 val isFclass = outVecCtrl.fpu.isFpToVecInst && (outCtrl.fuOpType === VfaluType.vfclass) 363 val fpCmpFuOpType = Seq(VfaluType.vfeq, VfaluType.vflt, VfaluType.vfle) 364 val isCmp = outVecCtrl.fpu.isFpToVecInst && (fpCmpFuOpType.map(_ === outCtrl.fuOpType).reduce(_|_)) 365 resultFpMask := Mux(isFclass || isCmp, Fill(16, 1.U(1.W)), Fill(VLEN, 1.U(1.W))) 366 io.out.bits.res.data := mgu.io.out.vd & resultFpMask 367 io.out.bits.ctrl.exceptionVec.get(ExceptionNO.illegalInstr) := mgu.io.out.illegal 368 369} 370 371class VFMgu(vlen:Int)(implicit p: Parameters) extends Module{ 372 val io = IO(new VFMguIO(vlen)) 373 374 val vd = io.in.vd 375 val oldvd = io.in.oldVd 376 val mask = io.in.mask 377 val vsew = io.in.info.eew 378 val num16bits = vlen / 16 379 380} 381 382class VFMguIO(vlen: Int)(implicit p: Parameters) extends Bundle { 383 val in = new Bundle { 384 val vd = Input(UInt(vlen.W)) 385 val oldVd = Input(UInt(vlen.W)) 386 val mask = Input(UInt(vlen.W)) 387 val info = Input(new VecInfo) 388 } 389 val out = new Bundle { 390 val vd = Output(UInt(vlen.W)) 391 } 392}