1package xiangshan.backend.fu.wrapper 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import utils.XSError 7import xiangshan.backend.fu.FuConfig 8import xiangshan.backend.fu.vector.Bundles.{VLmul, VSew, ma} 9import xiangshan.backend.fu.vector.utils.VecDataSplitModule 10import xiangshan.backend.fu.vector.{Mgu, Mgtu, VecInfo, VecPipedFuncUnit} 11import xiangshan.ExceptionNO 12import yunsuan.{VfaluType, VfpuType} 13import yunsuan.vector.VectorFloatAdder 14 15class VFAlu(cfg: FuConfig)(implicit p: Parameters) extends VecPipedFuncUnit(cfg) { 16 XSError(io.in.valid && io.in.bits.ctrl.fuOpType === VfpuType.dummy, "Vfalu OpType not supported") 17 18 // params alias 19 private val dataWidth = cfg.dataBits 20 private val dataWidthOfDataModule = 64 21 private val numVecModule = dataWidth / dataWidthOfDataModule 22 23 // io alias 24 private val opcode = fuOpType(4,0) 25 private val resWiden = fuOpType(5) 26 private val opbWiden = fuOpType(6) 27 28 // modules 29 private val vfalus = Seq.fill(numVecModule)(Module(new VectorFloatAdder)) 30 private val vs2Split = Module(new VecDataSplitModule(dataWidth, dataWidthOfDataModule)) 31 private val vs1Split = Module(new VecDataSplitModule(dataWidth, dataWidthOfDataModule)) 32 private val oldVdSplit = Module(new VecDataSplitModule(dataWidth, dataWidthOfDataModule)) 33 private val mgu = Module(new Mgu(dataWidth)) 34 private val mgtu = Module(new Mgtu(dataWidth)) 35 36 /** 37 * In connection of [[vs2Split]], [[vs1Split]] and [[oldVdSplit]] 38 */ 39 vs2Split.io.inVecData := vs2 40 vs1Split.io.inVecData := vs1 41 oldVdSplit.io.inVecData := oldVd 42 43 /** 44 * [[vfalus]]'s in connection 45 */ 46 // Vec(vs2(31,0), vs2(63,32), vs2(95,64), vs2(127,96)) ==> 47 // Vec( 48 // Cat(vs2(95,64), vs2(31,0)), 49 // Cat(vs2(127,96), vs2(63,32)), 50 // ) 51 private val vs2GroupedVec: Vec[UInt] = VecInit(vs2Split.io.outVec32b.zipWithIndex.groupBy(_._2 % 2).map(x => x._1 -> x._2.map(_._1)).values.map(x => Cat(x.reverse)).toSeq) 52 private val vs1GroupedVec: Vec[UInt] = VecInit(vs1Split.io.outVec32b.zipWithIndex.groupBy(_._2 % 2).map(x => x._1 -> x._2.map(_._1)).values.map(x => Cat(x.reverse)).toSeq) 53 private val resultData = Wire(Vec(numVecModule,UInt(dataWidthOfDataModule.W))) 54 private val fflagsData = Wire(Vec(numVecModule,UInt(20.W))) 55 private val srcMaskRShiftForReduction = Wire(UInt((8 * numVecModule).W)) 56 // for reduction 57 val isFirstGroupUop = vuopIdx === 0.U || 58 (vuopIdx === 1.U && (vlmul === VLmul.m4 || vlmul === VLmul.m8)) || 59 ((vuopIdx === 2.U || vuopIdx === 3.U) && vlmul === VLmul.m8) 60 val maskRshiftWidthForReduction = Wire(UInt(6.W)) 61 maskRshiftWidthForReduction := Mux(fuOpType === VfaluType.vfredosum || fuOpType === VfaluType.vfwredosum, 62 vuopIdx, 63 Mux1H(Seq( 64 (vsew === VSew.e16) -> (vuopIdx(1, 0) << 4), 65 (vsew === VSew.e32) -> (vuopIdx(1, 0) << 3), 66 (vsew === VSew.e64) -> (vuopIdx(1, 0) << 2), 67 )) 68 ) 69 val vlMaskForReduction = (~(Fill(VLEN, 1.U) << vl)).asUInt 70 srcMaskRShiftForReduction := ((srcMask & vlMaskForReduction) >> maskRshiftWidthForReduction)(8 * numVecModule - 1, 0) 71 72 def genMaskForReduction(inmask: UInt, sew: UInt, i: Int): UInt = { 73 val f64MaskNum = dataWidth / 64 * 2 74 val f32MaskNum = dataWidth / 32 * 2 75 val f16MaskNum = dataWidth / 16 * 2 76 val f64Mask = inmask(f64MaskNum - 1, 0) 77 val f32Mask = inmask(f32MaskNum - 1, 0) 78 val f16Mask = inmask(f16MaskNum - 1, 0) 79 // vs2 reordered, so mask use high bits 80 val f64FirstFoldMaskUnorder = Mux1H( 81 Seq( 82 vecCtrl.fpu.isFoldTo1_2 -> Cat(0.U(3.W), f64Mask(0), 0.U(3.W), f64Mask(1)), 83 ) 84 ) 85 val f64FirstFoldMaskOrder = Mux1H( 86 Seq( 87 vecCtrl.fpu.isFoldTo1_2 -> Cat(0.U(3.W), f64Mask(1), 0.U(3.W), f64Mask(0)) 88 ) 89 ) 90 val f32FirstFoldMaskUnorder = Mux1H( 91 Seq( 92 vecCtrl.fpu.isFoldTo1_2 -> Cat(0.U(2.W), f32Mask(1), f32Mask(0), 0.U(2.W), f32Mask(3), f32Mask(2)), 93 vecCtrl.fpu.isFoldTo1_4 -> Cat(0.U(3.W), f32Mask(0), 0.U(3.W), f32Mask(1)), 94 ) 95 ) 96 val f32FirstFoldMaskOrder = Mux1H( 97 Seq( 98 vecCtrl.fpu.isFoldTo1_2 -> Cat(0.U(2.W), f32Mask(3), f32Mask(2), 0.U(2.W), f32Mask(1), f32Mask(0)), 99 vecCtrl.fpu.isFoldTo1_4 -> Cat(0.U(3.W), f32Mask(1), 0.U(3.W), f32Mask(0)), 100 ) 101 ) 102 val f16FirstFoldMaskUnorder = Mux1H( 103 Seq( 104 vecCtrl.fpu.isFoldTo1_2 -> Cat(f16Mask(7,4), f16Mask(3,0)), 105 vecCtrl.fpu.isFoldTo1_4 -> Cat(0.U(2.W), f16Mask(1), f16Mask(0), 0.U(2.W), f16Mask(3), f16Mask(2)), 106 vecCtrl.fpu.isFoldTo1_8 -> Cat(0.U(3.W), f16Mask(0), 0.U(3.W), f16Mask(1)), 107 ) 108 ) 109 val f16FirstFoldMaskOrder = Mux1H( 110 Seq( 111 vecCtrl.fpu.isFoldTo1_2 -> Cat(f16Mask(7,4), f16Mask(3,0)), 112 vecCtrl.fpu.isFoldTo1_4 -> Cat(0.U(2.W), f16Mask(3), f16Mask(2), 0.U(2.W), f16Mask(1), f16Mask(0)), 113 vecCtrl.fpu.isFoldTo1_8 -> Cat(0.U(3.W), f16Mask(1), 0.U(3.W), f16Mask(0)), 114 ) 115 ) 116 val f64FoldMask = Mux1H( 117 Seq( 118 vecCtrl.fpu.isFoldTo1_2 -> "b00010001".U, 119 ) 120 ) 121 val f32FoldMask = Mux1H( 122 Seq( 123 vecCtrl.fpu.isFoldTo1_2 -> "b00110011".U, 124 vecCtrl.fpu.isFoldTo1_4 -> "b00010001".U, 125 ) 126 ) 127 val f16FoldMask = Mux1H( 128 Seq( 129 vecCtrl.fpu.isFoldTo1_2 -> "b11111111".U, 130 vecCtrl.fpu.isFoldTo1_4 -> "b00110011".U, 131 vecCtrl.fpu.isFoldTo1_8 -> "b00010001".U, 132 ) 133 ) 134 // low 4 bits for vs2(fp_a), high 4 bits for vs1(fp_b), 135 val isFold = vecCtrl.fpu.isFoldTo1_2 || vecCtrl.fpu.isFoldTo1_4 || vecCtrl.fpu.isFoldTo1_8 136 val f64FirstNotFoldMask = Cat(0.U(3.W), f64Mask(i + 2), 0.U(3.W), f64Mask(i)) 137 val f32FirstNotFoldMask = Cat(0.U(2.W), f32Mask(i * 2 + 5, i * 2 + 4), 0.U(2.W), Cat(f32Mask(i * 2 + 1, i * 2))) 138 val f16FirstNotFoldMask = Cat(f16Mask(i * 4 + 11, i * 4 + 8), f16Mask(i * 4 + 3, i * 4)) 139 val f64MaskI = Mux(fuOpType === VfaluType.vfredosum || fuOpType === VfaluType.vfwredosum, 140 Mux(isFold, f64FirstFoldMaskOrder, f64FirstNotFoldMask), 141 Mux(isFirstGroupUop, 142 Mux(isFold, f64FirstFoldMaskUnorder, f64FirstNotFoldMask), 143 Mux(isFold, f64FoldMask, Fill(8, 1.U)))) 144 val f32MaskI = Mux(fuOpType === VfaluType.vfredosum || fuOpType === VfaluType.vfwredosum, 145 Mux(isFold, f32FirstFoldMaskOrder, f32FirstNotFoldMask), 146 Mux(isFirstGroupUop, 147 Mux(isFold, f32FirstFoldMaskUnorder, f32FirstNotFoldMask), 148 Mux(isFold, f32FoldMask, Fill(8, 1.U)))) 149 val f16MaskI = Mux(fuOpType === VfaluType.vfredosum || fuOpType === VfaluType.vfwredosum, 150 Mux(isFold, f16FirstFoldMaskOrder, f16FirstNotFoldMask), 151 Mux(isFirstGroupUop, 152 Mux(isFold, f16FirstFoldMaskUnorder, f16FirstNotFoldMask), 153 Mux(isFold, f16FoldMask, Fill(8, 1.U)))) 154 val outMask = Mux1H( 155 Seq( 156 (sew === 3.U) -> f64MaskI, 157 (sew === 2.U) -> f32MaskI, 158 (sew === 1.U) -> f16MaskI, 159 ) 160 ) 161 Mux(fuOpType === VfaluType.vfredosum || fuOpType === VfaluType.vfwredosum, outMask(0),outMask) 162 } 163 def genMaskForMerge(inmask:UInt, sew:UInt, i:Int): UInt = { 164 val f64MaskNum = dataWidth / 64 165 val f32MaskNum = dataWidth / 32 166 val f16MaskNum = dataWidth / 16 167 val f64Mask = inmask(f64MaskNum-1,0) 168 val f32Mask = inmask(f32MaskNum-1,0) 169 val f16Mask = inmask(f16MaskNum-1,0) 170 val f64MaskI = Cat(0.U(3.W),f64Mask(i)) 171 val f32MaskI = Cat(0.U(2.W),f32Mask(2*i+1,2*i)) 172 val f16MaskI = f16Mask(4*i+3,4*i) 173 val outMask = Mux1H( 174 Seq( 175 (sew === 3.U) -> f64MaskI, 176 (sew === 2.U) -> f32MaskI, 177 (sew === 1.U) -> f16MaskI, 178 ) 179 ) 180 outMask 181 } 182 val isScalarMove = (fuOpType === VfaluType.vfmv_f_s) || (fuOpType === VfaluType.vfmv_s_f) 183 val srcMaskRShift = Wire(UInt((4 * numVecModule).W)) 184 val maskRshiftWidth = Wire(UInt(6.W)) 185 maskRshiftWidth := Mux1H( 186 Seq( 187 (vsew === VSew.e16) -> (vuopIdx(2,0) << 3), 188 (vsew === VSew.e32) -> (vuopIdx(2,0) << 2), 189 (vsew === VSew.e64) -> (vuopIdx(2,0) << 1), 190 ) 191 ) 192 srcMaskRShift := (srcMask >> maskRshiftWidth)(4 * numVecModule - 1, 0) 193 val fp_aIsFpCanonicalNAN = Wire(Vec(numVecModule,Bool())) 194 val fp_bIsFpCanonicalNAN = Wire(Vec(numVecModule,Bool())) 195 val inIsFold = Wire(UInt(3.W)) 196 inIsFold := Cat(vecCtrl.fpu.isFoldTo1_8, vecCtrl.fpu.isFoldTo1_4, vecCtrl.fpu.isFoldTo1_2) 197 vfalus.zipWithIndex.foreach { 198 case (mod, i) => 199 mod.io.fire := io.in.valid 200 mod.io.fp_a := vs2Split.io.outVec64b(i) 201 mod.io.fp_b := vs1Split.io.outVec64b(i) 202 mod.io.widen_a := Cat(vs2Split.io.outVec32b(i+numVecModule), vs2Split.io.outVec32b(i)) 203 mod.io.widen_b := Cat(vs1Split.io.outVec32b(i+numVecModule), vs1Split.io.outVec32b(i)) 204 mod.io.frs1 := 0.U // already vf -> vv 205 mod.io.is_frs1 := false.B // already vf -> vv 206 mod.io.mask := Mux(isScalarMove, !vuopIdx.orR, genMaskForMerge(inmask = srcMaskRShift, sew = vsew, i = i)) 207 mod.io.maskForReduction := genMaskForReduction(inmask = srcMaskRShiftForReduction, sew = vsew, i = i) 208 mod.io.uop_idx := vuopIdx(0) 209 mod.io.is_vec := true.B // Todo 210 mod.io.round_mode := frm 211 mod.io.fp_format := Mux(resWiden, vsew + 1.U, vsew) 212 mod.io.opb_widening := opbWiden 213 mod.io.res_widening := resWiden 214 mod.io.op_code := opcode 215 mod.io.is_vfwredosum := fuOpType === VfaluType.vfwredosum 216 mod.io.is_fold := inIsFold 217 mod.io.vs2_fold := vs2 // for better timing 218 resultData(i) := mod.io.fp_result 219 fflagsData(i) := mod.io.fflags 220 fp_aIsFpCanonicalNAN(i) := vecCtrl.fpu.isFpToVecInst & ( 221 ((vsew === VSew.e32) & (!vs2Split.io.outVec64b(i).head(32).andR)) | 222 ((vsew === VSew.e16) & (!vs2Split.io.outVec64b(i).head(48).andR)) 223 ) 224 fp_bIsFpCanonicalNAN(i) := vecCtrl.fpu.isFpToVecInst & ( 225 ((vsew === VSew.e32) & (!vs1Split.io.outVec64b(i).head(32).andR)) | 226 ((vsew === VSew.e16) & (!vs1Split.io.outVec64b(i).head(48).andR)) 227 ) 228 mod.io.fp_aIsFpCanonicalNAN := fp_aIsFpCanonicalNAN(i) 229 mod.io.fp_bIsFpCanonicalNAN := fp_bIsFpCanonicalNAN(i) 230 } 231 val resultDataUInt = resultData.asUInt 232 val cmpResultWidth = dataWidth / 16 233 val cmpResult = Wire(Vec(cmpResultWidth, Bool())) 234 for (i <- 0 until cmpResultWidth) { 235 if(i == 0) { 236 cmpResult(i) := resultDataUInt(0) 237 } 238 else if(i < dataWidth / 64) { 239 cmpResult(i) := Mux1H( 240 Seq( 241 (outVecCtrl.vsew === 1.U) -> resultDataUInt(i*16), 242 (outVecCtrl.vsew === 2.U) -> resultDataUInt(i*32), 243 (outVecCtrl.vsew === 3.U) -> resultDataUInt(i*64) 244 ) 245 ) 246 } 247 else if(i < dataWidth / 32) { 248 cmpResult(i) := Mux1H( 249 Seq( 250 (outVecCtrl.vsew === 1.U) -> resultDataUInt(i * 16), 251 (outVecCtrl.vsew === 2.U) -> resultDataUInt(i * 32), 252 (outVecCtrl.vsew === 3.U) -> false.B 253 ) 254 ) 255 } 256 else if(i < dataWidth / 16) { 257 cmpResult(i) := Mux(outVecCtrl.vsew === 1.U, resultDataUInt(i*16), false.B) 258 } 259 } 260 261 val outEew = Mux(RegEnable(resWiden, io.in.fire), outVecCtrl.vsew + 1.U, outVecCtrl.vsew) 262 val outVuopidx = outVecCtrl.vuopIdx(2, 0) 263 val vlMax = ((VLEN/8).U >> outEew).asUInt 264 val lmulAbs = Mux(outVecCtrl.vlmul(2), (~outVecCtrl.vlmul(1,0)).asUInt + 1.U, outVecCtrl.vlmul(1,0)) 265 // vfmv_f_s need vl=1, reduction last uop need vl=1, other uop need vl=vlmax 266 val numOfUopVFRED = { 267 // addTime include add frs1 268 val addTime = MuxLookup(outVecCtrl.vlmul, 1.U(4.W))(Array( 269 VLmul.m2 -> 2.U, 270 VLmul.m4 -> 4.U, 271 VLmul.m8 -> 8.U, 272 )) 273 val foldLastVlmul = MuxLookup(outVecCtrl.vsew, "b000".U)(Array( 274 VSew.e16 -> VLmul.mf8, 275 VSew.e32 -> VLmul.mf4, 276 VSew.e64 -> VLmul.mf2, 277 )) 278 // lmul < 1, foldTime = vlmul - foldFastVlmul 279 // lmul >= 1, foldTime = 0.U - foldFastVlmul 280 val foldTime = Mux(outVecCtrl.vlmul(2), outVecCtrl.vlmul, 0.U) - foldLastVlmul 281 addTime + foldTime 282 } 283 val reductionVl = Mux((outVecCtrl.vuopIdx === numOfUopVFRED - 1.U) || (outCtrl.fuOpType === VfaluType.vfredosum || outCtrl.fuOpType === VfaluType.vfwredosum), 1.U, vlMax) 284 val outIsResuction = outCtrl.fuOpType === VfaluType.vfredusum || 285 outCtrl.fuOpType === VfaluType.vfredmax || 286 outCtrl.fuOpType === VfaluType.vfredmin || 287 outCtrl.fuOpType === VfaluType.vfredosum || 288 outCtrl.fuOpType === VfaluType.vfwredosum 289 val outVlFix = Mux( 290 outVecCtrl.fpu.isFpToVecInst || (outCtrl.fuOpType === VfaluType.vfmv_f_s), 291 1.U, 292 Mux( 293 outCtrl.fuOpType === VfaluType.vfmv_s_f, 294 outVl.orR, 295 Mux(outIsResuction, reductionVl, outVl) 296 ) 297 ) 298 val vlMaxAllUop = Wire(outVl.cloneType) 299 vlMaxAllUop := Mux(outVecCtrl.vlmul(2), vlMax >> lmulAbs, vlMax << lmulAbs).asUInt 300 val vlMaxThisUop = Mux(outVecCtrl.vlmul(2), vlMax >> lmulAbs, vlMax).asUInt 301 val vlSetThisUop = Mux(outVlFix > outVuopidx*vlMaxThisUop, outVlFix - outVuopidx*vlMaxThisUop, 0.U) 302 val vlThisUop = Wire(UInt(3.W)) 303 vlThisUop := Mux(vlSetThisUop < vlMaxThisUop, vlSetThisUop, vlMaxThisUop) 304 val vlMaskRShift = Wire(UInt((4 * numVecModule).W)) 305 vlMaskRShift := Fill(4 * numVecModule, 1.U(1.W)) >> ((4 * numVecModule).U - vlThisUop) 306 307 private val needNoMask = outCtrl.fuOpType === VfaluType.vfmerge || 308 outCtrl.fuOpType === VfaluType.vfmv_s_f || 309 outIsResuction || 310 outVecCtrl.fpu.isFpToVecInst 311 val maskToMgu = Mux(needNoMask, allMaskTrue, outSrcMask) 312 val allFFlagsEn = Wire(Vec(4*numVecModule,Bool())) 313 val outSrcMaskRShift = Wire(UInt((4*numVecModule).W)) 314 outSrcMaskRShift := (maskToMgu >> (outVecCtrl.vuopIdx(2,0) * vlMax))(4*numVecModule-1,0) 315 val f16FFlagsEn = outSrcMaskRShift 316 val f32FFlagsEn = Wire(Vec(numVecModule,UInt(4.W))) 317 for (i <- 0 until numVecModule){ 318 f32FFlagsEn(i) := Cat(Fill(2, 0.U),outSrcMaskRShift(2*i+1,2*i)) 319 } 320 val f64FFlagsEn = Wire(Vec(numVecModule, UInt(4.W))) 321 for (i <- 0 until numVecModule) { 322 f64FFlagsEn(i) := Cat(Fill(3, 0.U), outSrcMaskRShift(i)) 323 } 324 val fflagsEn= Mux1H( 325 Seq( 326 (outEew === 1.U) -> f16FFlagsEn.asUInt, 327 (outEew === 2.U) -> f32FFlagsEn.asUInt, 328 (outEew === 3.U) -> f64FFlagsEn.asUInt 329 ) 330 ) 331 allFFlagsEn := Mux(outIsResuction, Fill(4*numVecModule, 1.U), (fflagsEn & vlMaskRShift)).asTypeOf(allFFlagsEn) 332 333 val allFFlags = fflagsData.asTypeOf(Vec(4*numVecModule,UInt(5.W))) 334 val outFFlags = allFFlagsEn.zip(allFFlags).map{ 335 case(en,fflags) => Mux(en, fflags, 0.U(5.W)) 336 }.reduce(_ | _) 337 io.out.bits.res.fflags.get := outFFlags 338 339 340 val cmpResultOldVd = Wire(UInt(cmpResultWidth.W)) 341 val cmpResultOldVdRshiftWidth = Wire(UInt(6.W)) 342 cmpResultOldVdRshiftWidth := Mux1H( 343 Seq( 344 (outVecCtrl.vsew === VSew.e16) -> (outVecCtrl.vuopIdx(2, 0) << 3), 345 (outVecCtrl.vsew === VSew.e32) -> (outVecCtrl.vuopIdx(2, 0) << 2), 346 (outVecCtrl.vsew === VSew.e64) -> (outVecCtrl.vuopIdx(2, 0) << 1), 347 ) 348 ) 349 cmpResultOldVd := (outOldVd >> cmpResultOldVdRshiftWidth)(4*numVecModule-1,0) 350 val cmpResultForMgu = Wire(Vec(cmpResultWidth, Bool())) 351 private val maxVdIdx = 8 352 private val elementsInOneUop = Mux1H( 353 Seq( 354 (outEew === 1.U) -> (cmpResultWidth).U(4.W), 355 (outEew === 2.U) -> (cmpResultWidth / 2).U(4.W), 356 (outEew === 3.U) -> (cmpResultWidth / 4).U(4.W), 357 ) 358 ) 359 private val vdIdx = outVecCtrl.vuopIdx(2, 0) 360 private val elementsComputed = Mux1H(Seq.tabulate(maxVdIdx)(i => (vdIdx === i.U) -> (elementsInOneUop * i.U))) 361 for (i <- 0 until cmpResultWidth) { 362 val cmpResultWithVmask = Mux(outSrcMaskRShift(i), cmpResult(i), Mux(outVecCtrl.vma, true.B, cmpResultOldVd(i))) 363 cmpResultForMgu(i) := Mux(elementsComputed +& i.U >= outVl, true.B, cmpResultWithVmask) 364 } 365 val outIsFold = outVecCtrl.fpu.isFoldTo1_2 || outVecCtrl.fpu.isFoldTo1_4 || outVecCtrl.fpu.isFoldTo1_8 366 val outOldVdForREDO = Mux1H(Seq( 367 (outVecCtrl.vsew === VSew.e16) -> (outOldVd >> 16), 368 (outVecCtrl.vsew === VSew.e32) -> (outOldVd >> 32), 369 (outVecCtrl.vsew === VSew.e64) -> (outOldVd >> 64), 370 )) 371 val outOldVdForWREDO = Mux( 372 !outIsFold, 373 Mux(outVecCtrl.vsew === VSew.e16, Cat(outOldVd(VLEN-1-16,16), 0.U(32.W)), Cat(outOldVd(VLEN-1-32,32), 0.U(64.W))), 374 Mux(outVecCtrl.vsew === VSew.e16, 375 // Divide vuopIdx by 8 and the remainder is 1 376 Mux(outVecCtrl.vuopIdx(2,0) === 1.U, outOldVd, outOldVd >> 16), 377 // Divide vuopIdx by 4 and the remainder is 1 378 Mux(outVecCtrl.vuopIdx(1,0) === 1.U, outOldVd, outOldVd >> 32) 379 ), 380 ) 381 val outOldVdForRED = Mux(outCtrl.fuOpType === VfaluType.vfredosum, outOldVdForREDO, outOldVdForWREDO) 382 val numOfUopVFREDOSUM = { 383 val uvlMax = MuxLookup(outVecCtrl.vsew, 0.U)(Array( 384 VSew.e16 -> 8.U, 385 VSew.e32 -> 4.U, 386 VSew.e64 -> 2.U, 387 )) 388 val vlMax = Mux(outVecCtrl.vlmul(2), uvlMax >> (-outVecCtrl.vlmul)(1, 0), uvlMax << outVecCtrl.vlmul(1, 0)).asUInt 389 vlMax 390 } 391 val isOutOldVdForREDO = (outCtrl.fuOpType === VfaluType.vfredosum && outIsFold) || outCtrl.fuOpType === VfaluType.vfwredosum 392 val taIsFalseForVFREDO = ((outCtrl.fuOpType === VfaluType.vfredosum) || (outCtrl.fuOpType === VfaluType.vfwredosum)) && (outVecCtrl.vuopIdx =/= numOfUopVFREDOSUM - 1.U) 393 // outVecCtrl.fpu.isFpToVecInst means the instruction is float instruction, not vector float instruction 394 val notUseVl = outVecCtrl.fpu.isFpToVecInst || (outCtrl.fuOpType === VfaluType.vfmv_f_s) 395 val notModifyVd = !notUseVl && (outVl === 0.U) 396 mgu.io.in.vd := Mux(outVecCtrl.isDstMask, Cat(0.U((dataWidth / 16 * 15).W), cmpResultForMgu.asUInt), resultDataUInt) 397 mgu.io.in.oldVd := Mux(isOutOldVdForREDO, outOldVdForRED, outOldVd) 398 mgu.io.in.mask := maskToMgu 399 mgu.io.in.info.ta := Mux(outCtrl.fuOpType === VfaluType.vfmv_f_s, true.B , Mux(taIsFalseForVFREDO, false.B, outVecCtrl.vta)) 400 mgu.io.in.info.ma := Mux(outCtrl.fuOpType === VfaluType.vfmv_s_f, true.B , outVecCtrl.vma) 401 mgu.io.in.info.vl := outVlFix 402 mgu.io.in.info.vstart := outVecCtrl.vstart 403 mgu.io.in.info.vlmul := outVecCtrl.vlmul 404 mgu.io.in.info.valid := Mux(notModifyVd, false.B, io.in.valid) 405 mgu.io.in.info.vstart := Mux(outVecCtrl.fpu.isFpToVecInst, 0.U, outVecCtrl.vstart) 406 mgu.io.in.info.eew := outEew 407 mgu.io.in.info.vsew := outVecCtrl.vsew 408 mgu.io.in.info.vdIdx := Mux(outIsResuction, 0.U, outVecCtrl.vuopIdx) 409 mgu.io.in.info.narrow := outVecCtrl.isNarrow 410 mgu.io.in.info.dstMask := outVecCtrl.isDstMask 411 mgu.io.in.isIndexedVls := false.B 412 mgtu.io.in.vd := Mux(outVecCtrl.isDstMask, mgu.io.out.vd, resultDataUInt) 413 mgtu.io.in.vl := outVl 414 val resultFpMask = Wire(UInt(VLEN.W)) 415 val isFclass = outVecCtrl.fpu.isFpToVecInst && (outCtrl.fuOpType === VfaluType.vfclass) 416 val fpCmpFuOpType = Seq(VfaluType.vfeq, VfaluType.vflt, VfaluType.vfle) 417 val isCmp = outVecCtrl.fpu.isFpToVecInst && (fpCmpFuOpType.map(_ === outCtrl.fuOpType).reduce(_|_)) 418 resultFpMask := Mux(isFclass || isCmp, Fill(16, 1.U(1.W)), Fill(VLEN, 1.U(1.W))) 419 // when dest is mask, the result need to be masked by mgtu 420 io.out.bits.res.data := Mux(notModifyVd, outOldVd, Mux(outVecCtrl.isDstMask, mgtu.io.out.vd, mgu.io.out.vd) & resultFpMask) 421 io.out.bits.ctrl.exceptionVec.get(ExceptionNO.illegalInstr) := mgu.io.out.illegal 422 423} 424 425class VFMgu(vlen:Int)(implicit p: Parameters) extends Module{ 426 val io = IO(new VFMguIO(vlen)) 427 428 val vd = io.in.vd 429 val oldvd = io.in.oldVd 430 val mask = io.in.mask 431 val vsew = io.in.info.eew 432 val num16bits = vlen / 16 433 434} 435 436class VFMguIO(vlen: Int)(implicit p: Parameters) extends Bundle { 437 val in = new Bundle { 438 val vd = Input(UInt(vlen.W)) 439 val oldVd = Input(UInt(vlen.W)) 440 val mask = Input(UInt(vlen.W)) 441 val info = Input(new VecInfo) 442 } 443 val out = new Bundle { 444 val vd = Output(UInt(vlen.W)) 445 } 446}