1package xiangshan.backend.fu.wrapper 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import utils.XSError 7import xiangshan.backend.fu.FuConfig 8import xiangshan.backend.fu.vector.Bundles.{VLmul, VSew, ma} 9import xiangshan.backend.fu.vector.utils.VecDataSplitModule 10import xiangshan.backend.fu.vector.{Mgu, VecInfo, VecPipedFuncUnit} 11import yunsuan.{VfaluType, VfpuType} 12import yunsuan.vector.VectorFloatAdder 13 14class VFAlu(cfg: FuConfig)(implicit p: Parameters) extends VecPipedFuncUnit(cfg) { 15 XSError(io.in.valid && io.in.bits.ctrl.fuOpType === VfpuType.dummy, "Vfalu OpType not supported") 16 17 // params alias 18 private val dataWidth = cfg.dataBits 19 private val dataWidthOfDataModule = 64 20 private val numVecModule = dataWidth / dataWidthOfDataModule 21 22 // io alias 23 private val opcode = fuOpType(4,0) 24 private val resWiden = fuOpType(5) 25 private val opbWiden = fuOpType(6) 26 27 // modules 28 private val vfalus = Seq.fill(numVecModule)(Module(new VectorFloatAdder)) 29 private val vs2Split = Module(new VecDataSplitModule(dataWidth, dataWidthOfDataModule)) 30 private val vs1Split = Module(new VecDataSplitModule(dataWidth, dataWidthOfDataModule)) 31 private val oldVdSplit = Module(new VecDataSplitModule(dataWidth, dataWidthOfDataModule)) 32 private val mgu = Module(new Mgu(dataWidth)) 33 34 /** 35 * In connection of [[vs2Split]], [[vs1Split]] and [[oldVdSplit]] 36 */ 37 vs2Split.io.inVecData := vs2 38 vs1Split.io.inVecData := vs1 39 oldVdSplit.io.inVecData := oldVd 40 41 /** 42 * [[vfalus]]'s in connection 43 */ 44 // Vec(vs2(31,0), vs2(63,32), vs2(95,64), vs2(127,96)) ==> 45 // Vec( 46 // Cat(vs2(95,64), vs2(31,0)), 47 // Cat(vs2(127,96), vs2(63,32)), 48 // ) 49 private val vs2GroupedVec: Vec[UInt] = VecInit(vs2Split.io.outVec32b.zipWithIndex.groupBy(_._2 % 2).map(x => x._1 -> x._2.map(_._1)).values.map(x => Cat(x.reverse)).toSeq) 50 private val vs1GroupedVec: Vec[UInt] = VecInit(vs1Split.io.outVec32b.zipWithIndex.groupBy(_._2 % 2).map(x => x._1 -> x._2.map(_._1)).values.map(x => Cat(x.reverse)).toSeq) 51 private val resultData = Wire(Vec(numVecModule,UInt(dataWidthOfDataModule.W))) 52 private val fflagsData = Wire(Vec(numVecModule,UInt(20.W))) 53 private val srcMaskRShiftForReduction = Wire(UInt((8 * numVecModule).W)) 54 // for reduction 55 val isFirstGroupUop = vuopIdx === 0.U || 56 (vuopIdx === 1.U && (vlmul === VLmul.m4 || vlmul === VLmul.m8)) || 57 ((vuopIdx === 2.U || vuopIdx === 3.U) && vlmul === VLmul.m8) 58 val maskRshiftWidthForReduction = Wire(UInt(6.W)) 59 maskRshiftWidthForReduction := Mux(fuOpType === VfaluType.vfredosum, 60 vuopIdx, 61 Mux1H(Seq( 62 (vsew === VSew.e16) -> (vuopIdx(1, 0) << 4), 63 (vsew === VSew.e32) -> (vuopIdx(1, 0) << 3), 64 (vsew === VSew.e64) -> (vuopIdx(1, 0) << 2), 65 )) 66 ) 67 val vlMaskForReduction = (~(Fill(VLEN, 1.U) << vl)).asUInt 68 srcMaskRShiftForReduction := ((srcMask & vlMaskForReduction) >> maskRshiftWidthForReduction)(8 * numVecModule - 1, 0) 69 70 def genMaskForReduction(inmask: UInt, sew: UInt, i: Int): UInt = { 71 val f64MaskNum = dataWidth / 64 * 2 72 val f32MaskNum = dataWidth / 32 * 2 73 val f16MaskNum = dataWidth / 16 * 2 74 val f64Mask = inmask(f64MaskNum - 1, 0) 75 val f32Mask = inmask(f32MaskNum - 1, 0) 76 val f16Mask = inmask(f16MaskNum - 1, 0) 77 // vs2 reordered, so mask use high bits 78 val f64FirstFoldMask = Mux1H( 79 Seq( 80 vecCtrl.fpu.isFoldTo1_2 -> Cat(0.U(3.W), f64Mask(0), 0.U(3.W), f64Mask(1)), 81 ) 82 ) 83 val f32FirstFoldMask = Mux1H( 84 Seq( 85 vecCtrl.fpu.isFoldTo1_2 -> Cat(0.U(2.W), f32Mask(1), f32Mask(0), 0.U(2.W), f32Mask(3), f32Mask(2)), 86 vecCtrl.fpu.isFoldTo1_4 -> Cat(0.U(3.W), f32Mask(0), 0.U(3.W), f32Mask(1)), 87 ) 88 ) 89 val f16FirstFoldMask = Mux1H( 90 Seq( 91 vecCtrl.fpu.isFoldTo1_2 -> Cat(f16Mask(7,4), f16Mask(3,0)), 92 vecCtrl.fpu.isFoldTo1_4 -> Cat(0.U(2.W), f16Mask(1), f16Mask(0), 0.U(2.W), f16Mask(3), f16Mask(2)), 93 vecCtrl.fpu.isFoldTo1_8 -> Cat(0.U(3.W), f16Mask(0), 0.U(3.W), f16Mask(1)), 94 ) 95 ) 96 val f64FoldMask = Mux1H( 97 Seq( 98 vecCtrl.fpu.isFoldTo1_2 -> "b00010001".U, 99 ) 100 ) 101 val f32FoldMask = Mux1H( 102 Seq( 103 vecCtrl.fpu.isFoldTo1_2 -> "b00110011".U, 104 vecCtrl.fpu.isFoldTo1_4 -> "b00010001".U, 105 ) 106 ) 107 val f16FoldMask = Mux1H( 108 Seq( 109 vecCtrl.fpu.isFoldTo1_2 -> "b11111111".U, 110 vecCtrl.fpu.isFoldTo1_4 -> "b00110011".U, 111 vecCtrl.fpu.isFoldTo1_8 -> "b00010001".U, 112 ) 113 ) 114 // low 4 bits for vs2(fp_a), high 4 bits for vs1(fp_b), 115 val isFold = vecCtrl.fpu.isFoldTo1_2 || vecCtrl.fpu.isFoldTo1_4 || vecCtrl.fpu.isFoldTo1_8 116 val f64FirstNotFoldMask = Cat(0.U(3.W), f64Mask(i+2), 0.U(3.W), f64Mask(i)) 117 val f32FirstNotFoldMask = Cat(0.U(2.W), f32Mask(i + 5, i+4), 0.U(2.W), Cat(f32Mask(i + 1, i))) 118 val f16FirstNotFoldMask = Cat(f16Mask(i+11,i+8), f16Mask(i+3,0)) 119 val f64MaskI = Mux(isFirstGroupUop, Mux(isFold, f64FirstFoldMask, f64FirstNotFoldMask), Mux(isFold, f64FoldMask, Fill(8,1.U))) 120 val f32MaskI = Mux(isFirstGroupUop, Mux(isFold, f32FirstFoldMask, f32FirstNotFoldMask), Mux(isFold, f32FoldMask, Fill(8,1.U))) 121 val f16MaskI = Mux(isFirstGroupUop, Mux(isFold, f16FirstFoldMask, f16FirstNotFoldMask), Mux(isFold, f16FoldMask, Fill(8,1.U))) 122 val outMask = Mux1H( 123 Seq( 124 (sew === 3.U) -> f64MaskI, 125 (sew === 2.U) -> f32MaskI, 126 (sew === 1.U) -> f16MaskI, 127 ) 128 ) 129 Mux(fuOpType === VfaluType.vfredosum || fuOpType === VfaluType.vfwredosum, outMask(0),outMask) 130 } 131 def genMaskForMerge(inmask:UInt, sew:UInt, i:Int): UInt = { 132 val f64MaskNum = dataWidth / 64 133 val f32MaskNum = dataWidth / 32 134 val f16MaskNum = dataWidth / 16 135 val f64Mask = inmask(f64MaskNum-1,0) 136 val f32Mask = inmask(f32MaskNum-1,0) 137 val f16Mask = inmask(f16MaskNum-1,0) 138 val f64MaskI = Cat(0.U(3.W),f64Mask(i)) 139 val f32MaskI = Cat(0.U(2.W),f32Mask(2*i+1,2*i)) 140 val f16MaskI = f16Mask(4*i+3,4*i) 141 val outMask = Mux1H( 142 Seq( 143 (sew === 3.U) -> f64MaskI, 144 (sew === 2.U) -> f32MaskI, 145 (sew === 1.U) -> f16MaskI, 146 ) 147 ) 148 outMask 149 } 150 val isScalarMove = (fuOpType === VfaluType.vfmv_f_s) || (fuOpType === VfaluType.vfmv_s_f) 151 val srcMaskRShift = Wire(UInt((4 * numVecModule).W)) 152 val maskRshiftWidth = Wire(UInt(6.W)) 153 maskRshiftWidth := Mux1H( 154 Seq( 155 (vsew === VSew.e16) -> (vuopIdx(2,0) << 3), 156 (vsew === VSew.e32) -> (vuopIdx(2,0) << 2), 157 (vsew === VSew.e64) -> (vuopIdx(2,0) << 1), 158 ) 159 ) 160 srcMaskRShift := (srcMask >> maskRshiftWidth)(4 * numVecModule - 1, 0) 161 val fp_aIsFpCanonicalNAN = Wire(Vec(numVecModule,Bool())) 162 val fp_bIsFpCanonicalNAN = Wire(Vec(numVecModule,Bool())) 163 vfalus.zipWithIndex.foreach { 164 case (mod, i) => 165 mod.io.fp_a := Mux(opbWiden, vs1Split.io.outVec64b(i), vs2Split.io.outVec64b(i)) // very dirty TODO 166 mod.io.fp_b := Mux(opbWiden, vs2Split.io.outVec64b(i), vs1Split.io.outVec64b(i)) // very dirty TODO 167 mod.io.widen_a := Cat(vs2Split.io.outVec32b(i+numVecModule), vs2Split.io.outVec32b(i)) 168 mod.io.widen_b := Cat(vs1Split.io.outVec32b(i+numVecModule), vs1Split.io.outVec32b(i)) 169 mod.io.frs1 := 0.U // already vf -> vv 170 mod.io.is_frs1 := false.B // already vf -> vv 171 mod.io.mask := Mux(isScalarMove, !vuopIdx.orR, genMaskForMerge(inmask = srcMaskRShift, sew = vsew, i = i)) 172 mod.io.maskForReduction := genMaskForReduction(inmask = srcMaskRShiftForReduction, sew = vsew, i = i) 173 mod.io.uop_idx := Mux(fuOpType === VfaluType.vfwredosum, 0.U, vuopIdx(0)) 174 mod.io.is_vec := true.B // Todo 175 mod.io.round_mode := frm 176 mod.io.fp_format := Mux(resWiden, vsew + 1.U, vsew) 177 mod.io.opb_widening := opbWiden || (fuOpType === VfaluType.vfwredosum) 178 mod.io.res_widening := resWiden 179 mod.io.op_code := opcode 180 resultData(i) := mod.io.fp_result 181 fflagsData(i) := mod.io.fflags 182 fp_aIsFpCanonicalNAN(i) := vecCtrl.fpu.isFpToVecInst & ( 183 ((vsew === VSew.e32) & (!vs2Split.io.outVec64b(i).head(32).andR)) | 184 ((vsew === VSew.e16) & (!vs2Split.io.outVec64b(i).head(48).andR)) 185 ) 186 fp_bIsFpCanonicalNAN(i) := vecCtrl.fpu.isFpToVecInst & ( 187 ((vsew === VSew.e32) & (!vs1Split.io.outVec64b(i).head(32).andR)) | 188 ((vsew === VSew.e16) & (!vs1Split.io.outVec64b(i).head(48).andR)) 189 ) 190 mod.io.fp_aIsFpCanonicalNAN := fp_aIsFpCanonicalNAN(i) 191 mod.io.fp_bIsFpCanonicalNAN := fp_bIsFpCanonicalNAN(i) 192 } 193 val resultDataUInt = resultData.asUInt 194 val cmpResultWidth = dataWidth / 16 195 val cmpResult = Wire(Vec(cmpResultWidth, Bool())) 196 for (i <- 0 until cmpResultWidth) { 197 if(i == 0) { 198 cmpResult(i) := resultDataUInt(0) 199 } 200 else if(i < dataWidth / 64) { 201 cmpResult(i) := Mux1H( 202 Seq( 203 (outVecCtrl.vsew === 1.U) -> resultDataUInt(i*16), 204 (outVecCtrl.vsew === 2.U) -> resultDataUInt(i*32), 205 (outVecCtrl.vsew === 3.U) -> resultDataUInt(i*64) 206 ) 207 ) 208 } 209 else if(i < dataWidth / 32) { 210 cmpResult(i) := Mux1H( 211 Seq( 212 (outVecCtrl.vsew === 1.U) -> resultDataUInt(i * 16), 213 (outVecCtrl.vsew === 2.U) -> resultDataUInt(i * 32), 214 (outVecCtrl.vsew === 3.U) -> false.B 215 ) 216 ) 217 } 218 else if(i < dataWidth / 16) { 219 cmpResult(i) := Mux(outVecCtrl.vsew === 1.U, resultDataUInt(i*16), false.B) 220 } 221 } 222 223 val outEew = Mux(RegNext(resWiden), outVecCtrl.vsew + 1.U, outVecCtrl.vsew) 224 val outVuopidx = outVecCtrl.vuopIdx(2, 0) 225 val vlMax = ((VLEN/8).U >> outEew).asUInt 226 val lmulAbs = Mux(outVecCtrl.vlmul(2), (~outVecCtrl.vlmul(1,0)).asUInt + 1.U, outVecCtrl.vlmul(1,0)) 227 // vfmv_f_s need vl=1, reduction last uop need vl=1, other uop need vl=vlmax 228 val numOfUopVFRED = { 229 // addTime include add frs1 230 val addTime = MuxLookup(outVecCtrl.vlmul, 1.U(4.W), Array( 231 VLmul.m2 -> 2.U, 232 VLmul.m4 -> 4.U, 233 VLmul.m8 -> 8.U, 234 )) 235 val foldLastVlmul = MuxLookup(outVecCtrl.vsew, "b000".U, Array( 236 VSew.e16 -> VLmul.mf8, 237 VSew.e32 -> VLmul.mf4, 238 VSew.e64 -> VLmul.mf2, 239 )) 240 // lmul < 1, foldTime = vlmul - foldFastVlmul 241 // lmul >= 1, foldTime = 0.U - foldFastVlmul 242 val foldTime = Mux(outVecCtrl.vlmul(2), outVecCtrl.vlmul, 0.U) - foldLastVlmul 243 addTime + foldTime 244 } 245 val reductionVl = Mux((outVecCtrl.vuopIdx === numOfUopVFRED - 1.U) || (outCtrl.fuOpType === VfaluType.vfredosum || outCtrl.fuOpType === VfaluType.vfwredosum), 1.U, vlMax) 246 val outIsResuction = outCtrl.fuOpType === VfaluType.vfredusum || 247 outCtrl.fuOpType === VfaluType.vfredmax || 248 outCtrl.fuOpType === VfaluType.vfredmin || 249 outCtrl.fuOpType === VfaluType.vfredosum || 250 outCtrl.fuOpType === VfaluType.vfwredosum 251 val outVlFix = Mux( 252 outVecCtrl.fpu.isFpToVecInst || (outCtrl.fuOpType === VfaluType.vfmv_f_s), 253 1.U, 254 Mux( 255 outCtrl.fuOpType === VfaluType.vfmv_s_f, 256 outVl.orR, 257 Mux(outIsResuction, reductionVl, outVl) 258 ) 259 ) 260 val vlMaxAllUop = Wire(outVl.cloneType) 261 vlMaxAllUop := Mux(outVecCtrl.vlmul(2), vlMax >> lmulAbs, vlMax << lmulAbs).asUInt 262 val vlMaxThisUop = Mux(outVecCtrl.vlmul(2), vlMax >> lmulAbs, vlMax).asUInt 263 val vlSetThisUop = Mux(outVlFix > outVuopidx*vlMaxThisUop, outVlFix - outVuopidx*vlMaxThisUop, 0.U) 264 val vlThisUop = Wire(UInt(3.W)) 265 vlThisUop := Mux(vlSetThisUop < vlMaxThisUop, vlSetThisUop, vlMaxThisUop) 266 val vlMaskRShift = Wire(UInt((4 * numVecModule).W)) 267 vlMaskRShift := Fill(4 * numVecModule, 1.U(1.W)) >> ((4 * numVecModule).U - vlThisUop) 268 269 private val needNoMask = outCtrl.fuOpType === VfaluType.vfmerge || 270 outCtrl.fuOpType === VfaluType.vfmv_s_f || 271 outIsResuction || 272 outVecCtrl.fpu.isFpToVecInst 273 val maskToMgu = Mux(needNoMask, allMaskTrue, outSrcMask) 274 val allFFlagsEn = Wire(Vec(4*numVecModule,Bool())) 275 val outSrcMaskRShift = Wire(UInt((4*numVecModule).W)) 276 outSrcMaskRShift := (maskToMgu >> (outVecCtrl.vuopIdx(2,0) * vlMax))(4*numVecModule-1,0) 277 val f16FFlagsEn = outSrcMaskRShift 278 val f32FFlagsEn = Wire(Vec(numVecModule,UInt(4.W))) 279 for (i <- 0 until numVecModule){ 280 f32FFlagsEn(i) := Cat(Fill(2, 0.U),outSrcMaskRShift(2*i+1,2*i)) 281 } 282 val f64FFlagsEn = Wire(Vec(numVecModule, UInt(4.W))) 283 for (i <- 0 until numVecModule) { 284 f64FFlagsEn(i) := Cat(Fill(3, 0.U), outSrcMaskRShift(i)) 285 } 286 val fflagsEn= Mux1H( 287 Seq( 288 (outEew === 1.U) -> f16FFlagsEn.asUInt, 289 (outEew === 2.U) -> f32FFlagsEn.asUInt, 290 (outEew === 3.U) -> f64FFlagsEn.asUInt 291 ) 292 ) 293 allFFlagsEn := Mux(outIsResuction, Fill(4*numVecModule, 1.U), (fflagsEn & vlMaskRShift)).asTypeOf(allFFlagsEn) 294 295 val allFFlags = fflagsData.asTypeOf(Vec(4*numVecModule,UInt(5.W))) 296 val outFFlags = allFFlagsEn.zip(allFFlags).map{ 297 case(en,fflags) => Mux(en, fflags, 0.U(5.W)) 298 }.reduce(_ | _) 299 io.out.bits.res.fflags.get := outFFlags 300 301 302 val cmpResultOldVd = Wire(UInt(cmpResultWidth.W)) 303 val cmpResultOldVdRshiftWidth = Wire(UInt(6.W)) 304 cmpResultOldVdRshiftWidth := Mux1H( 305 Seq( 306 (outVecCtrl.vsew === VSew.e16) -> (outVecCtrl.vuopIdx(2, 0) << 3), 307 (outVecCtrl.vsew === VSew.e32) -> (outVecCtrl.vuopIdx(2, 0) << 2), 308 (outVecCtrl.vsew === VSew.e64) -> (outVecCtrl.vuopIdx(2, 0) << 1), 309 ) 310 ) 311 cmpResultOldVd := (outOldVd >> cmpResultOldVdRshiftWidth)(4*numVecModule-1,0) 312 val cmpResultForMgu = Wire(Vec(cmpResultWidth, Bool())) 313 for (i <- 0 until cmpResultWidth) { 314 cmpResultForMgu(i) := Mux(outSrcMaskRShift(i), cmpResult(i), Mux(outVecCtrl.vma, true.B, cmpResultOldVd(i))) 315 } 316 val outIsFold = outVecCtrl.fpu.isFoldTo1_2 || outVecCtrl.fpu.isFoldTo1_4 || outVecCtrl.fpu.isFoldTo1_8 317 val outOldVdForREDO = Mux1H(Seq( 318 (outVecCtrl.vsew === VSew.e16) -> (outOldVd >> 16), 319 (outVecCtrl.vsew === VSew.e32) -> (outOldVd >> 32), 320 (outVecCtrl.vsew === VSew.e64) -> (outOldVd >> 64), 321 )) 322 val outOldVdForWREDO = Mux( 323 !outIsFold, 324 Mux(outVecCtrl.vsew === VSew.e16, Cat(outOldVd(VLEN-1-16,16), 0.U(32.W)), Cat(outOldVd(VLEN-1-32,32), 0.U(64.W))), 325 Mux(outVecCtrl.vsew === VSew.e16, 326 // Divide vuopIdx by 8 and the remainder is 1 327 Mux(outVecCtrl.vuopIdx(2,0) === 1.U, outOldVd, outOldVd >> 16), 328 // Divide vuopIdx by 4 and the remainder is 1 329 Mux(outVecCtrl.vuopIdx(1,0) === 1.U, outOldVd, outOldVd >> 32) 330 ), 331 ) 332 val outOldVdForRED = Mux(outCtrl.fuOpType === VfaluType.vfredosum, outOldVdForREDO, outOldVdForWREDO) 333 val numOfUopVFREDOSUM = { 334 val uvlMax = MuxLookup(outVecCtrl.vsew, 0.U, Array( 335 VSew.e16 -> 8.U, 336 VSew.e32 -> 4.U, 337 VSew.e64 -> 2.U, 338 )) 339 val vlMax = Mux(outVecCtrl.vlmul(2), uvlMax >> (-outVecCtrl.vlmul)(1, 0), uvlMax << outVecCtrl.vlmul(1, 0)).asUInt 340 vlMax 341 } 342 val isOutOldVdForREDO = (outCtrl.fuOpType === VfaluType.vfredosum && outIsFold) || outCtrl.fuOpType === VfaluType.vfwredosum 343 val taIsFalseForVFREDO = ((outCtrl.fuOpType === VfaluType.vfredosum) || (outCtrl.fuOpType === VfaluType.vfwredosum)) && (outVecCtrl.vuopIdx =/= numOfUopVFREDOSUM - 1.U) 344 mgu.io.in.vd := Mux(outVecCtrl.isDstMask, Cat(0.U((dataWidth / 16 * 15).W), cmpResultForMgu.asUInt), resultDataUInt) 345 mgu.io.in.oldVd := Mux(isOutOldVdForREDO, outOldVdForRED, outOldVd) 346 mgu.io.in.mask := maskToMgu 347 mgu.io.in.info.ta := Mux(outCtrl.fuOpType === VfaluType.vfmv_f_s, true.B , Mux(taIsFalseForVFREDO, false.B, outVecCtrl.vta)) 348 mgu.io.in.info.ma := Mux(outCtrl.fuOpType === VfaluType.vfmv_s_f, true.B , outVecCtrl.vma) 349 mgu.io.in.info.vl := outVlFix 350 mgu.io.in.info.vstart := outVecCtrl.vstart 351 mgu.io.in.info.vlmul := outVecCtrl.vlmul 352 mgu.io.in.info.valid := io.out.valid 353 mgu.io.in.info.vstart := Mux(outVecCtrl.fpu.isFpToVecInst, 0.U, outVecCtrl.vstart) 354 mgu.io.in.info.eew := outEew 355 mgu.io.in.info.vsew := outVecCtrl.vsew 356 mgu.io.in.info.vdIdx := Mux(outIsResuction, 0.U, outVecCtrl.vuopIdx) 357 mgu.io.in.info.narrow := outVecCtrl.isNarrow 358 mgu.io.in.info.dstMask := outVecCtrl.isDstMask 359 val resultFpMask = Wire(UInt(VLEN.W)) 360 val isFclass = outVecCtrl.fpu.isFpToVecInst && (outCtrl.fuOpType === VfaluType.vfclass) 361 val fpCmpFuOpType = Seq(VfaluType.vfeq, VfaluType.vflt, VfaluType.vfle) 362 val isCmp = outVecCtrl.fpu.isFpToVecInst && (fpCmpFuOpType.map(_ === outCtrl.fuOpType).reduce(_|_)) 363 resultFpMask := Mux(isFclass || isCmp, Fill(16, 1.U(1.W)), Fill(VLEN, 1.U(1.W))) 364 io.out.bits.res.data := mgu.io.out.vd & resultFpMask 365 366} 367 368class VFMgu(vlen:Int)(implicit p: Parameters) extends Module{ 369 val io = IO(new VFMguIO(vlen)) 370 371 val vd = io.in.vd 372 val oldvd = io.in.oldVd 373 val mask = io.in.mask 374 val vsew = io.in.info.eew 375 val num16bits = vlen / 16 376 377} 378 379class VFMguIO(vlen: Int)(implicit p: Parameters) extends Bundle { 380 val in = new Bundle { 381 val vd = Input(UInt(vlen.W)) 382 val oldVd = Input(UInt(vlen.W)) 383 val mask = Input(UInt(vlen.W)) 384 val info = Input(new VecInfo) 385 } 386 val out = new Bundle { 387 val vd = Output(UInt(vlen.W)) 388 } 389}