xref: /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFALU.scala (revision 684d7acea36dd90fd3ad8adc34ab058dde969b46) 
1package xiangshan.backend.fu.wrapper
2
3import chipsalliance.rocketchip.config.Parameters
4import chisel3._
5import chisel3.util._
6import utils.XSError
7import xiangshan.backend.fu.FuConfig
8import xiangshan.backend.fu.vector.Bundles.VSew
9import xiangshan.backend.fu.vector.utils.VecDataSplitModule
10import xiangshan.backend.fu.vector.{Mgu, Utils, VecInfo, VecPipedFuncUnit, VecSrcTypeModule}
11import yunsuan.{VfaluType, VfpuType}
12import xiangshan.backend.fu.vector.Bundles.{VSew, Vl}
13import yunsuan.vector.VectorFloatAdder
14
15class VFAlu(cfg: FuConfig)(implicit p: Parameters) extends VecPipedFuncUnit(cfg) {
16  XSError(io.in.valid && io.in.bits.ctrl.fuOpType === VfpuType.dummy, "Vfalu OpType not supported")
17
18  // params alias
19  private val dataWidth = cfg.dataBits
20  private val dataWidthOfDataModule = 64
21  private val numVecModule = dataWidth / dataWidthOfDataModule
22
23  // io alias
24  private val opcode  = fuOpType(4,0)
25  private val resWiden  = fuOpType(5)
26  private val opbWiden  = fuOpType(6)
27
28  // modules
29  private val vfalus = Seq.fill(numVecModule)(Module(new VectorFloatAdder))
30  private val vs2Split = Module(new VecDataSplitModule(dataWidth, dataWidthOfDataModule))
31  private val vs1Split = Module(new VecDataSplitModule(dataWidth, dataWidthOfDataModule))
32  private val oldVdSplit  = Module(new VecDataSplitModule(dataWidth, dataWidthOfDataModule))
33  private val mgu = Module(new Mgu(dataWidth))
34
35  /**
36    * In connection of [[vs2Split]], [[vs1Split]] and [[oldVdSplit]]
37    */
38  vs2Split.io.inVecData := vs2
39  vs1Split.io.inVecData := vs1
40  oldVdSplit.io.inVecData := oldVd
41
42  /**
43    * [[vfalus]]'s in connection
44    */
45  // Vec(vs2(31,0), vs2(63,32), vs2(95,64), vs2(127,96)) ==>
46  // Vec(
47  //   Cat(vs2(95,64),  vs2(31,0)),
48  //   Cat(vs2(127,96), vs2(63,32)),
49  // )
50  private val vs2GroupedVec: Vec[UInt] = VecInit(vs2Split.io.outVec32b.zipWithIndex.groupBy(_._2 % 2).map(x => x._1 -> x._2.map(_._1)).values.map(x => Cat(x.reverse)).toSeq)
51  private val vs1GroupedVec: Vec[UInt] = VecInit(vs1Split.io.outVec32b.zipWithIndex.groupBy(_._2 % 2).map(x => x._1 -> x._2.map(_._1)).values.map(x => Cat(x.reverse)).toSeq)
52  private val resultData = Wire(Vec(numVecModule,UInt(dataWidthOfDataModule.W)))
53  private val fflagsData = Wire(Vec(numVecModule,UInt(20.W)))
54
55  vfalus.zipWithIndex.foreach {
56    case (mod, i) =>
57      mod.io.fp_a         := vs2Split.io.outVec64b(i)
58      mod.io.fp_b         := vs1Split.io.outVec64b(i)
59      mod.io.widen_a      := Cat(vs2Split.io.outVec32b(i+numVecModule), vs2Split.io.outVec32b(i))
60      mod.io.widen_b      := Cat(vs1Split.io.outVec32b(i+numVecModule), vs1Split.io.outVec32b(i))
61      mod.io.frs1         := 0.U     // already vf -> vv
62      mod.io.is_frs1      := false.B // already vf -> vv
63      mod.io.mask         := 0.U // Todo
64      mod.io.uop_idx      := vuopIdx(0)
65      mod.io.is_vec       := true.B // Todo
66      mod.io.round_mode   := frm
67      mod.io.fp_format    := vsew
68      mod.io.opb_widening := opbWiden
69      mod.io.res_widening := resWiden
70      mod.io.op_code      := opcode
71      resultData(i)       := mod.io.fp_result
72      fflagsData(i)       := mod.io.fflags
73  }
74
75  val allFFlagsEn = Wire(Vec(4*numVecModule,Bool()))
76  val srcMaskRShift = Wire(UInt((4*numVecModule).W))
77  srcMaskRShift := (outSrcMask >> (vuopIdx * (16.U >> vsew)))(4*numVecModule-1,0)
78  val f16FFlagsEn = srcMaskRShift
79  val f32FFlagsEn = Wire(Vec(numVecModule,UInt(4.W)))
80  for (i <- 0 until numVecModule){
81    f32FFlagsEn(i) := Cat(Fill(2, 1.U),srcMaskRShift(2*i+1,2*i))
82  }
83  val f64FFlagsEn = Wire(Vec(numVecModule, UInt(4.W)))
84  for (i <- 0 until numVecModule) {
85    f64FFlagsEn(i) := Cat(Fill(3, 1.U), srcMaskRShift(i))
86  }
87  val fflagsEn= Mux1H(
88    Seq(
89      (vsew === 1.U) -> f16FFlagsEn.asUInt,
90      (vsew === 2.U) -> f32FFlagsEn.asUInt,
91      (vsew === 3.U) -> f64FFlagsEn.asUInt
92    )
93  )
94  allFFlagsEn := Mux(outVecCtrl.isDstMask, 0.U((4*numVecModule).W), fflagsEn).asTypeOf(allFFlagsEn)
95
96  val allFFlags = fflagsData.asTypeOf(Vec(4*numVecModule,UInt(5.W)))
97  val outFFlags = allFFlagsEn.zip(allFFlags).map{
98    case(en,fflags) => Mux(en, fflags, 0.U(5.W))
99  }.reduce(_ | _)
100  io.out.bits.res.fflags.get := outFFlags
101
102//  private val needNoMask = VfaluType.needNoMask(outCtrl.fuOpType)
103
104//  private val outEew = Mux(outWiden, outVecCtrl.vsew + 1.U, outVecCtrl.vsew)
105  mgu.io.in.vd := resultData.asUInt
106  mgu.io.in.oldVd := outOldVd
107  mgu.io.in.mask := outSrcMask
108  mgu.io.in.info.ta := outVecCtrl.vta
109  mgu.io.in.info.ma := outVecCtrl.vma
110  mgu.io.in.info.vl := outVl
111  mgu.io.in.info.vstart := outVecCtrl.vstart
112  mgu.io.in.info.eew := outVecCtrl.vsew
113  mgu.io.in.info.vdIdx := outVecCtrl.vuopIdx
114  mgu.io.in.info.narrow := outVecCtrl.isNarrow
115  mgu.io.in.info.dstMask := outVecCtrl.isDstMask
116  io.out.bits.res.data := mgu.io.out.vd
117
118//  io.out.bits.res.data := resultData.asUInt
119}
120
121class VFMgu(vlen:Int)(implicit p: Parameters) extends Module{
122  val io = IO(new VFMguIO(vlen))
123
124  val vd = io.in.vd
125  val oldvd = io.in.oldVd
126  val mask = io.in.mask
127  val vsew = io.in.info.eew
128  val num16bits = vlen / 16
129
130}
131
132class VFMguIO(vlen: Int)(implicit p: Parameters) extends Bundle {
133  val in = new Bundle {
134    val vd = Input(UInt(vlen.W))
135    val oldVd = Input(UInt(vlen.W))
136    val mask = Input(UInt(vlen.W))
137    val info = Input(new VecInfo)
138  }
139  val out = new Bundle {
140    val vd = Output(UInt(vlen.W))
141  }
142}