1package xiangshan.backend.fu.wrapper 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import utils.XSError 7import xiangshan.backend.fu.FuConfig 8import xiangshan.backend.fu.vector.Bundles.VSew 9import xiangshan.backend.fu.fpu.FpNonPipedFuncUnit 10import xiangshan.backend.rob.RobPtr 11import yunsuan.VfpuType 12import yunsuan.vector.VectorFloatDivider 13 14class FDivSqrt(cfg: FuConfig)(implicit p: Parameters) extends FpNonPipedFuncUnit(cfg) { 15 XSError(io.in.valid && io.in.bits.ctrl.fuOpType === VfpuType.dummy, "fdiv OpType not supported") 16 17 // io alias 18 private val opcode = fuOpType(0) 19 private val src0 = inData.src(0) 20 private val src1 = inData.src(1) 21 22 // modules 23 private val fdiv = Module(new VectorFloatDivider) 24 25 val fp_aIsFpCanonicalNAN = fp_fmt === VSew.e32 && !src1.head(32).andR || 26 fp_fmt === VSew.e16 && !src1.head(48).andR 27 val fp_bIsFpCanonicalNAN = fp_fmt === VSew.e32 && !src0.head(32).andR || 28 fp_fmt === VSew.e16 && !src0.head(48).andR 29 30 val thisRobIdx = Wire(new RobPtr) 31 when(io.in.ready){ 32 thisRobIdx := io.in.bits.ctrl.robIdx 33 }.otherwise{ 34 thisRobIdx := outCtrl.robIdx 35 } 36 37 fdiv.io.start_valid_i := io.in.valid 38 fdiv.io.finish_ready_i := io.out.ready & io.out.valid 39 fdiv.io.flush_i := thisRobIdx.needFlush(io.flush) 40 fdiv.io.fp_format_i := fp_fmt 41 fdiv.io.opa_i := src1 42 fdiv.io.opb_i := src0 43 fdiv.io.frs2_i := 0.U 44 fdiv.io.frs1_i := 0.U 45 fdiv.io.is_frs2_i := false.B 46 fdiv.io.is_frs1_i := false.B 47 fdiv.io.is_sqrt_i := opcode 48 fdiv.io.rm_i := rm 49 fdiv.io.is_vec_i := false.B 50 fdiv.io.fp_aIsFpCanonicalNAN := fp_aIsFpCanonicalNAN 51 fdiv.io.fp_bIsFpCanonicalNAN := fp_bIsFpCanonicalNAN 52 53 private val resultData = fdiv.io.fpdiv_res_o 54 private val fflagsData = fdiv.io.fflags_o 55 56 io.in.ready := fdiv.io.start_ready_o 57 io.out.valid := fdiv.io.finish_valid_o 58 59 io.out.bits.res.fflags.get := fflagsData 60 io.out.bits.res.data := resultData 61} 62