1package xiangshan.backend.fu.wrapper 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import utils.XSError 7import xiangshan.backend.fu.FuConfig 8import xiangshan.backend.fu.vector.Bundles.VSew 9import xiangshan.backend.fu.fpu.FpPipedFuncUnit 10import yunsuan.{VfaluType, VfpuType} 11import yunsuan.vector.VectorFloatAdder 12 13class FAlu(cfg: FuConfig)(implicit p: Parameters) extends FpPipedFuncUnit(cfg) { 14 XSError(io.in.valid && io.in.bits.ctrl.fuOpType === VfpuType.dummy, "falu OpType not supported") 15 16 // io alias 17 private val opcode = fuOpType(4, 0) 18 private val src0 = inData.src(0) 19 private val src1 = inData.src(1) 20 21 // modules 22 private val falu = Module(new VectorFloatAdder) 23 24 val fp_aIsFpCanonicalNAN = fp_fmt === VSew.e32 && !src1.head(32).andR || 25 fp_fmt === VSew.e16 && !src1.head(48).andR 26 val fp_bIsFpCanonicalNAN = fp_fmt === VSew.e32 && !src0.head(32).andR || 27 fp_fmt === VSew.e16 && !src0.head(48).andR 28 29 falu.io.fire := io.in.valid 30 falu.io.fp_a := src1 31 falu.io.fp_b := src0 32 falu.io.widen_a := 0.U 33 falu.io.widen_b := 0.U 34 falu.io.frs1 := 0.U 35 falu.io.is_frs1 := false.B 36 falu.io.mask := "b1111".U 37 falu.io.maskForReduction := 0.U 38 falu.io.uop_idx := 0.U 39 falu.io.is_vec := false.B 40 falu.io.round_mode := rm 41 falu.io.fp_format := fp_fmt 42 falu.io.opb_widening := false.B 43 falu.io.res_widening := false.B 44 falu.io.op_code := opcode 45 falu.io.is_vfwredosum := false.B 46 falu.io.is_fold := false.B 47 falu.io.vs2_fold := 0.U 48 falu.io.fp_aIsFpCanonicalNAN := fp_aIsFpCanonicalNAN 49 falu.io.fp_bIsFpCanonicalNAN := fp_bIsFpCanonicalNAN 50 51 private val resultData = falu.io.fp_result 52 private val fflagsData = falu.io.fflags 53 54 io.out.bits.res.fflags.get := fflagsData 55 io.out.bits.res.data := resultData 56} 57