1package xiangshan.backend.fu.wrapper 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util.RegEnable 6import utility.{SignExt, ZeroExt} 7import xiangshan.DIVOpType 8import xiangshan.backend.fu.{FuncUnit, MulDivCtrl, SRT16DividerDataModule} 9import xiangshan.backend.fu.FuConfig 10 11class DivUnit(cfg: FuConfig)(implicit p: Parameters) extends FuncUnit(cfg) { 12 13 val xlen = cfg.destDataBits 14 15 val func = io.in.bits.ctrl.fuOpType 16 val ctrl = Wire(new MulDivCtrl) 17 ctrl.isW := DIVOpType.isW(func) 18 ctrl.isHi := DIVOpType.isH(func) 19 ctrl.sign := DIVOpType.isSign(func) 20 21 val divInputCvtFunc: UInt => UInt = (x: UInt) => Mux( 22 ctrl.isW, 23 Mux(ctrl.sign, 24 SignExt(x(31, 0), xlen), 25 ZeroExt(x(31, 0), xlen) 26 ), 27 x 28 ) 29 30 val robIdxReg = RegEnable(io.in.bits.ctrl.robIdx, io.in.fire) 31 val ctrlReg = RegEnable(ctrl, io.in.fire) 32 33 val divDataModule = Module(new SRT16DividerDataModule(cfg.destDataBits)) 34 35 val kill_w = io.in.bits.ctrl.robIdx.needFlush(io.flush) 36 val kill_r = !divDataModule.io.in_ready && robIdxReg.needFlush(io.flush) 37 38 divDataModule.io.valid := io.in.valid 39 divDataModule.io.src(0) := divInputCvtFunc(io.in.bits.data.src(0)) 40 divDataModule.io.src(1) := divInputCvtFunc(io.in.bits.data.src(1)) 41 divDataModule.io.sign := ctrl.sign 42 divDataModule.io.kill_w := kill_w 43 divDataModule.io.kill_r := kill_r 44 divDataModule.io.isHi := ctrlReg.isHi 45 divDataModule.io.isW := ctrlReg.isW 46 divDataModule.io.out_ready := io.out.ready 47 48 val validNext = divDataModule.io.out_validNext // if high, io.valid will assert next cycle 49 50 io.in.ready := divDataModule.io.in_ready 51 io.out.valid := divDataModule.io.out_valid 52 io.out.bits.res.data := divDataModule.io.out_data 53 connectNonPipedCtrlSingal 54} 55