1package xiangshan.backend.fu.wrapper 2 3import chisel3._ 4import chisel3.util._ 5import org.chipsalliance.cde.config.Parameters 6import utility._ 7import xiangshan._ 8import xiangshan.backend.fu.NewCSR._ 9import xiangshan.backend.fu.util._ 10import xiangshan.backend.fu.{FuConfig, FuncUnit} 11import device._ 12import system.HasSoCParameter 13import xiangshan.ExceptionNO._ 14import xiangshan.backend.Bundles.TrapInstInfo 15import xiangshan.backend.decode.Imm_Z 16import xiangshan.backend.fu.NewCSR.CSRBundles.PrivState 17import xiangshan.backend.fu.NewCSR.CSRDefines.PrivMode 18import xiangshan.frontend.FtqPtr 19 20class CSR(cfg: FuConfig)(implicit p: Parameters) extends FuncUnit(cfg) 21 with HasCircularQueuePtrHelper with HasCriticalErrors 22{ 23 val csrIn = io.csrio.get 24 val csrOut = io.csrio.get 25 val csrToDecode = io.csrToDecode.get 26 27 val setFsDirty = csrIn.fpu.dirty_fs 28 val setFflags = csrIn.fpu.fflags 29 30 val setVsDirty = csrIn.vpu.dirty_vs 31 val setVstart = csrIn.vpu.set_vstart 32 val setVtype = csrIn.vpu.set_vtype 33 val setVxsat = csrIn.vpu.set_vxsat 34 val vlFromPreg = csrIn.vpu.vl 35 36 val flushPipe = Wire(Bool()) 37 val flush = io.flush.valid 38 39 /** Alias of input signals */ 40 val (valid, src1, imm, func) = ( 41 io.in.valid, 42 io.in.bits.data.src(0), 43 io.in.bits.data.imm(Imm_Z().len - 1, 0), 44 io.in.bits.ctrl.fuOpType 45 ) 46 47 // split imm/src1/rd from IMM_Z: src1/rd for tval 48 val addr = Imm_Z().getCSRAddr(imm) 49 val rd = Imm_Z().getRD(imm) 50 val rs1 = Imm_Z().getRS1(imm) 51 val imm5 = Imm_Z().getImm5(imm) 52 val csri = ZeroExt(imm5, XLEN) 53 54 import CSRConst._ 55 56 private val isEcall = CSROpType.isSystemOp(func) && addr === privEcall 57 private val isEbreak = CSROpType.isSystemOp(func) && addr === privEbreak 58 private val isMNret = CSROpType.isSystemOp(func) && addr === privMNret 59 private val isMret = CSROpType.isSystemOp(func) && addr === privMret 60 private val isSret = CSROpType.isSystemOp(func) && addr === privSret 61 private val isDret = CSROpType.isSystemOp(func) && addr === privDret 62 private val isWfi = CSROpType.isWfi(func) 63 private val isCSRAcc = CSROpType.isCsrAccess(func) 64 65 val csrMod = Module(new NewCSR) 66 val trapInstMod = Module(new TrapInstMod) 67 val trapTvalMod = Module(new TrapTvalMod) 68 69 private val privState = csrMod.io.status.privState 70 // The real reg value in CSR, with no read mask 71 private val regOut = csrMod.io.out.bits.regOut 72 private val src = Mux(CSROpType.needImm(func), csri, src1) 73 private val wdata = LookupTree(func, Seq( 74 CSROpType.wrt -> src1, 75 CSROpType.set -> (regOut | src1), 76 CSROpType.clr -> (regOut & (~src1).asUInt), 77 CSROpType.wrti -> csri, 78 CSROpType.seti -> (regOut | csri), 79 CSROpType.clri -> (regOut & (~csri).asUInt), 80 )) 81 82 private val csrAccess = valid && CSROpType.isCsrAccess(func) 83 private val csrWen = valid && ( 84 CSROpType.isCSRRW(func) || 85 CSROpType.isCSRRSorRC(func) && rs1 =/= 0.U 86 ) 87 private val csrRen = valid && ( 88 CSROpType.isCSRRW(func) && rd =/= 0.U || 89 CSROpType.isCSRRSorRC(func) 90 ) 91 92 private val waddrReg = RegEnable(addr, 0.U(12.W), io.in.fire) 93 private val wdataReg = RegEnable(wdata, 0.U(64.W), io.in.fire) 94 95 csrMod.io.in match { 96 case in => 97 in.valid := valid 98 in.bits.wen := csrWen 99 in.bits.ren := csrRen 100 in.bits.op := CSROpType.getCSROp(func) 101 in.bits.addr := addr 102 in.bits.waddrReg := waddrReg 103 in.bits.src := src 104 in.bits.wdata := wdataReg 105 in.bits.mret := isMret 106 in.bits.mnret := isMNret 107 in.bits.sret := isSret 108 in.bits.dret := isDret 109 } 110 csrMod.io.trapInst := trapInstMod.io.currentTrapInst 111 csrMod.io.fetchMalTval := trapTvalMod.io.tval 112 csrMod.io.fromMem.excpVA := csrIn.memExceptionVAddr 113 csrMod.io.fromMem.excpGPA := csrIn.memExceptionGPAddr 114 csrMod.io.fromMem.excpIsForVSnonLeafPTE := csrIn.memExceptionIsForVSnonLeafPTE 115 116 csrMod.io.fromRob.trap.valid := csrIn.exception.valid 117 csrMod.io.fromRob.trap.bits.pc := csrIn.exception.bits.pc 118 csrMod.io.fromRob.trap.bits.instr := csrIn.exception.bits.instr 119 csrMod.io.fromRob.trap.bits.pcGPA := csrIn.exception.bits.gpaddr 120 // Todo: shrink the width of trap vector. 121 // We use 64bits trap vector in CSR, and 24 bits exceptionVec in exception bundle. 122 csrMod.io.fromRob.trap.bits.trapVec := csrIn.exception.bits.exceptionVec.asUInt 123 csrMod.io.fromRob.trap.bits.isFetchBkpt := csrIn.exception.bits.isPcBkpt 124 csrMod.io.fromRob.trap.bits.singleStep := csrIn.exception.bits.singleStep 125 csrMod.io.fromRob.trap.bits.crossPageIPFFix := csrIn.exception.bits.crossPageIPFFix 126 csrMod.io.fromRob.trap.bits.isInterrupt := csrIn.exception.bits.isInterrupt 127 csrMod.io.fromRob.trap.bits.trigger := csrIn.exception.bits.trigger 128 csrMod.io.fromRob.trap.bits.isHls := csrIn.exception.bits.isHls 129 csrMod.io.fromRob.trap.bits.isFetchMalAddr := csrIn.exception.bits.isFetchMalAddr 130 csrMod.io.fromRob.trap.bits.isForVSnonLeafPTE := csrIn.exception.bits.isForVSnonLeafPTE 131 132 csrMod.io.fromRob.commit.fflags := setFflags 133 csrMod.io.fromRob.commit.fsDirty := setFsDirty 134 csrMod.io.fromRob.commit.vxsat.valid := setVxsat.valid 135 csrMod.io.fromRob.commit.vxsat.bits := setVxsat.bits 136 csrMod.io.fromRob.commit.vsDirty := setVsDirty 137 csrMod.io.fromRob.commit.vstart := setVstart 138 csrMod.io.fromRob.commit.vl := vlFromPreg 139 // Todo: correct vtype 140 csrMod.io.fromRob.commit.vtype.valid := setVtype.valid 141 csrMod.io.fromRob.commit.vtype.bits.VILL := setVtype.bits(XLEN - 1) 142 csrMod.io.fromRob.commit.vtype.bits.VMA := setVtype.bits(7) 143 csrMod.io.fromRob.commit.vtype.bits.VTA := setVtype.bits(6) 144 csrMod.io.fromRob.commit.vtype.bits.VSEW := setVtype.bits(5, 3) 145 csrMod.io.fromRob.commit.vtype.bits.VLMUL := setVtype.bits(2, 0) 146 147 csrMod.io.fromRob.commit.instNum.valid := true.B // Todo: valid control signal 148 csrMod.io.fromRob.commit.instNum.bits := csrIn.perf.retiredInstr 149 150 csrMod.io.fromRob.robDeqPtr := csrIn.robDeqPtr 151 152 csrMod.io.fromVecExcpMod.busy := io.csrin.get.fromVecExcpMod.busy 153 154 csrMod.io.perf := csrIn.perf 155 156 csrMod.platformIRP.MEIP := csrIn.externalInterrupt.meip 157 csrMod.platformIRP.MTIP := csrIn.externalInterrupt.mtip 158 csrMod.platformIRP.MSIP := csrIn.externalInterrupt.msip 159 csrMod.platformIRP.SEIP := csrIn.externalInterrupt.seip 160 csrMod.platformIRP.STIP := false.B 161 csrMod.platformIRP.VSEIP := false.B // Todo 162 csrMod.platformIRP.VSTIP := false.B // Todo 163 csrMod.platformIRP.debugIP := csrIn.externalInterrupt.debug 164 csrMod.nonMaskableIRP.NMI_43 := csrIn.externalInterrupt.nmi.nmi_43 165 csrMod.nonMaskableIRP.NMI_31 := csrIn.externalInterrupt.nmi.nmi_31 166 167 csrMod.io.fromTop.hartId := io.csrin.get.hartId 168 csrMod.io.fromTop.clintTime := io.csrin.get.clintTime 169 csrMod.io.fromTop.criticalErrorState := io.csrin.get.criticalErrorState 170 private val csrModOutValid = csrMod.io.out.valid 171 private val csrModOut = csrMod.io.out.bits 172 173 trapInstMod.io.fromDecode.trapInstInfo := RegNextWithEnable(io.csrin.get.trapInstInfo, hasInit = true) 174 trapInstMod.io.fromRob.flush.valid := io.flush.valid 175 trapInstMod.io.fromRob.flush.bits.ftqPtr := io.flush.bits.ftqIdx 176 trapInstMod.io.fromRob.flush.bits.ftqOffset := io.flush.bits.ftqOffset 177 trapInstMod.io.faultCsrUop.valid := csrMod.io.out.valid && (csrMod.io.out.bits.EX_II || csrMod.io.out.bits.EX_VI) 178 trapInstMod.io.faultCsrUop.bits.fuOpType := DataHoldBypass(io.in.bits.ctrl.fuOpType, io.in.fire) 179 trapInstMod.io.faultCsrUop.bits.imm := DataHoldBypass(io.in.bits.data.imm, io.in.fire) 180 trapInstMod.io.faultCsrUop.bits.ftqInfo.ftqPtr := DataHoldBypass(io.in.bits.ctrl.ftqIdx.get, io.in.fire) 181 trapInstMod.io.faultCsrUop.bits.ftqInfo.ftqOffset := DataHoldBypass(io.in.bits.ctrl.ftqOffset.get, io.in.fire) 182 // Clear trap instruction when instruction fault trap(EX_II, EX_VI) occurs. 183 trapInstMod.io.readClear := (csrMod.io.fromRob.trap match { 184 case t => 185 t.valid && !t.bits.isInterrupt && (t.bits.trapVec(EX_II) || t.bits.trapVec(EX_VI)) 186 }) 187 188 trapTvalMod.io.targetPc.valid := csrMod.io.out.bits.targetPcUpdate 189 trapTvalMod.io.targetPc.bits := csrMod.io.out.bits.targetPc 190 trapTvalMod.io.clear := csrIn.exception.valid && csrIn.exception.bits.isFetchMalAddr 191 trapTvalMod.io.fromCtrlBlock.flush := io.flush 192 trapTvalMod.io.fromCtrlBlock.robDeqPtr := io.csrio.get.robDeqPtr 193 194 private val imsic = Module(new IMSIC(NumVSIRFiles = 5, NumHart = 1, XLEN = 64, NumIRSrc = 256)) 195 imsic.i.hartId := io.csrin.get.hartId 196 imsic.i.msiInfo := io.csrin.get.msiInfo 197 imsic.i.csr.addr.valid := csrMod.toAIA.addr.valid 198 imsic.i.csr.addr.bits.addr := csrMod.toAIA.addr.bits.addr 199 imsic.i.csr.addr.bits.prvm := csrMod.toAIA.addr.bits.prvm.asUInt 200 imsic.i.csr.addr.bits.v := csrMod.toAIA.addr.bits.v.asUInt 201 imsic.i.csr.vgein := csrMod.toAIA.vgein 202 imsic.i.csr.mClaim := csrMod.toAIA.mClaim 203 imsic.i.csr.sClaim := csrMod.toAIA.sClaim 204 imsic.i.csr.vsClaim := csrMod.toAIA.vsClaim 205 imsic.i.csr.wdata.valid := csrMod.toAIA.wdata.valid 206 imsic.i.csr.wdata.bits.op := csrMod.toAIA.wdata.bits.op 207 imsic.i.csr.wdata.bits.data := csrMod.toAIA.wdata.bits.data 208 209 csrMod.fromAIA.rdata.valid := imsic.o.csr.rdata.valid 210 csrMod.fromAIA.rdata.bits.data := imsic.o.csr.rdata.bits.rdata 211 csrMod.fromAIA.rdata.bits.illegal := imsic.o.csr.rdata.bits.illegal 212 csrMod.fromAIA.meip := imsic.o.meip 213 csrMod.fromAIA.seip := imsic.o.seip 214 csrMod.fromAIA.vseip := imsic.o.vseip 215 csrMod.fromAIA.mtopei := imsic.o.mtopei 216 csrMod.fromAIA.stopei := imsic.o.stopei 217 csrMod.fromAIA.vstopei := imsic.o.vstopei 218 219 private val exceptionVec = WireInit(0.U.asTypeOf(ExceptionVec())) // Todo: 220 221 exceptionVec(EX_BP ) := DataHoldBypass(isEbreak, false.B, io.in.fire) 222 exceptionVec(EX_MCALL ) := DataHoldBypass(isEcall && privState.isModeM, false.B, io.in.fire) 223 exceptionVec(EX_HSCALL) := DataHoldBypass(isEcall && privState.isModeHS, false.B, io.in.fire) 224 exceptionVec(EX_VSCALL) := DataHoldBypass(isEcall && privState.isModeVS, false.B, io.in.fire) 225 exceptionVec(EX_UCALL ) := DataHoldBypass(isEcall && privState.isModeHUorVU, false.B, io.in.fire) 226 exceptionVec(EX_II ) := csrMod.io.out.bits.EX_II 227 exceptionVec(EX_VI ) := csrMod.io.out.bits.EX_VI 228 229 val isXRet = valid && func === CSROpType.jmp && !isEcall && !isEbreak 230 231 // ctrl block will use theses later for flush // Todo: optimize isXRetFlag's DelayN 232 val isXRetFlag = RegInit(false.B) 233 isXRetFlag := Mux1H(Seq( 234 DelayN(flush, 5) -> false.B, 235 isXRet -> true.B, 236 )) 237 238 flushPipe := csrMod.io.out.bits.flushPipe 239 240 // tlb 241 val tlb = Wire(new TlbCsrBundle) 242 tlb.satp.changed := csrMod.io.tlb.satpASIDChanged 243 tlb.satp.mode := csrMod.io.tlb.satp.MODE.asUInt 244 tlb.satp.asid := csrMod.io.tlb.satp.ASID.asUInt 245 tlb.satp.ppn := csrMod.io.tlb.satp.PPN.asUInt 246 tlb.vsatp.changed := csrMod.io.tlb.vsatpASIDChanged 247 tlb.vsatp.mode := csrMod.io.tlb.vsatp.MODE.asUInt 248 tlb.vsatp.asid := csrMod.io.tlb.vsatp.ASID.asUInt 249 tlb.vsatp.ppn := csrMod.io.tlb.vsatp.PPN.asUInt 250 tlb.hgatp.changed := csrMod.io.tlb.hgatpVMIDChanged 251 tlb.hgatp.mode := csrMod.io.tlb.hgatp.MODE.asUInt 252 tlb.hgatp.vmid := csrMod.io.tlb.hgatp.VMID.asUInt 253 tlb.hgatp.ppn := csrMod.io.tlb.hgatp.PPN.asUInt 254 255 // expose several csr bits for tlb 256 tlb.priv.mxr := csrMod.io.tlb.mxr 257 tlb.priv.sum := csrMod.io.tlb.sum 258 tlb.priv.vmxr := csrMod.io.tlb.vmxr 259 tlb.priv.vsum := csrMod.io.tlb.vsum 260 tlb.priv.spvp := csrMod.io.tlb.spvp 261 tlb.priv.virt := csrMod.io.tlb.dvirt 262 tlb.priv.imode := csrMod.io.tlb.imode 263 tlb.priv.dmode := csrMod.io.tlb.dmode 264 265 // Svpbmt extension enable 266 tlb.mPBMTE := csrMod.io.tlb.mPBMTE 267 tlb.hPBMTE := csrMod.io.tlb.hPBMTE 268 269 /** Since some CSR read instructions are allowed to be pipelined, ready/valid signals should be modified */ 270 io.in.ready := csrMod.io.in.ready // Todo: Async read imsic may block CSR 271 io.out.valid := csrModOutValid 272 io.out.bits.ctrl.exceptionVec.get := exceptionVec 273 io.out.bits.ctrl.flushPipe.get := flushPipe 274 io.out.bits.res.data := csrMod.io.out.bits.rData 275 276 /** initialize NewCSR's io_out_ready from wrapper's io */ 277 csrMod.io.out.ready := io.out.ready 278 279 io.out.bits.res.redirect.get.valid := io.out.valid && RegEnable(isXRet, false.B, io.in.fire) 280 val redirect = io.out.bits.res.redirect.get.bits 281 redirect := 0.U.asTypeOf(redirect) 282 redirect.level := RedirectLevel.flushAfter 283 redirect.robIdx := RegEnable(io.in.bits.ctrl.robIdx, io.in.fire) 284 redirect.ftqIdx := RegEnable(io.in.bits.ctrl.ftqIdx.get, io.in.fire) 285 redirect.ftqOffset := RegEnable(io.in.bits.ctrl.ftqOffset.get, io.in.fire) 286 redirect.cfiUpdate.predTaken := true.B 287 redirect.cfiUpdate.taken := true.B 288 redirect.cfiUpdate.target := csrMod.io.out.bits.targetPc.pc 289 redirect.cfiUpdate.backendIPF := csrMod.io.out.bits.targetPc.raiseIPF 290 redirect.cfiUpdate.backendIAF := csrMod.io.out.bits.targetPc.raiseIAF 291 redirect.cfiUpdate.backendIGPF := csrMod.io.out.bits.targetPc.raiseIGPF 292 // Only mispred will send redirect to frontend 293 redirect.cfiUpdate.isMisPred := true.B 294 295 connectNonPipedCtrlSingal 296 297 override val criticalErrors = csrMod.getCriticalErrors 298 generateCriticalErrors() 299 300 // Todo: summerize all difftest skip condition 301 csrOut.isPerfCnt := io.out.valid && csrMod.io.out.bits.isPerfCnt && RegEnable(func =/= CSROpType.jmp, false.B, io.in.fire) 302 csrOut.fpu.frm := csrMod.io.status.fpState.frm.asUInt 303 csrOut.vpu.vstart := csrMod.io.status.vecState.vstart.asUInt 304 csrOut.vpu.vxrm := csrMod.io.status.vecState.vxrm.asUInt 305 306 csrOut.isXRet := RegEnable(isXRetFlag, false.B, io.in.fire) 307 308 csrOut.trapTarget := csrMod.io.out.bits.targetPc 309 csrOut.interrupt := csrMod.io.status.interrupt 310 csrOut.wfi_event := csrMod.io.status.wfiEvent 311 312 csrOut.tlb := tlb 313 314 csrOut.debugMode := csrMod.io.status.debugMode 315 316 csrOut.customCtrl match { 317 case custom => 318 custom.l1I_pf_enable := csrMod.io.status.custom.l1I_pf_enable 319 custom.l2_pf_enable := csrMod.io.status.custom.l2_pf_enable 320 custom.l1D_pf_enable := csrMod.io.status.custom.l1D_pf_enable 321 custom.l1D_pf_train_on_hit := csrMod.io.status.custom.l1D_pf_train_on_hit 322 custom.l1D_pf_enable_agt := csrMod.io.status.custom.l1D_pf_enable_agt 323 custom.l1D_pf_enable_pht := csrMod.io.status.custom.l1D_pf_enable_pht 324 custom.l1D_pf_active_threshold := csrMod.io.status.custom.l1D_pf_active_threshold 325 custom.l1D_pf_active_stride := csrMod.io.status.custom.l1D_pf_active_stride 326 custom.l1D_pf_enable_stride := csrMod.io.status.custom.l1D_pf_enable_stride 327 custom.l2_pf_store_only := csrMod.io.status.custom.l2_pf_store_only 328 // ICache 329 custom.icache_parity_enable := csrMod.io.status.custom.icache_parity_enable 330 // Load violation predictor 331 custom.lvpred_disable := csrMod.io.status.custom.lvpred_disable 332 custom.no_spec_load := csrMod.io.status.custom.no_spec_load 333 custom.storeset_wait_store := csrMod.io.status.custom.storeset_wait_store 334 custom.storeset_no_fast_wakeup := csrMod.io.status.custom.storeset_no_fast_wakeup 335 custom.lvpred_timeout := csrMod.io.status.custom.lvpred_timeout 336 // Branch predictor 337 custom.bp_ctrl := csrMod.io.status.custom.bp_ctrl 338 // Memory Block 339 custom.sbuffer_threshold := csrMod.io.status.custom.sbuffer_threshold 340 custom.ldld_vio_check_enable := csrMod.io.status.custom.ldld_vio_check_enable 341 custom.soft_prefetch_enable := csrMod.io.status.custom.soft_prefetch_enable 342 custom.cache_error_enable := csrMod.io.status.custom.cache_error_enable 343 custom.uncache_write_outstanding_enable := csrMod.io.status.custom.uncache_write_outstanding_enable 344 custom.hd_misalign_st_enable := csrMod.io.status.custom.hd_misalign_st_enable 345 custom.hd_misalign_ld_enable := csrMod.io.status.custom.hd_misalign_ld_enable 346 // Rename 347 custom.fusion_enable := csrMod.io.status.custom.fusion_enable 348 custom.wfi_enable := csrMod.io.status.custom.wfi_enable 349 // distribute csr write signal 350 // write to frontend and memory 351 custom.distribute_csr.w.valid := csrMod.io.distributedWenLegal 352 custom.distribute_csr.w.bits.addr := waddrReg 353 custom.distribute_csr.w.bits.data := wdataReg 354 // rename single step 355 custom.singlestep := csrMod.io.status.singleStepFlag 356 // trigger 357 custom.frontend_trigger := csrMod.io.status.frontendTrigger 358 custom.mem_trigger := csrMod.io.status.memTrigger 359 // virtual mode 360 custom.virtMode := csrMod.io.status.privState.V.asBool 361 // xstatus.fs field is off 362 custom.fsIsOff := csrMod.io.toDecode.illegalInst.fsIsOff 363 } 364 365 csrOut.instrAddrTransType := csrMod.io.status.instrAddrTransType 366 csrOut.criticalErrorState := csrMod.io.status.criticalErrorState 367 368 csrToDecode := csrMod.io.toDecode 369} 370 371class CSRInput(implicit p: Parameters) extends XSBundle with HasSoCParameter{ 372 val hartId = Input(UInt(8.W)) 373 val msiInfo = Input(ValidIO(new MsiInfoBundle)) 374 val criticalErrorState = Input(Bool()) 375 val clintTime = Input(ValidIO(UInt(64.W))) 376 val trapInstInfo = Input(ValidIO(new TrapInstInfo)) 377 val fromVecExcpMod = Input(new Bundle { 378 val busy = Bool() 379 }) 380} 381 382class CSRToDecode(implicit p: Parameters) extends XSBundle { 383 val illegalInst = new Bundle { 384 /** 385 * illegal sfence.vma, sinval.vma 386 * raise EX_II when isModeHS && mstatus.TVM=1 || isModeHU 387 */ 388 val sfenceVMA = Bool() 389 390 /** 391 * illegal sfence.w.inval sfence.inval.ir 392 * raise EX_II when isModeHU 393 */ 394 val sfencePart = Bool() 395 396 /** 397 * illegal hfence.gvma, hinval.gvma 398 * raise EX_II when isModeHS && mstatus.TVM=1 || isModeHU 399 * the condition is the same as sfenceVMA 400 */ 401 val hfenceGVMA = Bool() 402 403 /** 404 * illegal hfence.vvma, hinval.vvma 405 * raise EX_II when isModeHU 406 */ 407 val hfenceVVMA = Bool() 408 409 /** 410 * illegal hlv, hlvx, and hsv 411 * raise EX_II when isModeHU && hstatus.HU=0 412 */ 413 val hlsv = Bool() 414 415 /** 416 * decode all fp inst or all vecfp inst 417 * raise EX_II when FS=Off 418 */ 419 val fsIsOff = Bool() 420 421 /** 422 * decode all vec inst 423 * raise EX_II when VS=Off 424 */ 425 val vsIsOff = Bool() 426 427 /** 428 * illegal wfi 429 * raise EX_II when isModeHU || !isModeM && mstatus.TW=1 430 */ 431 val wfi = Bool() 432 433 /** 434 * frm reserved 435 * raise EX_II when frm.data > 4 436 */ 437 val frm = Bool() 438 439 /** 440 * illegal CBO.ZERO 441 * raise [[EX_II]] when !isModeM && !MEnvCfg.CBZE || isModeHU && !SEnvCfg.CBZE 442 */ 443 val cboZ = Bool() 444 445 /** 446 * illegal CBO.CLEAN/FLUSH 447 * raise [[EX_II]] when !isModeM && !MEnvCfg.CBCFE || isModeHU && !SEnvCfg.CBCFE 448 */ 449 val cboCF = Bool() 450 451 /** 452 * illegal CBO.INVAL 453 * raise [[EX_II]] when !isModeM && MEnvCfg.CBIE = EnvCBIE.Off || isModeHU && SEnvCfg.CBIE = EnvCBIE.Off 454 */ 455 val cboI = Bool() 456 } 457 458 val virtualInst = new Bundle { 459 /** 460 * illegal sfence.vma, svinval.vma 461 * raise EX_VI when isModeVS && hstatus.VTVM=1 || isModeVU 462 */ 463 val sfenceVMA = Bool() 464 465 /** 466 * illegal sfence.w.inval sfence.inval.ir 467 * raise EX_VI when isModeVU 468 */ 469 val sfencePart = Bool() 470 471 /** 472 * illegal hfence.gvma, hinval.gvma, hfence.vvma, hinval.vvma 473 * raise EX_VI when isModeVS || isModeVU 474 */ 475 val hfence = Bool() 476 477 /** 478 * illegal hlv, hlvx, and hsv 479 * raise EX_VI when isModeVS || isModeVU 480 */ 481 val hlsv = Bool() 482 483 /** 484 * illegal wfi 485 * raise EX_VI when isModeVU && mstatus.TW=0 || isModeVS && mstatus.TW=0 && hstatus.VTW=1 486 */ 487 val wfi = Bool() 488 489 /** 490 * illegal CBO.ZERO 491 * raise [[EX_VI]] when MEnvCfg.CBZE && (isModeVS && !HEnvCfg.CBZE || isModeVU && (!HEnvCfg.CBZE || !SEnvCfg.CBZE)) 492 */ 493 val cboZ = Bool() 494 495 /** 496 * illegal CBO.CLEAN/FLUSH 497 * raise [[EX_VI]] when MEnvCfg.CBZE && (isModeVS && !HEnvCfg.CBCFE || isModeVU && (!HEnvCfg.CBCFE || !SEnvCfg.CBCFE)) 498 */ 499 val cboCF = Bool() 500 501 /** 502 * illegal CBO.INVAL <br/> 503 * raise [[EX_VI]] when MEnvCfg.CBIE =/= EnvCBIE.Off && ( <br/> 504 * isModeVS && HEnvCfg.CBIE === EnvCBIE.Off || <br/> 505 * isModeVU && (HEnvCfg.CBIE === EnvCBIE.Off || SEnvCfg.CBIE === EnvCBIE.Off) <br/> 506 * ) <br/> 507 */ 508 val cboI = Bool() 509 } 510 511 val special = new Bundle { 512 /** 513 * execute CBO.INVAL and perform flush operation when <br/> 514 * isModeHS && MEnvCfg.CBIE === EnvCBIE.Flush || <br/> 515 * isModeHU && (MEnvCfg.CBIE === EnvCBIE.Flush || SEnvCfg.CBIE === EnvCBIE.Flush) <br/> 516 * isModeVS && (MEnvCfg.CBIE === EnvCBIE.Flush || HEnvCfg.CBIE === EnvCBIE.Flush) <br/> 517 * isModeVU && (MEnvCfg.CBIE === EnvCBIE.Flush || HEnvCfg.CBIE === EnvCBIE.Flush || SEnvCfg.CBIE === EnvCBIE.Flush) <br/> 518 */ 519 val cboI2F = Bool() 520 } 521}